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Searched refs:_EMU_IFC_VMONALTAVDDRISE_DEFAULT (Results 1 – 25 of 71) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_emu.h487 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
488 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_emu.h487 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
488 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h566 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
567 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h561 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
562 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h566 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
567 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h561 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
562 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h566 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
567 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h639 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
640 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b390f1024gl112.h2715 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
2716 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b390f512gl112.h2715 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
2716 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512il120.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512im64.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512iq100.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512iq64.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gq100.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gq64.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512il112.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b110f1024gm64.h3546 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3547 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b110f1024gq64.h3546 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3547 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gl112.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gl120.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b530f512gm64.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gq100.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
Defm32gg12b510f1024gq64.h3554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
3555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h647 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL … macro
648 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3…

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