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Searched refs:_EMU_IFC_DCDCINBYPASS_DEFAULT (Results 1 – 25 of 71) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_emu.h542 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
543 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_emu.h542 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
543 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h621 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
622 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h616 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
617 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h621 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
622 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h616 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
617 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h621 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
622 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h709 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
710 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b390f1024gl112.h2785 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
2786 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b390f512gl112.h2785 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
2786 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512il120.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512im64.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512iq100.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512iq64.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512gq100.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512gq64.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512il112.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b110f1024gm64.h3616 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3617 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b110f1024gq64.h3616 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3617 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512gl112.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512gl120.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b530f512gm64.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b510f1024gq100.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
Defm32gg12b510f1024gq64.h3624 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
3625 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h717 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL … macro
718 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) …

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