Home
last modified time | relevance | path

Searched refs:_EMU_DCDCMISCCTRL_PFETCNT_MASK (Results 1 – 25 of 73) sorted by relevance

123

/hal_silabs-latest/gecko/emlib/src/
Dem_emu.c621 & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); in dcdcFetCntSet()
2398 pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) in currentLimitersUpdate()
3243 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK in EMU_DCDCOptimizeSlice()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_emu.c626 & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); in dcdcFetCntSet()
2453 pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) in currentLimitersUpdate()
3298 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK in EMU_DCDCOptimizeSlice()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_emu.h748 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_emu.h748 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h866 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h849 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h866 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h849 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h866 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h977 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b390f1024gl112.h3053 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b390f512gl112.h3053 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512il120.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512im64.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512iq100.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512iq64.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512gq100.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512gq64.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512il112.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b110f1024gm64.h3884 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b110f1024gq64.h3884 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512gl112.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512gl120.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
Defm32gg12b530f512gm64.h3892 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h985 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL … macro

123