Home
last modified time | relevance | path

Searched refs:_EMU_DCDCLPVCTRL_LPATT_DIV8 (Results 1 – 25 of 71) sorted by relevance

123

/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_emu.h883 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mo… macro
886 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Sh…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_emu.h883 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mo… macro
886 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Sh…
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h976 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
979 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h959 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
962 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h976 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
979 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h959 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
962 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h976 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
979 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h1087 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
1090 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b390f1024gl112.h3163 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
3166 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b390f512gl112.h3163 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
3166 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512il120.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512im64.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512iq100.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512iq64.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512gq100.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512gq64.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512il112.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b110f1024gm64.h3994 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
3997 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b110f1024gq64.h3994 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
3997 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512gl112.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512gl120.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b530f512gm64.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b510f1024gq100.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
Defm32gg12b510f1024gq64.h4002 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
4005 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h1095 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL … macro
1098 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) …

123