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Searched refs:_DMA_CTRLBASE_CTRLBASE_DEFAULT (Results 1 – 25 of 35) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_dma.h144 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
145 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32hg321f32.h504 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
505 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32hg321f64.h504 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
505 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32hg108f32.h550 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
551 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32hg108f64.h550 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
551 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32hg308f32.h562 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
563 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32hg308f64.h562 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
563 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_dma.h152 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
153 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg360f128.h589 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
590 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg360f256.h589 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
590 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg360f64.h589 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
590 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg230f128.h664 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
665 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg230f256.h664 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
665 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg230f64.h664 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
665 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg232f128.h664 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
665 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg232f256.h664 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
665 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg232f64.h664 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
665 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg330f128.h677 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
678 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg330f256.h677 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
678 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg330f64.h677 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
678 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg332f128.h677 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
678 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg332f256.h677 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
678 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg332f64.h677 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
678 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg840f128.h669 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
670 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …
Defm32wg840f256.h669 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< … macro
670 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< …

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