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Searched refs:_CSEN_TIMCTRL_PCPRESC_DIV64 (Results 1 – 8 of 8) sorted by relevance

/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_csen.h270 #define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL … macro
279 #define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) …
/hal_silabs-latest/gecko/emlib/inc/
Dem_csen.h172 csenPCPrescaleDiv64 = _CSEN_TIMCTRL_PCPRESC_DIV64, /**< Divide by 64. */