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Searched refs:_CMU_ADCCTRL_ADC0CLKDIV_MASK (Results 1 – 25 of 66) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_cmu.c7904 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockFreqGet()
7905 ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockFreqGet()
8130 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ in CMU_ClockPrescGet()
8134 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescGet()
8136 ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescGet()
8468 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ in CMU_ClockPrescSet()
8472 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescSet()
8475 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescSet()
/hal_silabs-latest/gecko/emlib/src/
Dem_cmu.c7851 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockFreqGet()
7852 ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockFreqGet()
8077 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ in CMU_ClockPrescGet()
8081 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescGet()
8083 ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescGet()
8415 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ in CMU_ClockPrescSet()
8419 #if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescSet()
8422 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) in CMU_ClockPrescSet()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_cmu.h2365 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b390f1024gl112.h6181 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b390f512gl112.h6181 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512il120.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512im64.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512iq100.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512iq64.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512gq100.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512gq64.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512il112.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b110f1024gm64.h6979 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b110f1024gq64.h6979 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512gl112.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512gl120.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b530f512gm64.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024gq100.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024gq64.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024gl112.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024gl120.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024gm64.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024il112.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
Defm32gg12b510f1024il120.h7010 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_cmu.h2432 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL … macro

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