1 /******************************************************************************
2 * @file system_si91x.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 #include <stdint.h>
31
32 #ifndef __SYSTEM_ARMCM4_H__
33 #define __SYSTEM_ARMCM4_H__
34
35 /**
36 *
37 */
38 #include "rsi_error.h"
39 #include "rsi_ccp_user_config.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
46 extern uint32_t npssIntrState;
47 extern uint32_t __sp;
48 extern uint32_t SiliconRev;
49 extern uint32_t package_type;
50
51 void RSI_PS_ConfigureTaMemories(void);
52 /*WiSeAOC specific VTOR values*/
53 #if defined(WISE_AOC_MODE)
54 #define VECTOR_OFF_SET_TA_ROM (0x100000 + 0x70100) /*<! M4 execution from NWP ROM */
55 #define VECTOR_OFF_SET_M4_ROM (0x300000 + 0xB100) /*<! M4 execution from M4 ROM */
56 #define VECTOR_OFF_SET_TA_ROM_DIRECT (0x80000 + 0x70100) /*<! M4 execution from NWP ROM in directed mode */
57 #endif //WISE_AOC_MODE
58
59 typedef enum SLEEP_TYPE {
60 SLEEP_WITH_RETENTION, /*Saves the CPU context while entering into sleep */
61 SLEEP_WITHOUT_RETENTION, /*do not Save the CPU context while entering into sleep */
62 } SLEEP_TYPE_T;
63
64 #define DISABLE_LF_MODE 0x00
65 #define LF_32_KHZ_RC BIT(0)
66 #define LF_32_KHZ_XTAL BIT(1)
67 #define EXTERNAL_CAP_MODE BIT(2)
68 #define HF_MHZ_RO 3
69 #define BG_SLEEP_TIMER_REG_OFFSET 0x125
70 /*System default clocks*/
71 #define DEFAULT_SOC_PLL_CLOCK 0
72 #define DEFAULT_INTF_PLL_CLOCK 0
73 #define DEFAULT_MODEM_PLL_CLOCK 80000000
74 #define DEFAULT_MHZ_RC_CLOCK 32000000 /* Not recommended to use for applicatios */
75 #define DEFAULT_20MHZ_RO_CLOCK 20000000
76 #define DEFAULT_DOUBLER_CLOCK (2 * DEFAULT_20MHZ_RO_CLOCK)
77 #define DEFAULT_32KHZ_RC_CLOCK 32000
78 #define DEFAULT_32KHZ_RO_CLOCK 32000
79 #define DEFAULT_32KHZ_XTAL_CLOCK 32768
80 #define DEFAULT_40MHZ_CLOCK 40000000
81 #define DEFAULT_MEMS_REF_CLOCK 40000000
82 #define DEFAULT_BYP_RC_CLOCK 32000000
83 #define DEFAULT_I2S_PLL_CLOCK 0
84 #define DEFAULT_REF_CLOCK 2
85
86 /* Selecting the PLL reference clock */
87 /* 0 - XTAL_CLK, 1 - Reserved, 2 - Reserved, 3 - Reserved */
88 #define PLL_REF_CLK_CONFIG_REG (*(volatile uint32_t *)(0x46180000UL + 0x00008000 + 0x04))
89 #define SELECT_RC_MHZ_CLOCK BIT(15)
90 #define SELECT_XTAL_MHZ_CLOCK ~(BIT(14) | BIT(15))
91 #define XTAL_CLK_FREQ 40000000UL
92
93 #define M4SS_P2P_INT_BASE_ADDRESS 0x46008000
94 #ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE
95 #define NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 (*(volatile uint32_t *)(0x41300000 + 0x0))
96 #define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 (*(volatile uint32_t *)(0x41300000 + 0x4))
97 #define MCUAON_CONTROL_REG4 (*(volatile uint32_t *)(0x24048600 + 0x10))
98
99 #define M4SS_TASS_CTRL_SET_REG_VAL (*(volatile uint32_t *)(0x24048400 + 0x34))
100 #define M4SS_TASS_CTRL_CLR_REG_VAL (*(volatile uint32_t *)(0x24048400 + 0x38))
101 #define M4SS_P2P_INTR_CLR_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x170)
102 #define M4SS_REF_CLK_MUX_CTRL BIT(24)
103 #define TASS_REF_CLK_MUX_CTRL BIT(25)
104 #if defined(SLI_SI917) || defined(SLI_SI915)
105 #define MCU_TASS_REF_CLK_SEL_MUX_CTRL BIT(8)
106 #endif
107 #define M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS_BIT BIT(2)
108 #define M4_USING_FLASH BIT(3)
109 #endif
110 #define M4SS_P2P_INTR_SET_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x16C)
111 #define P2P_STATUS_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x174)
112 #define TASS_P2P_INTR_MASK_CLR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x17C)
113
114 #define M4_is_active BIT(1)
115 #define RX_BUFFER_VALID BIT(1)
116
117 #define TA_USING_FLASH BIT(3)
118 #define PROGRAM_COMMON_FLASH BIT(4)
119 #define M4_WAKEUP_TA BIT(0)
120 #define TA_IS_ACTIVE BIT(3)
121 #define TASS_P2P_INTR_CLEAR_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x180)
122
123 /* Flash offset to read Silicon revision */
124 #define TA_FLASH_BASE 0x04000000
125 #ifdef CHIP_9118
126 #define SILICON_REV_WMCU (*(volatile uint32_t *)(TA_FLASH_BASE + 1024 + 55))
127 #define PACKAGE_TYPE_WMCU (*(volatile uint32_t *)(TA_FLASH_BASE + 992 + 86))
128 #endif
129
130 #if defined(SLI_SI917B0) || defined(SLI_SI915)
131 #ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE
132 #define SILICON_REV_WMCU (*(volatile uint32_t *)(SILICON_REV_VALUES_OFFSET_COMMON_FLASH))
133 #define PACKAGE_TYPE_WMCU (*(volatile uint32_t *)(PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH))
134 #else
135 #define SILICON_REV_WMCU (*(volatile uint32_t *)(SILICON_REV_VALUES_OFFSET_DUAL_FLASH))
136 #define PACKAGE_TYPE_WMCU (*(volatile uint32_t *)(PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH))
137 #endif
138 #endif
139
140 #define M4_FLASH_BASE 0x08000000
141 #define SILICON_REV_MCU (*(volatile uint32_t *)(M4_FLASH_BASE + 1024 + 55))
142 #define PACKAGE_TYPE_MCU (*(volatile uint32_t *)(M4_FLASH_BASE + 992 + 86))
143
144 /* Board capabilities */
145 #define SLI_CRYPTOACC_PRESENT_SI91X
146
147 /*XTAL bypass from MCU macros */
148 #define XTAL_IS_IN_SW_CTRL_FROM_M4 0
149 #define XTAL_DISABLE_FROM_M4 0
150
151 /* system clock source look up table*/
152 typedef struct SYSTEM_CLOCK_SOURCE_FREQUENCIES {
153 uint32_t m4ss_ref_clk;
154 uint32_t ulpss_ref_clk;
155 uint32_t soc_pll_clock;
156 uint32_t soc_clock;
157 uint32_t modem_pll_clock;
158 uint32_t intf_pll_clock;
159 uint32_t i2s_pll_clock;
160 uint32_t modem_pll_clock2;
161 uint32_t ro_32khz_clock;
162 uint32_t rc_32khz_clock;
163 uint32_t xtal_32khz_clock;
164 uint32_t rc_mhz_clock;
165 uint32_t ro_20mhz_clock;
166 uint32_t doubler_clock;
167 uint32_t sleep_clock;
168 uint32_t rf_ref_clock;
169 uint32_t mems_ref_clock;
170 uint32_t byp_rc_ref_clock;
171 uint32_t m4_ref_clock_source;
172 uint32_t ulp_ref_clock_source;
173 } SYSTEM_CLOCK_SOURCE_FREQUENCIES_T;
174
175 typedef struct sl_p2p_intr_status_bkp_s {
176 uint32_t tass_p2p_intr_mask_clr_bkp;
177 uint32_t m4ss_p2p_intr_set_reg_bkp;
178 } sl_p2p_intr_status_bkp_t;
179
180 extern SYSTEM_CLOCK_SOURCE_FREQUENCIES_T system_clocks;
181
182 /**
183 * \ingroup RSI_SPECIFIC_DRIVERS
184 */
185
186 /**
187 * \defgroup RSI_SYSTEM_RS1XXXX RSI:SYSTEM RS1XXXX
188 * @{
189 *
190 */
191
192 #define SI91X_EXT_IRQ_COUNT 75 /**< Number of External (NVIC) interrupts of M4*/
193 #define SI91X_RESERVED_IRQ_COUNT 16
194 #define SI91X_VECTOR_TABLE_ENTRIES (SI91X_RESERVED_IRQ_COUNT + SI91X_EXT_IRQ_COUNT)
195
196 typedef union {
197 void (*VECTOR_TABLE_Type)(void);
198 void *topOfStack;
199 } tVectorEntry;
200
201 #ifndef __VECTOR_TABLE
202 #define __VECTOR_TABLE __Vectors
203 #endif
204 #ifndef __VECTOR_TABLE_ATTRIBUTE
205 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".isr_vector")))
206 #endif
207 extern void SystemInit(void);
208
209 extern void SystemCoreClockUpdate(void);
210
SystemCoreClockGet(void)211 static inline uint32_t SystemCoreClockGet(void)
212 {
213 return SystemCoreClock;
214 }
215
216 void RSI_Set_Cntrls_To_M4(void);
217 void RSI_Set_Cntrls_To_TA(void);
218
219 rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode);
220
221 void RSI_PS_SaveCpuContext(void);
222 void RSI_PS_RestoreCpuContext(void);
223 void SystemCoreClockUpdate(void);
224 void fpuInit(void);
225 void RSI_Save_Context(void);
226 void NMI_Handler(void);
227 void HardFault_Handler(void);
228 void MemManage_Handler(void);
229 void BusFault_Handler(void);
230 void UsageFault_Handler(void);
231 void SVC_Handler(void);
232 void DebugMon_Handler(void);
233 void PendSV_Handler(void);
234 void SysTick_Handler(void);
235
236 /*Boot up functions*/
237 void RSI_Default_Reset_Handler(void);
238 void RSI_Default_WakeUp_Handler(void);
239 void RSI_PS_RestoreCpuContext(void);
240
241 void IRQ000_Handler(void); /*!< ULP Processor Interrupt 0 */
242 void IRQ001_Handler(void); /*!< ULP Processor Interrupt 1 */
243 void IRQ002_Handler(void); /*!< ULP Processor Interrupt 2 */
244 void IRQ003_Handler(void); /*!< ULP Processor Interrupt 3 */
245 void IRQ004_Handler(void); /*!< ULP Processor Interrupt 4 */
246 void IRQ005_Handler(void); /*!< ULP Processor Interrupt 5 */
247 void IRQ006_Handler(void); /*!< ULP Processor Interrupt 6 */
248 void IRQ007_Handler(void); /*!< ULP Processor Interrupt 7 */
249 void IRQ008_Handler(void); /*!< ULP Processor Interrupt 8 */
250 void IRQ009_Handler(void); /*!< ULP Processor Interrupt 9 */
251 void IRQ010_Handler(void); /*!< ULP Processor Interrupt 10 */
252 void IRQ011_Handler(void); /*!< ULP Processor Interrupt 11 */
253 void IRQ012_Handler(void); /*!< ULP Processor Interrupt 12 */
254 void IRQ013_Handler(void); /*!< ULP Processor Interrupt 13 */
255 void IRQ014_Handler(void); /*!< ULP Processor Interrupt 14 */
256 void IRQ015_Handler(void); /*!< ULP Processor Interrupt 15 */
257 void IRQ016_Handler(void); /*!< ULP Processor Interrupt 15 */
258 void IRQ017_Handler(void); /*!< ULP Processor Interrupt 17 */
259 void IRQ018_Handler(void); /*!< ULP Processor Interrupt 18 */
260 void IRQ019_Handler(void); /*!< ULP Processor Interrupt 19 */
261 void IRQ020_Handler(void); /*!< Sleep Sensor Interrupts 0 */ /*WDT*/
262 void IRQ021_Handler(void); /*!< Sleep Sensor Interrupts 1 */
263 void IRQ022_Handler(void); /*!< Sleep Sensor Interrupts 2 */
264 void IRQ023_Handler(void); /*!< Sleep Sensor Interrupts 3 */
265 void IRQ024_Handler(void); /*!< Sleep Sensor Interrupts 4 */
266 void IRQ025_Handler(void); /*!< Sleep Sensor Interrupts 5 */
267 void IRQ026_Handler(void); /*!< Sleep Sensor Interrupts 6 */
268 void IRQ027_Handler(void); /*!< Sleep Sensor Interrupts 7 */
269 void IRQ028_Handler(void); /*!< Sleep Sensor Interrupts 8 */ /*Alarm*/
270 void IRQ029_Handler(void); /*!< Sleep Sensor Interrupts 9 */ /*Msec and sec interrupt */
271 void IRQ030_Handler(void); /*!< Reserved */
272 void IRQ031_Handler(void); /*!< M4SS DMA interrupt */
273 void IRQ032_Handler(void); /*!< Reserved */
274 void IRQ033_Handler(void); /*!< M4SS DMA interrupt */
275 void IRQ034_Handler(void); /*!< M4SS SCT interrupt */
276 void HIF1_IRQHandler(void); /*!< HIF Interrupt 1 */
277 void HIF2_IRQHandler(void); /*!< HIF Interrupt 2 */
278 void IRQ037_Handler(void); /*!< SIO Interrupt */
279 void IRQ038_Handler(void); /*!< USART 1 Interrupt */
280 void IRQ039_Handler(void); /*!< Reserved */
281 void IRQ040_Handler(void); /*!< Reserved */
282 void IRQ041_Handler(void); /*!< Reserved */
283 void IRQ042_Handler(void); /*!< I2C Interrupt */
284 void IRQ043_Handler(void); /*!< Reserved */
285 void IRQ044_Handler(void); /*!< SSI Slave Interrupt */
286 void IRQ045_Handler(void); /*!< Reserved */
287 void IRQ046_Handler(void); /*!< GSPI Master 1 Interrupt */
288 void IRQ047_Handler(void); /*!< Reserved */
289 void IRQ048_Handler(void); /*!< MCPWM Interrupt */
290 void IRQ049_Handler(void); /*!< QEI Interrupt */
291 void IRQ050_Handler(void); /*!< GPIO Group Interrupt 0 */
292 void IRQ051_Handler(void); /*!< GPIO Group Interrupt 1 */
293 void IRQ052_Handler(void); /*!< GPIO Pin Interrupt 0 */
294 void IRQ053_Handler(void); /*!< GPIO Pin Interrupt 1 */
295 void IRQ054_Handler(void); /*!< GPIO Pin Interrupt 2 */
296 void IRQ055_Handler(void); /*!< GPIO Pin Interrupt 3 */
297 void IRQ056_Handler(void); /*!< GPIO Pin Interrupt 4 */
298 void IRQ057_Handler(void); /*!< GPIO Pin Interrupt 5 */
299 void IRQ058_Handler(void); /*!< GPIO Pin Interrupt 6 */
300 void IRQ059_Handler(void); /*!< GPIO Pin Interrupt 7 */
301 void IRQ060_Handler(void); /*!< QSPI Interrupt */
302 void IRQ061_Handler(void); /*!< I2C 2 Interrupt */
303 void IRQ062_Handler(void); /*!< Ethernet Interrupt */
304 void IRQ063_Handler(void); /*!< Reserved */
305 void IRQ064_Handler(void); /*!< I2S master Interrupt */
306 void IRQ065_Handler(void); /*!< Reserved */
307 void IRQ066_Handler(void); /*!< Can 1 Interrupt */
308 void IRQ067_Handler(void); /*!< Reserved */
309 void IRQ068_Handler(void); /*!< SDMEM Interrupt */
310 void IRQ069_Handler(void); /*!< PLL clock ind Interrupt */
311 void IRQ070_Handler(void); /*!< Reserved */
312 void IRQ071_Handler(void); /*!< CCI system Interrupt Out */
313 void IRQ072_Handler(void); /*!< FPU exception */
314 void IRQ073_Handler(void); /*!< USB INTR */
315 void IRQ074_Handler(void); /*!< TASS_P2P_INTR */
316 #ifdef __cplusplus
317 }
318 #endif
319
320 #endif /* __SYSTEM_ARMCM4_H__ */
321
