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Searched refs:USART2_SCLK_SEL (Results 1 – 3 of 3) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c3065 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x00; in clk_usart_clk_config()
3101 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x02; in clk_usart_clk_config()
3137 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x03; in clk_usart_clk_config()
3174 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x01; in clk_usart_clk_config()
3208 pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x04; in clk_usart_clk_config()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/
Dclock_update.c162 src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL; in RSI_CLK_GetBaseClock()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h10511 __IOM unsigned int USART2_SCLK_SEL : 3; /*!< [9..7] Selects one of the following clocks member