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Searched refs:USART1_SCLK_FRAC_SEL (Results 1 – 3 of 3) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c2250 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; in clk_usart_clk_div()
2252 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; in clk_usart_clk_div()
3059 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; in clk_usart_clk_config()
3061 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; in clk_usart_clk_config()
3095 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; in clk_usart_clk_config()
3097 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; in clk_usart_clk_config()
3131 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; in clk_usart_clk_config()
3133 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; in clk_usart_clk_config()
3168 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; in clk_usart_clk_config()
3170 pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; in clk_usart_clk_config()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/
Dclock_update.c145 swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL; in RSI_CLK_GetBaseClock()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h10537 __IOM unsigned int USART1_SCLK_FRAC_SEL : 1; /*!< [29..29] Selects the type of divider member