Home
last modified time | relevance | path

Searched refs:ULP_VAD_FCLK_MAX_SEL (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_ulpss_clk.h141 #define ULP_VAD_FCLK_MAX_SEL 8 /* Maximum Seletion value for ulp Vad fclock source*/ macro
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ulpss_clk.c624 || FclkSource > ULP_VAD_FCLK_MAX_SEL) { in ulpss_vad_clk_config()