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Searched refs:ULP_UART_MAX_SEL (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_ulpss_clk.h123 #define ULP_UART_MAX_SEL 7 /* Maximum Seletion value for ulp Uart clock source*/ macro
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ulpss_clk.c344 …pULPCLK == NULL) || (divFactor > ULP_UART_MAX_DIVISION_FACTOR) || (clkSource > ULP_UART_MAX_SEL)) { in ulpss_ulp_uar_clk_config()