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Searched refs:ULP_TIMER_CLK_GEN_REG_b (Results 1 – 3 of 3) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ulpss_clk.c448 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_IN_SYNC_b = 1; in ulpss_time_clk_config()
450 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_IN_SYNC_b = 0; in ulpss_time_clk_config()
456 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
463 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
470 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
477 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
483 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
490 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
494 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; in ulpss_time_clk_config()
999 pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = 0xF; in ulpss_time_clk_disable()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/
Dclock_update.c683 src_clk_mux = ULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL; in RSI_CLK_GetBaseClock()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h13921 } ULP_TIMER_CLK_GEN_REG_b; member