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Searched refs:ULP_GPIO (Results 1 – 3 of 3) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/
Dsl_si91x_peripheral_gpio.c134 ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.MODE = mode; // Set mode in ULP GPIO instance in sl_gpio_set_pin_mode()
180 return (sl_gpio_mode_t)(ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.MODE); in sl_gpio_get_pin_mode()
220 ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.DIRECTION = direction; in sl_si91x_gpio_set_pin_direction()
258 return ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.DIRECTION; in sl_si91x_gpio_get_pin_direction()
439 ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = ENABLE; in sl_si91x_gpio_enable_group_interrupt()
442 ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = ENABLE; in sl_si91x_gpio_enable_group_interrupt()
444 ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = ENABLE; in sl_si91x_gpio_enable_group_interrupt()
475 ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = DISABLE; in sl_si91x_gpio_disable_group_interrupt()
477 ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = DISABLE; in sl_si91x_gpio_disable_group_interrupt()
502 ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = ENABLE; in sl_si91x_gpio_mask_group_interrupt()
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/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/
Dsl_si91x_peripheral_gpio.h316 ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = SET; in sl_gpio_set_pin_output()
343 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (pins); in sl_gpio_set_port_output()
369 …ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (ULP_GPIO->PORT_CONFIG[port].PORT_SET_REG & ~… in sl_gpio_set_port_output_value()
418 ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = CLR; in sl_gpio_clear_pin_output()
445 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_CLEAR_REG = (pins); in sl_gpio_clear_port_output()
479 return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG; in sl_gpio_get_pin_input()
509 return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG; in sl_gpio_get_pin_output()
534 return ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK; in sl_gpio_get_port_input()
558 return (ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK); in sl_gpio_get_port_output()
590 ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG ^= SET; in sl_gpio_toggle_pin_output()
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Dsl_si91x_gpio_common.h53 #define ULP_GPIO ((EGPIO_Type *)EGPIO1_BASE) ///< MCU ULP base address macro