Home
last modified time | relevance | path

Searched refs:ULP_DYN_CLK_CTRL_DISABLE_b (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ulpss_clk.c827 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_EN_b = 1; in ulpss_peripheral_enable()
830 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 1; in ulpss_peripheral_enable()
834 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 0; in ulpss_peripheral_enable()
835 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_DYN_CTRL_DISABLE_b = 0; in ulpss_peripheral_enable()
836 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_DYN_CTRL_DISABLE_b = 0; in ulpss_peripheral_enable()
845 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.FIM_CLK_DYN_CTRL_DISABLE_b = 0; in ulpss_peripheral_enable()
860 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_PCLK_DYN_CTRL_DISABLE_b = 0; in ulpss_peripheral_enable()
861 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_SCLK_DYN_CTRL_DISABLE_b = 0; in ulpss_peripheral_enable()
865 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UDMA_CLK_ENABLE_b = 1; in ulpss_peripheral_enable()
875 pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_CLK_DYN_CTRL_DISABLE_b = 0; in ulpss_peripheral_enable()
[all …]
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/
Dsi91x_device.h14158 } ULP_DYN_CLK_CTRL_DISABLE_b; member