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Searched refs:ULPCLKS_TRIM_SEL_REG_ADDR (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_ipmu.c1569 ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) = ENABLE_CALIB_DOMAIN; in RSI_IPMU_20M_ROClktrim()
1571 ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) &= (uint32_t)~0x3F; in RSI_IPMU_20M_ROClktrim()
1573 ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) |= clkfreq; in RSI_IPMU_20M_ROClktrim()
1586 ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) = ULPCLKS_TRIM_SEL_REG_DEFAULT; in RSI_IPMU_20M_ROClktrim()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_ipmu.h210 #define ULPCLKS_TRIM_SEL_REG_ADDR 0x107 macro