1 /* ----------------------------------------------------------------------------- 2 * SPDX-License-Identifier: Zlib 3 * Copyright (c) 2013-2016 ARM Ltd. 4 * 5 * This software is provided 'as-is', without any express or implied warranty. 6 * In no event will the authors be held liable for any damages arising from 7 * the use of this software. Permission is granted to anyone to use this 8 * software for any purpose, including commercial applications, and to alter 9 * it and redistribute it freely, subject to the following restrictions: 10 * 11 * 1. The origin of this software must not be misrepresented; you must not 12 * claim that you wrote the original software. If you use this software in 13 * a product, an acknowledgment in the product documentation would be 14 * appreciated but is not required. 15 * 16 * 2. Altered source versions must be plainly marked as such, and must not be 17 * misrepresented as being the original software. 18 * 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * 22 * $Date: 29. March 2016 23 * $Revision: V2.6 24 * 25 * Project: Inter Integrated Circuit(I2C) Definitions for Silicon Labs MCU 26 * -------------------------------------------------------------------------- */ 27 28 #ifndef __I2C_H 29 #define __I2C_H 30 31 #include "rsi_pll.h" 32 #include "rsi_ulpss_clk.h" 33 #include "Driver_I2C.h" 34 #include "rsi_ccp_common.h" 35 36 37 /* I2C Interrupt Events */ 38 #define RSI_I2C_EVENT_RECEIVE_UNDER (1UL << 0) /*!< read the receive buffer when it is empty inerrupt */ 39 #define RSI_I2C_EVENT_RECEIVE_OVER (1UL << 1) /*!< receive buffer is completely filled interrupt */ 40 #define RSI_I2C_EVENT_RECEIVE_FULL (1UL << 2) /*!< receive buffer above the RX_TL threshold interrupt */ 41 #define RSI_I2C_EVENT_TRANSMIT_OVER (1UL << 3) /*!< issue write command after transmit buffer is filled completely */ 42 #define RSI_I2C_EVENT_TRANSMIT_EMPTY (1UL << 4) /*!< TX FIFO is empty interrupt */ 43 #define RSI_I2C_EVENT_READ_REQ (1UL << 5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ 44 #define RSI_I2C_EVENT_TRANSMIT_ABRT (1UL << 6) /*!< Transmit abort interrupt */ 45 #define RSI_I2C_EVENT_RECEIVE_DONE (1UL << 7) /*!< receive done interrupt */ 46 #define RSI_I2C_EVENT_ACTIVITY_ON_BUS (1UL << 8) /*!< I2C activity interrupt */ 47 #define RSI_I2C_EVENT_STOP_DETECT (1UL << 9) /*!< Stop condition on bus detection interrupt */ 48 #define RSI_I2C_EVENT_START_DETECT (1UL << 10) /*!< START or RESTART condition interrupt */ 49 #define RSI_I2C_EVENT_GENERAL_CALL (1UL << 11) /*!< General call interrupt */ 50 #define RSI_I2C_EVENT_RESTART_DET (1UL << 12) /*!< RESTART condition in slave mode */ 51 #define RSI_I2C_EVENT_MST_ON_HOLD (1UL << 13) /*!< master is holding the bus and the Tx FIFO is empty */ 52 #define RSI_I2C_EVENT_SCL_STUCK_AT_LOW (1UL << 14) 53 54 #define I2C_RECEIVE_UNDER (0) /*!< read the receive buffer when it is empty inerrupt */ 55 #define I2C_RECEIVE_OVER (1) /*!< receive buffer is completely filled interrupt */ 56 #define I2C_RECEIVE_FULL (2) /*!< receive buffer above the RX_TL threshold interrupt */ 57 #define I2C_TRANSMIT_OVER (3) /*!< issue write command after transmit buffer is filled completely */ 58 #define I2C_TRANSMIT_EMPTY (4) /*!< TX FIFO is empty interrupt */ 59 #define I2C_READ_REQ (5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ 60 #define I2C_TRANSMIT_ABRT (6) /*!< Transmit abort interrupt */ 61 #define I2C_RECEIVE_DONE (7) /*!< receive done interrupt */ 62 #define I2C_ACTIVITY_ON_BUS (8) /*!< I2C activity interrupt */ 63 #define I2C_STOP_DETECT (9) /*!< Stop condition on bus detection interrupt */ 64 #define I2C_START_DETECT (10) /*!< START or RESTART condition interrupt */ 65 #define I2C_GENERAL_CALL (11) /*!< General call interrupt */ 66 #define I2C_RESTART_DET (12) /*!< RESTART condition in slave mode */ 67 #define I2C_MST_ON_HOLD (13) /*!< master is holding the bus and the Tx FIFO is empty */ 68 #define I2C_SCL_STUCK_AT_LOW (14) 69 70 /* TX Abort Sources */ 71 #define I2C_TX_ABRT_7B_ADDR_NOACK (15) 72 #define I2C_TX_ABRT_10ADDR1_NOACK (16) 73 #define I2C_TX_ABRT_10ADDR2_NOACK (17) 74 #define I2C_TX_ABRT_TXDATA_NOACK (18) 75 #define I2C_TX_ABRT_GCALL_NOACK (19) 76 #define I2C_TX_ABRT_GCALL_READ (20) 77 #define I2C_TX_ABRT_HS_ACKDET (21) 78 #define I2C_TX_ABRT_SBYTE_ACKDET (22) 79 #define I2C_TX_ABRT_HS_NORSTRT (23) 80 #define I2C_TX_ABRT_SBYTE_NORSTRT (24) 81 #define I2C_TX_ABRT_10B_RD_NORSTRT (25) 82 #define I2C_TX_ABRT_MASTER_DIS (26) 83 #define I2C_TX_ARB_LOST (27) 84 #define I2C_TX_ABRT_SLVFLUSH_TXFIFO (28) 85 #define I2C_TX_ABRT_SLV_ARBLOST (29) 86 #define I2C_TX_ABRT_SLVRD_INTX (30) 87 #define I2C_TX_ABRT_USER_ABRT (31) 88 #define I2C_TX_ABRT_SDA_STUCK_AT_LOW (32) 89 #define I2C_TX_ABRT_DEVICE_NOACK (33) 90 #define I2C_TX_ABRT_DEVICE_SLVADDR_NOACK (34) 91 #define I2C_TX_ABRT_DEVICE_WRITE (35) 92 #define I2C_TX_TX_FLUSH_CNT (36) 93 94 #define SLAVE_ADDR_CHECK_ARG 0x01 95 #define SLAVE_RX_ARG 0x02 96 #define SLAVE_TX_ARG 0x03 97 98 #define NACK 1 99 #define ACK 0 100 101 #define F_RX_UNDER 0 102 #define F_RX_OVER 1 103 #define F_RX_FULL 2 104 #define F_TX_OVER 3 105 #define F_TX_EMPTY 4 106 #define F_RD_REQ 5 107 #define F_TX_ABRT 6 108 #define F_RX_DONE 7 109 #define F_ACTIVITY 8 110 #define F_STOP_DET 9 111 #define F_START_DET 10 112 #define F_GEN_CALL 11 113 #define F_RESTART_DET 12 114 #define F_MST_ON_HOLD 13 115 116 #define I2C_ACTIVITY (1UL << 0) 117 #define I2C_TFNF (1UL << 1) 118 #define I2C_TFE (1UL << 2) 119 #define I2C_RFNE (1UL << 3) 120 #define I2C_RFF (1UL << 4) 121 #define I2C_MST_ACTIVITY (1UL << 5) 122 #define I2C_SLV_ACTIVITY (1UL << 6) 123 124 125 #define I2C_STAT_ACTIVITY 0 126 #define I2C_STAT_TFNF 1 127 #define I2C_STAT_TFE 2 128 #define I2C_STAT_RFNE 3 129 #define I2C_STAT_RFF 4 130 #define I2C_STAT_MST_ACTIVITY 5 131 #define I2C_STAT_SLV_ACTIVITY 6 132 #define I2C_TX_ABRT_SOURCE 7 133 134 #define TX_ABRT_7B_ADDR_NOACK (1UL << 0) 135 #define TX_ABRT_10ADDR1_NOACK (1UL << 1) 136 #define TX_ABRT_10ADDR2_NOACK (1UL << 2) 137 #define TX_ABRT_TXDATA_NOACK (1UL << 3) 138 #define TX_ABRT_GCALL_NOACK (1UL << 4) 139 #define TX_ABRT_GCALL_READ (1UL << 5) 140 #define TX_ABRT_HS_ACKDET (1UL << 6) 141 #define TX_ABRT_SBYTE_ACKDET (1UL << 7) 142 #define TX_ABRT_HS_NORSTRT (1UL << 8) 143 #define TX_ABRT_SBYTE_NORSTRT (1UL << 9) 144 #define TX_ABRT_10B_RD_NORSTRT (1UL << 10) 145 #define TX_ABRT_MASTER_DIS (1UL << 11) 146 #define TX_ARB_LOST (1UL << 12) 147 #define TX_ABRT_SLVFLUSH_TXFIFO (1UL << 13) 148 #define TX_ABRT_SLV_ARBLOST (1UL << 14) 149 #define TX_ABRT_SLVRD_INTX (1UL << 15) 150 #define TX_ABRT_USER_ABRT (1UL << 16) 151 #define TX_ABRT_SDA_STUCK_AT_LOW (1UL << 17) 152 #define TX_ABRT_DEVICE_NOACK (1UL << 18) 153 #define TX_ABRT_DEVICE_SLVADDR_NOACK (1UL << 19) 154 #define TX_ABRT_DEVICE_WRITE (1UL << 20) 155 #define TX_TX_FLUSH_CNT (1UL << 23) 156 157 /* bit defines */ 158 #define I2C2_BUS_CLK_ENABLE (1UL << 8) 159 #define I2C_STATIC_CLK_EN (1UL << 17) 160 #define UDMA_HCLK_ENBALE (1UL << 6) 161 #define ULP_UDMA_STATIC_CLK_EN (1UL << 17) 162 #define I2C2_STATIC_CLK_EN (1UL << 18) 163 #define I2C_FIFO_DEPTH 8 164 165 166 /* I2C example defines */ 167 #define CHNL_30 30 168 #define CHNL_31 31 169 #define PRIMARY 0 170 #define ALTERNATE 1 171 172 173 #define I2C_RESTART_EN 0x1 174 175 #define I2C_MST_ADDR_7BIT_MODE 0x0 176 #define I2C_MST_ADDR_10BIT_MODE 0x1 177 #define I2C_SLV_ADDR_7BIT_MODE 0x0 178 179 #define I2C_SLV_ADDR 0x50 180 181 #define I2C_SCL_LOW_CLK 0x6 182 #define I2C_SCL_HIGH_CLK 0x1 183 184 #define I2C_TX_TL 0x1 185 #define I2C_RX_TL 0x4 186 #define ADDRESS_WIDTH 8 187 188 #define MULTI_PAGE_WRITE 1 189 #define SINGLE_PAGE_WRITE 0 190 191 #define BIT_WIDTH_8 0 192 #define BIT_WIDTH_16 1 193 #define BIT_WIDTH_32 2 194 195 #define READ_CMD 1 196 #define WRITE_CMD 0 197 198 #define TX_EN 1 199 #define RX_EN 1 200 201 #define I2C_DMA_TX_REQ 0x2 202 #define I2C_DMA_RX_REQ 0x2 203 #define DMA_ACK (1UL << 7) 204 205 /* PAD pin selection */ 206 #define I2C0_PAD_SEL_6_8 1 207 #define GPIO_6_REN 6 208 #define GPIO_8_REN 8 209 210 #define I2CM_BLOCKING_XFER 1 211 #define I2CM_NONBLOCKING_XFER 0 212 213 214 #define SS_MIN_SCL_HIGH 5200 215 #define SS_MIN_SCL_LOW 4700 216 #define FS_MIN_SCL_HIGH 1160 217 #define FS_MIN_SCL_LOW 1300 218 #define HS_MIN_SCL_HIGH_400PF 274 219 #define HS_MIN_SCL_LOW_400PF 333 220 #define HS_MIN_SCL_HIGH_100PF 60 221 #define HS_MIN_SCL_LOW_100PF 120 222 223 #define RSI_I2C_HIGH_SPEED 0x3 224 225 /* I2C Driver state flags */ 226 #define I2C_FLAG_INIT (1 << 0) // Driver initialized 227 #define I2C_FLAG_POWER (1 << 1) // Driver power on 228 #define I2C_FLAG_SETUP (1 << 2) // Master configured, clock set 229 #define I2C_FLAG_SLAVE_RX (1 << 3) // Slave receive registered 230 #define I2C_FLAG_STOP_DET (1 << 4) 231 232 /* I2C Stalled Status flags */ 233 #define I2C_MASTER (1 << 0) // Master stalled 234 #define I2C_SLAVE_TX (1 << 1) // Slave stalled on transmit 235 #define I2C_SLAVE_RX (1 << 2) // Slave stalled on receive 236 #define I2C_SLAVE (I2C_SLAVE_TX | I2C_SLAVE_RX) 237 238 /* I2C Interrupt Events */ 239 #define I2C_EVENT_RECEIVE_UNDER (1UL << 0) /*!< read the receive buffer when it is empty inerrupt */ 240 #define I2C_EVENT_RECEIVE_OVER (1UL << 1) /*!< receive buffer is completely filled interrupt */ 241 #define I2C_EVENT_RECEIVE_FULL (1UL << 2) /*!< receive buffer above the RX_TL threshold interrupt */ 242 #define I2C_EVENT_TRANSMIT_OVER (1UL << 3) /*!< issue write command after transmit buffer is filled completely */ 243 #define I2C_EVENT_TRANSMIT_EMPTY (1UL << 4) /*!< TX FIFO is empty interrupt */ 244 #define I2C_EVENT_READ_REQ (1UL << 5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ 245 #define I2C_EVENT_TRANSMIT_ABRT (1UL << 6) /*!< Transmit abort interrupt */ 246 #define I2C_EVENT_RECEIVE_DONE (1UL << 7) /*!< receive done interrupt */ 247 #define I2C_EVENT_ACTIVITY_ON_BUS (1UL << 8) /*!< I2C activity interrupt */ 248 #define I2C_EVENT_STOP_DETECT (1UL << 9) /*!< Stop condition on bus detection interrupt */ 249 #define I2C_EVENT_START_DETECT (1UL << 10) /*!< START or RESTART condition interrupt */ 250 #define I2C_EVENT_GENERAL_CALL (1UL << 11) /*!< General call interrupt */ 251 #define I2C_EVENT_RESTART_DET (1UL << 12) /*!< RESTART condition in slave mode */ 252 #define I2C_EVENT_MST_ON_HOLD (1UL << 13) /*!< master is holding the bus and the Tx FIFO is empty */ 253 #define I2C_EVENT_SCL_STUCK_AT_LOW (1UL << 14) 254 255 #define TRANSMITTER 0 256 #define RECEIVER 1 257 258 void I2C0_IRQHandler (void); 259 void I2C1_IRQHandler (void); 260 void I2C2_IRQHandler (void); 261 /* I2C Control Information */ 262 typedef struct 263 { 264 ARM_I2C_SignalEvent_t cb_event; // Event callback 265 ARM_I2C_STATUS status; // Status flags 266 uint8_t flags; // Control and state flags 267 uint16_t sla_rw; // Slave address and RW bit 268 bool pending; // Transfer pending (no STOP) 269 uint8_t stalled; // Stall mode status flags 270 uint8_t con_aa; // I2C slave CON flag 271 int32_t cnt; // Master transfer count 272 uint8_t *data; // Master data to transfer 273 uint32_t num; // Number of bytes to transfer 274 uint8_t *sdata; // Slave data to transfer 275 uint32_t snum; // Number of bytes to transfer 276 } I2C_CTRL; 277 278 typedef const struct _I2C_PIN { 279 uint8_t port; ///< CAN GPIO port 280 uint8_t pin; ///< CAN GPIO pin 281 uint8_t mode; ///< CAN GPIO mode 282 uint8_t pad_sel; ///< CAN GPIO pad selection 283 }I2C_PIN; 284 285 typedef const struct _I2C_IO { 286 I2C_PIN *scl; 287 I2C_PIN *sda; 288 } I2C_IO; 289 290 /* I2C Resource Configuration */ 291 typedef struct 292 { 293 I2C0_Type *reg; // I2C register interface 294 IRQn_Type i2c_ev_irq; // I2C Event IRQ Numbe 295 I2C_CTRL *ctrl; // Run-Time control information 296 I2C_IO io; //pins 297 } I2C_RESOURCES; 298 299 #endif 300 301
