1 /***************************************************************************/ /**
2 * @file rsi_pwm.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 // Includes Files
31
32 #include "rsi_ccp_common.h"
33 #include "base_types.h"
34 #include "rsi_error.h"
35
36 #ifndef RSI_PWM_H
37 #define RSI_PWM_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #define RSI_MCPWM_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1
44 #define RSI_MCPWM_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1
45
46 // MCPWM Interrupt Flags
47 #define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH0 \
48 (1UL << 0) // Time base match for 0th channel without considering postscaler
49 #define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH0 (1UL << 1) // Time base match for 0th channel which considering postscaler
50 #define RSI_MCPWM_EVENT_FAULT_A (1UL << 2) // Fault A pin match
51 #define RSI_MCPWM_EVENT_FAULT_B (1UL << 3) // Fault B pin match
52 #define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH1 \
53 (1UL << 4) // Time base match for 1st channel without considering postscaler
54 #define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH1 \
55 (1UL << 5) // Time base match for 1st channel which considering postscaler
56 #define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH2 \
57 (1UL << 6) // Time base match for 2nd channel without considering postscaler
58 #define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH2 (1UL << 7) // Time base match for 2nd channel which considering postscaler
59 #define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH3 \
60 (1UL << 8) // Time base match for 3rd channel without considering postscaler
61 #define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH3 \
62 (1UL << 9) // Time base match for 3rd channel without considering postscaler
63
64 #define FLTA_MODE (1UL << 0)
65 #define FLTB_MODE (1UL << 1)
66 #define FLTA_ENABLE (1UL << 4)
67 #define FLTB_ENABLE (1UL << 8)
68
69 // MCPWM Events
70 #define RISE_TIME_PERIOD_MATCH_CH0 0x0 // Event for 0th channel without considering postscaler
71 #define TIME_PERIOD_MATCH_CH0 0x1 // Event for 0th channel which considering postscaler
72 #define FAULT_A 0x2 // Fault A pin Event
73 #define FAULT_B 0x3 // Fault B pin Event
74 #define RISE_TIME_PERIOD_MATCH_CH1 0x4 // Event for 1st channel without considering postscaler
75 #define TIME_PERIOD_MATCH_CH1 0x5 // Event for 1st channel which considering postscaler
76 #define RISE_TIME_PERIOD_MATCH_CH2 0x6 // Event for 2nd channel without considering postscaler
77 #define TIME_PERIOD_MATCH_CH2 0x7 // Event for 2nd channel which considering postscaler
78 #define RISE_TIME_PERIOD_MATCH_CH3 0x8 // Event for 3rd channel without considering postscaler
79 #define TIME_PERIOD_MATCH_CH3 0x9 // Event for 3rd channel which considering postscaler
80
81 #define COUNTER_A 0
82 #define COUNTER_B 1
83
84 // PWM Example defines
85 #define PWM_CHNL_0 0
86 #define PWM_CHNL_1 1
87 #define PWM_CHNL_2 2
88 #define PWM_CHNL_3 3
89
90 #define TMR_FREE_RUN_MODE 0x0
91 #define TMR_SINGLE_EVENT_MODE 0x1
92 #define TMR_DOWN_COUNT_MODE 0x2
93 #define TMR_UP_DOWN_MODE 0x3
94 #define TMR_UP_DOWN_DOUBLE_UPDATE 0x4
95
96 #define ONE_TIMER_FOR_EACH_CHNL 0
97 #define ONE_TIMER_FOR_ALL_CHNL 1
98
99 #define TIME_PERIOD_PRESCALE_1 0x0
100 #define TIME_PERIOD_PRESCALE_2 0x1
101 #define TIME_PERIOD_PRESCALE_4 0x2
102 #define TIME_PERIOD_PRESCALE_8 0x3
103 #define TIME_PERIOD_PRESCALE_16 0x4
104 #define TIME_PERIOD_PRESCALE_32 0x5
105 #define TIME_PERIOD_PRESCALE_64 0x6
106
107 #define TIME_PERIOD_POSTSCALE_1_1 0x0
108 #define TIME_PERIOD_POSTSCALE_1_2 0x1
109 #define TIME_PERIOD_POSTSCALE_1_3 0x2
110 #define TIME_PERIOD_POSTSCALE_1_4 0x3
111 #define TIME_PERIOD_POSTSCALE_1_5 0x4
112 #define TIME_PERIOD_POSTSCALE_1_6 0x5
113 #define TIME_PERIOD_POSTSCALE_1_7 0x6
114 #define TIME_PERIOD_POSTSCALE_1_8 0x7
115 #define TIME_PERIOD_POSTSCALE_1_9 0x8
116 #define TIME_PERIOD_POSTSCALE_1_10 0x9
117 #define TIME_PERIOD_POSTSCALE_1_11 0xA
118 #define TIME_PERIOD_POSTSCALE_1_12 0xB
119 #define TIME_PERIOD_POSTSCALE_1_13 0xC
120 #define TIME_PERIOD_POSTSCALE_1_14 0xD
121 #define TIME_PERIOD_POSTSCALE_1_15 0xE
122 #define TIME_PERIOD_POSTSCALE_1_16 0xF
123
124 #define TMR0_PERIOD 0x1500
125 #define TMR1_PERIOD 0x1500
126 #define TMR2_PERIOD 0x1500
127 #define TMR3_PERIOD 0x1500
128
129 #define COUNTER_INIT_VAL 0
130
131 #define DUTYCYCLE_UPDATE_DIS0 (1 << 4)
132 #define DUTYCYCLE_UPDATE_DIS1 (1 << 5)
133 #define DUTYCYCLE_UPDATE_DIS2 (1 << 6)
134 #define DUTYCYCLE_UPDATE_DIS3 (1 << 7)
135
136 #define IMD_UPDATE_EN0 (1 << 0)
137 #define IMD_UPDATE_EN1 (1 << 1)
138 #define IMD_UPDATE_EN2 (1 << 2)
139 #define IMD_UPDATE_EN3 (1 << 3)
140
141 #define DUTYCYCLE_UPDATE_EN0 (1 << 4)
142 #define DUTYCYCLE_UPDATE_EN1 (1 << 5)
143 #define DUTYCYCLE_UPDATE_EN2 (1 << 6)
144 #define DUTYCYCLE_UPDATE_EN3 (1 << 7)
145
146 #define IMD_UPDATE_DIS0 (1 << 0)
147 #define IMD_UPDATE_DIS1 (1 << 1)
148 #define IMD_UPDATE_DIS2 (1 << 2)
149 #define IMD_UPDATE_DIS3 (1 << 3)
150
151 #define TMR0_DUTYCYCLE 0xA80
152 #define TMR1_DUTYCYCLE 0xA80
153 #define TMR2_DUTYCYCLE 0xA80
154 #define TMR3_DUTYCYCLE 0xA80
155
156 #define COMPLEMENT 1
157 #define INDEPENDENT 0
158
159 #define OUT_POL_H_HIGH (1 << 2)
160 #define OUT_POL_H_LOW (0 << 2)
161
162 #define OUT_POL_L_HIGH (1 << 3)
163 #define OUT_POL_L_LOW (0 << 3)
164
165 #define DT_SELECT_INACTIVE_CH0 (1 << 4)
166 #define DT_SELECT_INACTIVE_CH1 (1 << 5)
167 #define DT_SELECT_INACTIVE_CH2 (1 << 6)
168 #define DT_SELECT_INACTIVE_CH3 (1 << 7)
169
170 #define DT_SELECT_ACTIVE_CH0 (1 << 0)
171 #define DT_SELECT_ACTIVE_CH1 (1 << 1)
172 #define DT_SELECT_ACTIVE_CH2 (1 << 2)
173 #define DT_SELECT_ACTIVE_CH3 (1 << 3)
174
175 #define COUNTUP 0
176 #define COUNTDOWN 1
177 #define PWM_OUTPUT_L0 0
178 #define PWM_OUTPUT_L1 1
179 #define PWM_OUTPUT_L2 2
180 #define PWM_OUTPUT_L3 3
181 #define PWM_OUTPUT_H0 4
182 #define PWM_OUTPUT_H1 5
183 #define PWM_OUTPUT_H2 6
184 #define PWM_OUTPUT_H3 7
185
186 #define PWM_OUTPUT_MIN 0
187 #define PWM_OUTPUT_MAX 7
188
189 #define OVERRIDE_SYNC_EN 1
190 #define OVERRIDE_SYNC_DIS 0
191
192 #define OV_VALUE_0 1
193 #define OV_VALUE_1 0
194
195 #define DT_EN_CH0 (1 << 8)
196 #define DT_EN_CH1 (1 << 9)
197 #define DT_EN_CH2 (1 << 10)
198 #define DT_EN_CH3 (1 << 11)
199
200 #define DT_DIS_CH0 (1 << 8)
201 #define DT_DIS_CH1 (1 << 9)
202 #define DT_DIS_CH2 (1 << 10)
203 #define DT_DIS_CH3 (1 << 11)
204
205 typedef MCPWM_Type RSI_MCPWM_T;
206
207 // brief MCPWM Status
208 typedef struct {
209 uint32_t counterDir; // Current Counter direction
210 uint32_t counterVal; // Counter current value
211 } RSI_MCPWM_STATUS_T;
212
213 // brief MCPWM Driver Capabilities.
214 typedef struct {
215 uint32_t pwmOutputs : 4; // Number of PWM outputs
216 uint32_t faultPins : 2; // Number of fault input pins
217 } RSI_MCPWM_CAPABILITIES_T;
218
219 // brief MCPWM Callback structure
220 typedef struct {
221 void (*cbFunc)(uint16_t flag); // Call back function pointer
222
223 } RSI_MCPWM_CALLBACK_T;
224
225 // brief MCPWM Special Event trigger configuration parameters.
226 typedef struct {
227 uint16_t svtPostscalar; // SVT PostScalar value
228 uint16_t svtCompareVal; // SVT compare value to generate trigger for A/D
229 uint8_t svtChannel; // channel to generate SVT
230 } RSI_MCPWM_SVT_CONFIG_T;
231
232 // brief MCPWM DeadTime Configuration parameters.
233 typedef struct {
234 uint8_t counterSelect; // Selects coutner A/B for deadtime insertion
235 int8_t preScaleA; // PreScale for counter A
236 int8_t preScaleB; // PreScale for counter B
237 int8_t deadTimeA; // Deadtime for counter A
238 int8_t deadTimeB; // Deadtime for counter B
239 } RSI_MCPWM_DT_CONFIG_T;
240
241 /*===================================================*/
242 /**
243 * @fn rsi_error_t RSI_MCPWM_ReadCounter(RSI_MCPWM_T *pMCPWM,uint16_t *counterVal,
244 uint8_t chnlNum)
245 * @brief This API is used to read the counter current value
246 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
247 * @param[in] counterVal : counter value
248 * @param[in] chnlNum : Channel number(0 to 3)
249 * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel is invalid.
250 \n \ref RSI_OK : If process is done successfully.
251 */
RSI_MCPWM_ReadCounter(RSI_MCPWM_T * pMCPWM,uint16_t * counterVal,uint8_t chnlNum)252 STATIC INLINE rsi_error_t RSI_MCPWM_ReadCounter(RSI_MCPWM_T *pMCPWM, uint16_t *counterVal, uint8_t chnlNum)
253 {
254 // Gets Time period counter current value
255 switch (chnlNum) {
256 case PWM_CHNL_0:
257 *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH0);
258 break;
259 case PWM_CHNL_1:
260 *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH1);
261 break;
262 case PWM_CHNL_2:
263 *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH2);
264 break;
265 case PWM_CHNL_3:
266 *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH3);
267 break;
268 default:
269 return ERROR_PWM_INVALID_CHNLNUM;
270 }
271 return RSI_OK;
272 }
273
274 /*===================================================*/
275 /**
276 * @fn rsi_error_t RSI_MCPWM_GetCounterDir(RSI_MCPWM_T *pMCPWM,uint8_t *counterDir,
277 uint8_t chnlNum)
278 * @brief This API is used to get time period counter direction status of required MCPWM channel
279 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
280 * @param[in] chnlNum : Channel number(0 to 3)
281 * @param[out] counterDir : Counter direction as up/down counter.
282 * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid.
283 \n \ref RSI_OK(0) : If process is done successfully.
284 */
RSI_MCPWM_GetCounterDir(RSI_MCPWM_T * pMCPWM,uint8_t * counterDir,uint8_t chnlNum)285 STATIC INLINE rsi_error_t RSI_MCPWM_GetCounterDir(RSI_MCPWM_T *pMCPWM, uint8_t *counterDir, uint8_t chnlNum)
286 {
287 // Gets the counter direction
288 switch (chnlNum) {
289 case PWM_CHNL_0:
290 *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH0);
291 break;
292 case PWM_CHNL_1:
293 *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH1);
294 break;
295 case PWM_CHNL_2:
296 *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH2);
297 break;
298 case PWM_CHNL_3:
299 *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH3);
300 break;
301 default:
302 return ERROR_PWM_INVALID_CHNLNUM;
303 }
304 return RSI_OK;
305 }
306
307 /*===================================================*/
308 /**
309 * @fn void RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T *pMCPWM ,uint32_t flag)
310 * @brief Enables dead time insertion at rise edge or fall edge of any four channels
311 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
312 * @param[in] flag : This can be ORing of below values
313 - DT_EN_CH0
314 - DT_EN_CH1
315 - DT_EN_CH2
316 - DT_EN_CH3
317 * @return none
318 */
RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T * pMCPWM,uint32_t flag)319 STATIC INLINE void RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T *pMCPWM, uint32_t flag)
320 {
321 pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = flag;
322 }
323
324 /*===================================================*/
325 /**
326 * @fn void RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T *pMCPWM ,uint32_t flag)
327 * @brief This API is used to disable the dead time mode for the specified MCPWM generator.
328 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
329 * @param[in] flag : This can be ORing of below values
330 - DT_DIS_CH0
331 - DT_DIS_CH1
332 - DT_DIS_CH2
333 - DT_DIS_CH3
334 * @return none
335 */
RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T * pMCPWM,uint32_t flag)336 STATIC INLINE void RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T *pMCPWM, uint32_t flag)
337 {
338 pMCPWM->PWM_DEADTIME_CTRL_SET_REG = flag;
339 }
340
341 /*===================================================*/
342 /**
343 * @fn void RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T *pMCPWM ,uint32_t flag)
344 * @brief Enables dead time insertion at rise edge or fall edge of any four channels
345 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
346 * @param[in] flag : This can be ORing of below values
347 - DT_EN_CH0
348 - DT_EN_CH1
349 - DT_EN_CH2
350 - DT_EN_CH3
351 * @return none
352 */
RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T * pMCPWM,uint32_t flag)353 STATIC INLINE void RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T *pMCPWM, uint32_t flag)
354 {
355 pMCPWM->PWM_DEADTIME_CTRL_SET_REG = flag;
356 }
357
358 /*===================================================*/
359 /**
360 * @fn void RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T *pMCPWM ,uint32_t flag)
361 * @brief This API is used to disable the dead time mode for the specified MCPWM generator.
362 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
363 * @param[in] flag : This can be ORing of below values
364 - DT_DIS_CH0
365 - DT_DIS_CH1
366 - DT_DIS_CH2
367 - DT_DIS_CH3
368 * @return none
369 */
RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T * pMCPWM,uint32_t flag)370 STATIC INLINE void RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T *pMCPWM, uint32_t flag)
371 {
372 pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = flag;
373 }
374
375 /*===================================================*/
376 /**
377 * @fn void RSI_MCPWM_InterruptClear(RSI_MCPWM_T *pMCPWM, uint32_t clrFlag)
378 * @brief This API is used to clear the interrupts of MCPWM
379 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
380 * @param[in] clrFlag : This can be logical OR of the below parameters
381 - RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : Time base interrupt for 0th channel without considering postscaler
382 \n if bit is one then pwm time period match interrupt for 0th channel will
383 be cleared if bit zero then no effect.
384 - PWM_TIME_PRD_MATCH_INTR_CH0_ACK : Time base interrupt for 0th channel which
385 considering postscaler
386 \n if bit is one then pwm time period match interrupt for 0th channel will
387 be cleared if bit zero then no effect.
388 - FLT_A_INTR_ACK : Fault A pin interrupt
389 \n if bit is set pwm faultA interrupt will be cleared,if zero then ,no effect.
390 - FLT_A_INTR_ACK : Fault B pin interrupt
391 \n if bit is set pwm faultB interrupt will be cleared,if zero then ,no effect.
392 - RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : Time base interrupt for
393 1th channel without considering postscaler
394 \n if bit is one then pwm time period match interrupt for 1th channel will
395 be cleared if bit zero then no effect.
396 - PWM_TIME_PRD_MATCH_INTR_CH1_ACK : Time base interrupt for 1th channel which
397 considering postscaler
398 \n if bit is one then pwm time period match interrupt for 1th channel will
399 be cleared if bit zero then no effect.
400 - RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : Time base interrupt for
401 2nd channel without considering postscaler
402 \n if bit is one then pwm time period match interrupt for 1th channel will
403 be cleared if bit zero then no effect.
404 - PWM_TIME_PRD_MATCH_INTR_CH2_ACK : Time base interrupt for 2nd channel which
405 considering postscaler
406 \n if bit is one then pwm time period match interrupt for 2nd channel will
407 be cleared if bit zero then no effect.
408 - RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : Time base interrupt for
409 3rd channel without considering postscaler
410 \n if bit is one then pwm time period match interrupt for 3rd channel will
411 be cleared if bit zero then no effect.
412 - PWM_TIME_PRD_MATCH_INTR_CH3_ACK : Time base interrupt for 3rd channel which
413 considering postscaler
414 \n if bit is one then pwm time period match interrupt for 3rd channel will
415 be cleared if bit zero then no effect.
416
417 * @return none
418 */
RSI_MCPWM_InterruptClear(RSI_MCPWM_T * pMCPWM,uint32_t clrFlag)419 STATIC INLINE void RSI_MCPWM_InterruptClear(RSI_MCPWM_T *pMCPWM, uint32_t clrFlag)
420 {
421 pMCPWM->PWM_INTR_ACK = clrFlag;
422 }
423
424 /*===================================================*/
425 /**
426 * @fn void RSI_MCPWM_InterruptEnable(RSI_MCPWM_T *pMCPWM, uint16_t flag)
427 * @brief This API is used to enable the interrupts of MCPWM
428 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
429 * @param[in] flag : flag value can be logical OR of the below parameters
430 - RISE_PWM_TIME_PERIOD_MATCH_CH0 : Time base interrupt for 0th channel without
431 considering postscaler
432 \n if bit is 1 then pwm time period match interrupt for 0th channel
433 will be cleared,if zero then no effect.
434 - PWM_TIME_PRD_MATCH_INTR_CH0 : Time base interrupt for 0th channel which
435 considering postscaler
436 \n if bit is 1 then pwm time period match interrupt for 0th channel
437 will be cleared if zero then no effect.
438 - FLT_A_INTR : Fault A pin interrupt
439 \n if bit is one then pwm faultA interrupt will be cleared if zero
440 then no effect.
441 - FLT_B_INTR : Fault B pin interrupt
442 \n if bit is one pwm faultB interrupt will be cleared if zero
443 then no effect.
444 - RISE_PWM_TIME_PERIOD_MATCH_CH1 : Time base interrupt for 1st channel without
445 considering postscaler
446 \n if bit is one pwm time period match interrupt for 1st channel
447 will be cleared if bit is zero no effect
448 - PWM_TIME_PRD_MATCH_INTR_CH1 : Time base interrupt for 1st channel which
449 considering postscaler
450 \n if bit is 1 then pwm time period match interrupt for 1st channel
451 will be cleared if zero then no effect.
452 - RISE_PWM_TIME_PERIOD_MATCH_CH2 : Time base interrupt for 2nd channel without
453 considering postscaler
454 \n if bit is one pwm time period match interrupt for 2nd channel
455 will be cleared if bit is zero no effect
456 - PWM_TIME_PRD_MATCH_INTR_CH2 : Time base interrupt for 2nd channel which
457 considering postscaler
458 \n if bit is one pwm time period match interrupt for 2nd channel
459 will be cleared if bit is zero no effect
460 - RISE_PWM_TIME_PERIOD_MATCH_CH3 : Time base interrupt for 3rd channel without
461 considering postscaler
462 \n if bit is one pwm time period match interrupt for 3rd channel
463 will be cleared if bit is zero no effect
464 - PWM_TIME_PRD_MATCH_INTR_CH3 : Time base interrupt for 3rd channel which considering
465 postscaler
466 \n if bit is one pwm time period match interrupt for 3rd channel
467 will be cleared if bit is zero no effect
468 * @return none
469 */
RSI_MCPWM_InterruptEnable(RSI_MCPWM_T * pMCPWM,uint16_t flag)470 STATIC INLINE void RSI_MCPWM_InterruptEnable(RSI_MCPWM_T *pMCPWM, uint16_t flag)
471 {
472 pMCPWM->PWM_INTR_UNMASK = flag;
473 }
474
475 /*===================================================*/
476 /**
477 * @fn void RSI_MCPWM_InterruptDisable(RSI_MCPWM_T *pMCPWM, uint16_t flag)
478 * @brief This API is used to disable the interrupts of MCPWM
479 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
480 * @param[in] flag : flag value can be logical OR of the below parameters
481 - RISE_PWM_TIME_PERIOD_MATCH_CH0 : Time base interrupt for 0th channel without
482 considering postscaler
483 \n if bit is 1 then pwm time period match interrupt for 0th channel
484 will be cleared,if zero then no effect.
485 - PWM_TIME_PRD_MATCH_INTR_CH0 : Time base interrupt for 0th channel which
486 considering postscaler
487 \n if bit is 1 then pwm time period match interrupt for 0th channel
488 will be cleared if zero then no effect.
489 - FLT_A_INTR : Fault A pin interrupt
490 \n if bit is one then pwm faultA interrupt will be cleared if zero
491 then no effect.
492 - FLT_B_INTR : Fault B pin interrupt
493 \n if bit is one pwm faultB interrupt will be cleared if zero
494 then no effect.
495 - RISE_PWM_TIME_PERIOD_MATCH_CH1 : Time base interrupt for 1st channel without
496 considering postscaler
497 \n if bit is one pwm time period match interrupt for 1st channel
498 will be cleared if bit is zero no effect
499 - PWM_TIME_PRD_MATCH_INTR_CH1 : Time base interrupt for 1st channel which
500 considering postscaler
501 \n if bit is 1 then pwm time period match interrupt for 0th channel
502 will be cleared if zero then no effect.
503 - RISE_PWM_TIME_PERIOD_MATCH_CH2 : Time base interrupt for 2nd channel without
504 considering postscaler
505 \n if bit is one pwm time period match interrupt for 2nd channel
506 will be cleared if bit is zero no effect
507 - PWM_TIME_PRD_MATCH_INTR_CH2 : Time base interrupt for 2nd channel which
508 considering postscaler
509 \n if bit is one pwm time period match interrupt for 2nd channel
510 will be cleared if bit is zero no effect
511 - RISE_PWM_TIME_PERIOD_MATCH_CH3 : Time base interrupt for 3rd channel without
512 considering postscaler
513 \n if bit is one pwm time period match interrupt for 3rd channel
514 will be cleared if bit is zero no effect
515 - PWM_TIME_PRD_MATCH_INTR_CH3 : Time base interrupt for 3rd channel which considering
516 postscaler
517 \n if bit is one pwm time period match interrupt for 3rd channel
518 will be cleared if bit is zero no effect
519 * @return none
520 */
RSI_MCPWM_InterruptDisable(RSI_MCPWM_T * pMCPWM,uint16_t flag)521 STATIC INLINE void RSI_MCPWM_InterruptDisable(RSI_MCPWM_T *pMCPWM, uint16_t flag)
522 {
523 pMCPWM->PWM_INTR_MASK = flag;
524 }
525
526 /*===================================================*/
527 /**
528 * @fn uint16_t RSI_PWM_GetInterruptStatus(RSI_MCPWM_T *pMCPWM, uint16_t flag)
529 * @brief This API is used to get the interrupt status of interrupt flags of MCPWM.
530 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
531 * @param[in] flag : Flag value
532 * @return Interrupt status of required interrupt flag
533 */
RSI_PWM_GetInterruptStatus(RSI_MCPWM_T * pMCPWM,uint16_t flag)534 STATIC INLINE uint16_t RSI_PWM_GetInterruptStatus(RSI_MCPWM_T *pMCPWM, uint16_t flag)
535 {
536 return (uint16_t)(pMCPWM->PWM_INTR_STS & flag);
537 }
538
539 /*===================================================*/
540 /**
541 * @fn rsi_error_t RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value,uint8_t chnlNum)
542 * @brief This API is used to set duty cycle control parameters for the required MCPWM channel
543 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
544 * @param[in] value : This can be logical OR of below parameters
545 - IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately
546 - DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable
547 * @param[in] chnlNum : Channel number(0 to 3)
548 * @return ERROR_PWM_INVALID_CHNLNUM : If channel is invalid.
549 \n RSI_OK : If process is done successfully.
550 */
RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T * pMCPWM,uint32_t value,uint8_t chnlNum)551 STATIC INLINE rsi_error_t RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value, uint8_t chnlNum)
552 {
553 if (chnlNum <= PWM_CHNL_3) {
554 pMCPWM->PWM_DUTYCYCLE_CTRL_SET_REG = value;
555 } else {
556 return ERROR_PWM_INVALID_CHNLNUM;
557 }
558 return RSI_OK;
559 }
560
561 /*===================================================*/
562 /**
563 * @fn rsi_error_t RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T *pMCPWM,uint32_t value, uint8_t chnlNum)
564 * @brief This API is used to reset the duty cycle control parameters of required MCPWM channel
565 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
566 * @param[in] value : This can be logical OR of below parameters
567 - IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately
568 - DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable
569 * @param[in] chnlNum Channel number(0 to 3)
570 * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid
571 \n \ref RSI_OK : If process is done successfully.
572 */
RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T * pMCPWM,uint32_t value,uint8_t chnlNum)573 STATIC INLINE rsi_error_t RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T *pMCPWM, uint32_t value, uint8_t chnlNum)
574 {
575 if (chnlNum <= PWM_CHNL_3) {
576 pMCPWM->PWM_DUTYCYCLE_CTRL_RESET_REG = value;
577 } else {
578 return ERROR_PWM_INVALID_CHNLNUM;
579 }
580 return RSI_OK;
581 }
582
583 /*===================================================*/
584 /**
585 * @fn rsi_error_t RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput)
586 * @brief This API is used to enable the output override operation of MCPWM
587 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
588 * @param[in] pwmOutput : Pwm output over ride,possible values are as below
589 - 0 : L0
590 - 1 : L1
591 - 2 : L2
592 - 3 : L3
593 - 4 : H0
594 - 5 : H1
595 - 6 : H2
596 - 7 : H3
597 * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid
598 * \n \ref RSI_OK : If process is done successfully.
599 */
RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T * pMCPWM,uint8_t pwmOutput)600 STATIC INLINE rsi_error_t RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput)
601 {
602 if (pwmOutput <= PWM_OUTPUT_MAX) {
603 pMCPWM->PWM_OP_OVERRIDE_ENABLE_SET_REG = (1 << pwmOutput);
604 } else {
605 return ERROR_PWM_INVALID_ARG;
606 }
607 return RSI_OK;
608 }
609
610 /*===================================================*/
611 /**
612 * @fn rsi_error_t RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput)
613 * @brief This API is used to disable the output override operation of MCPWM
614 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
615 * @param[in] pwmOutput : Pwm output over ride enable,possible values are as below
616 - 0 : L0
617 - 1 : L1
618 - 2 : L2
619 - 3 : L3
620 - 4 : H0
621 - 5 : H1
622 - 6 : H2
623 - 7 : H3
624 * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid
625 * \n \ref RSI_OK : If process is done successfully.
626 */
RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T * pMCPWM,uint8_t pwmOutput)627 STATIC INLINE rsi_error_t RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput)
628 {
629 if (pwmOutput <= PWM_OUTPUT_MAX) {
630 pMCPWM->PWM_OP_OVERRIDE_ENABLE_RESET_REG = (1 << pwmOutput);
631 } else {
632 return ERROR_PWM_INVALID_ARG;
633 }
634 return RSI_OK;
635 }
636
637 /*===================================================*/
638 /**
639 * @fn void RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value)
640 * @brief This API is used to set the override control parameter,output is synced with pwm time period depending on operating mode
641 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
642 * @param[in] value : if value is 1 then Output override is synced with pwm time period depending
643 \n on operating mode, if 0 then no effect.
644 * @return none
645 */
RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T * pMCPWM,uint32_t value)646 STATIC INLINE void RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
647 {
648 pMCPWM->PWM_OP_OVERRIDE_CTRL_SET_REG = value;
649 }
650
651 /*===================================================*/
652 /**
653 * @fn void RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T *pMCPWM,uint32_t value)
654 * @brief This API is used to reset the output override sync control parameter.
655 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
656 * @param[in] value : if value is 1 then Output override is synced with pwm time period depending
657 \n on operating mode, if 0 then no effect.
658 * @return none
659 */
RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T * pMCPWM,uint32_t value)660 STATIC INLINE void RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
661 {
662 pMCPWM->PWM_OP_OVERRIDE_CTRL_RESET_REG = value;
663 }
664
665 /*===================================================*/
666 /**
667 * @fn void RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput,uint8_t value)
668 * @brief This API is used to set override value for the required output of MCPWM.
669 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
670 * @param[in] pwmOutput : PWM outputs are as below
671 - 0 : L0
672 - 1 : L1
673 - 2 : L2
674 - 3 : L3
675 - 4 : H0
676 - 5 : H1
677 - 6 : H2
678 - 7 : H3
679 * @param[in] value : override value can be 0 or 1
680 * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid
681 * \n \ref RSI_OK : If process is done successfully.
682 */
RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T * pMCPWM,uint8_t pwmOutput,uint8_t value)683 STATIC INLINE rsi_error_t RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value)
684 {
685 if (pwmOutput <= PWM_OUTPUT_MAX) {
686 pMCPWM->PWM_OP_OVERRIDE_VALUE_SET_REG = (value << pwmOutput);
687 } else {
688 return ERROR_PWM_INVALID_ARG;
689 }
690 return RSI_OK;
691 }
692
693 /*===================================================*/
694 /**
695 * @fn rsi_error_t RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput,uint8_t value)
696 * @brief This API is used to reset override value for the required output of MCPWM.
697 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
698 * @param[in] pwmOutput : PWM outputs are as below
699 - 0 : L0
700 - 1 : L1
701 - 2 : L2
702 - 3 : L3
703 - 4 : H0
704 - 5 : H1
705 - 6 : H2
706 - 7 : H3
707 * @param[in] value : override value can be 0 or 1
708 * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid
709 \n \ref RSI_OK : If process is done successfully.
710 */
RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T * pMCPWM,uint8_t pwmOutput,uint8_t value)711 STATIC INLINE rsi_error_t RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value)
712 {
713 if (pwmOutput <= PWM_OUTPUT_MAX) {
714 pMCPWM->PWM_OP_OVERRIDE_VALUE_RESET_REG = (value << pwmOutput);
715 } else {
716 return ERROR_PWM_INVALID_ARG;
717 }
718 return RSI_OK;
719 }
720
721 /*===================================================*/
722 /**
723 * @fn void RSI_MCPWM_FaultControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value)
724 * @brief This API is used to set output fault override control parameters for required PWM output
725 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
726 * @param[in] value : This can be logical OR of below parameters
727 - FLT_A_MODE : if bit one then cycle by cycle by mode and zero then latched mode
728 - FLT_B_MODE : if bit one then cycle by cycle by mode and zero then latched mode
729 - OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals.
730 \n if bit 0 then in active low mode and 1 then active high mode.
731 - OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals.
732 \n if bit 0 then in active low mode and 1 then active high mode.
733 - FLT_A_ENABLE : enable fault A
734 - FLT_B_ENABLE : enable fault B
735 - COMPLEMENT_MODE : PWM I/O pair mode
736 \n if bit is 1 then PWM I/O pin pair is in the complementary output mode
737 \n if bit is 0 then PWM I/O pin pair is in the independent output mode
738 * @return none
739 */
RSI_MCPWM_FaultControlSet(RSI_MCPWM_T * pMCPWM,uint32_t value)740 STATIC INLINE void RSI_MCPWM_FaultControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
741 {
742 pMCPWM->PWM_FLT_OVERRIDE_CTRL_SET_REG = value;
743 }
744
745 /*===================================================*/
746 /**
747 * @fn void RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
748 * @brief This API is used to reset output fault override control parameters for required PWM output.
749 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
750 * @param[in] value : This can be logical OR of below parameters
751 - FLT_A_MODE : if bit one then cycle by cycle by mode and zero then latched mode
752 - FLT_B_MODE : if bit one then cycle by cycle by mode and zero then latched mode
753 - OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals.
754 \n if bit 0 then in active low mode and 1 then active high mode.
755 - OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals.
756 \n if bit 0 then in active low mode and 1 then active high mode.
757 - FLT_A_ENABLE : enable fault A
758 - FLT_B_ENABLE : enable fault B
759 - COMPLEMENT_MODE : PWM I/O pair mode
760 \n if bit is 1 then PWM I/O pin pair is in the complementary output mode
761 \n if bit is 0 then PWM I/O pin pair is in the independent output mode
762 * @return none
763 */
RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T * pMCPWM,uint32_t value)764 STATIC INLINE void RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
765 {
766 pMCPWM->PWM_FLT_OVERRIDE_CTRL_RESET_REG = value;
767 }
768
769 /*===================================================*/
770 /**
771 * @fn void RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T *pMCPWM )
772 * @brief This API is used to enable generation of special event trigger for required channel of MCPWM
773 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
774 * @return none
775 */
RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T * pMCPWM)776 STATIC INLINE void RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T *pMCPWM)
777 {
778 pMCPWM->PWM_SVT_CTRL_SET_REG = (1 << 0);
779 }
780
781 /*===================================================*/
782 /**
783 * @fn void RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T *pMCPWM )
784 * @brief This API is used to disable generation of special event trigger for required channel of MCPWM
785 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
786 * @return none
787 */
RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T * pMCPWM)788 STATIC INLINE void RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T *pMCPWM)
789 {
790 pMCPWM->PWM_SVT_CTRL_RESET_REG = (1 << 0);
791 }
792
793 /*===================================================*/
794 /**
795 * @fn void RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value )
796 * @brief This API is used to set dead time control parameters for the reqired channel.
797 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
798 * @param[in] value : This can be logical OR of below parameters
799 - DEADTIME_SELECT_ACTIVE : Deadtime select bits for PWM going active
800 Possible values are as below if bit zero then use counter A , if one then use counter B
801 - DEADTIME_SELECT_INACTIVE : Deadtime select bits for PWM going inactive
802 Possible values are as below if bit zero then use counter A , if one then use counter B
803 * @return none
804 */
RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T * pMCPWM,uint32_t value)805 STATIC INLINE void RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
806 {
807 pMCPWM->PWM_DEADTIME_CTRL_SET_REG = value;
808 }
809
810 /*===================================================*/
811 /**
812 * @fn void RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value )
813 * @brief This API is used to reset dead time control for the MCPWM.
814 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
815 * @param[in] value : This can be logical OR of below parameters
816 - DEADTIME_SELECT_ACTIVE : Deadtime select bits for PWM going active
817 Possible values are as below if bit zero then use counter A , if one then use counter B
818 - DEADTIME_SELECT_INACTIVE : Deadtime select bits for PWM going inactive
819 Possible values are as below if bit zero then use counter A , if one then use counter B
820 * @return none
821 */
RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T * pMCPWM,uint32_t value)822 STATIC INLINE void RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value)
823 {
824 pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = value;
825 }
826
827 /*===================================================*/
828 /**
829 * @fn rsi_error_t RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T *pMCPWM, uint16_t dutyCycle, uint8_t chnlNum)
830 * @brief This API is used to set duty cycle for the required MCPWM channel.
831 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
832 * @param[in] dutyCycle : Duty cycle value
833 * @param[in] chnlNum : channel number(0 to 3)
834 * @return \ref ERROR_PWM_INVALID_ARG : If channel number is invalid
835 \n \ref RSI_OK : If process is done successfully.
836 */
RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T * pMCPWM,uint16_t dutyCycle,uint8_t chnlNum)837 STATIC INLINE rsi_error_t RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T *pMCPWM, uint16_t dutyCycle, uint8_t chnlNum)
838 {
839 if (chnlNum <= PWM_CHNL_3) {
840 pMCPWM->PWM_DUTYCYCLE_REG_WR_VALUE_b[chnlNum].PWM_DUTYCYCLE_REG_WR_VALUE_CH = dutyCycle;
841 } else {
842 return ERROR_PWM_INVALID_ARG;
843 }
844 return RSI_OK;
845 }
846
847 /*===================================================*/
848 /**
849 * @fn void RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T *pMCPWM,boolean_t enable)
850 * @brief This API is used to enable to use external trigger for base time counter increment or decrement of MCPWM
851 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
852 * @param[in] enable : If 0 then disable external trigger
853 \n If 1 then enable external trigger.
854 * @return none
855 */
RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T * pMCPWM,boolean_t enable)856 STATIC INLINE void RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T *pMCPWM, boolean_t enable)
857 {
858 pMCPWM->PWM_TIME_PRD_COMMON_REG_b.USE_EXT_TIMER_TRIG_FRM_REG = (unsigned int)(enable & 0x01);
859 }
860
861 /*==============================================*/
862 /**
863 * @fn rsi_error_t RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum)
864 * @brief This API is used to disable the reset for required channel of MCPWM.
865 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
866 * @param[in] chnlNum : Channel number(0 to 3)
867 * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel is invalid
868 * \n \ref RSI_OK : If process is done successfully.
869 */
RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T * pMCPWM,uint8_t chnlNum)870 STATIC INLINE rsi_error_t RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum)
871 {
872 // Resets operation of MCPWM channel
873 switch (chnlNum) {
874 case PWM_CHNL_0:
875 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH0_b.PWM_SFT_RST = DISABLE;
876 break;
877 case PWM_CHNL_1:
878 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH1_b.PWM_SFT_RST = DISABLE;
879 break;
880 case PWM_CHNL_2:
881 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH2_b.PWM_SFT_RST = DISABLE;
882 break;
883 case PWM_CHNL_3:
884 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH3_b.PWM_SFT_RST = DISABLE;
885 break;
886 default:
887 return ERROR_PWM_INVALID_CHNLNUM;
888 }
889 return RSI_OK;
890 }
891
892 /*==============================================*/
893 /**
894 * @fn rsi_error_t RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum)
895 * @brief This API is used to disable the counter reset for required channel of MCPWM
896 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
897 * @param[in] chnlNum : Channel number(0 to 3)
898 * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid
899 * \n \ref RSI_OK : If process is done successfully
900 */
RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T * pMCPWM,uint8_t chnlNum)901 STATIC INLINE rsi_error_t RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum)
902 {
903 // resets counter operations
904 switch (chnlNum) {
905 case PWM_CHNL_0:
906 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH0_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE;
907 break;
908 case PWM_CHNL_1:
909 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH1_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE;
910 break;
911 case PWM_CHNL_2:
912 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH2_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE;
913 break;
914 case PWM_CHNL_3:
915 pMCPWM->PWM_TIME_PRD_CTRL_REG_CH3_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE;
916 break;
917 default:
918 return ERROR_PWM_INVALID_CHNLNUM;
919 }
920 return RSI_OK;
921 }
922
923 /*===================================================*/
924 /**
925 * @fn void RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T *pMCPWM,uint8_t baseTime)
926 * @brief This API is used to select number of base timers as four base timers for four channels or one base timer for all channels of MCPWM
927 * @param[in] pMCPWM : Pointer to the MCPWM instance register area
928 * @param[in] baseTime : if 0 then one base timer for each channel
929 \n if 1 then only one base timer for all channels
930 * @return none
931 */
RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T * pMCPWM,uint8_t baseTime)932 STATIC INLINE void RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T *pMCPWM, uint8_t baseTime)
933 {
934 pMCPWM->PWM_TIME_PRD_COMMON_REG_b.PWM_TIME_PRD_USE_0TH_TIMER_ONLY = (unsigned int)(baseTime & 0x01);
935 }
936 // PWM FUNCTION PROTOTYPES
937 RSI_DRIVER_VERSION_M4 RSI_MCPWM_GetVersion(void);
938
939 RSI_MCPWM_CAPABILITIES_T RSI_MCPWM_GetCapabilities(void);
940
941 rsi_error_t mcpwm_counter_reset(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum);
942
943 rsi_error_t mcpwm_channel_reset(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum);
944
945 rsi_error_t mcpwm_start(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum);
946
947 rsi_error_t mcpwm_stop(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum);
948
949 rsi_error_t mcpwm_set_time_period(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum, uint16_t period, uint16_t initVal);
950
951 void mcpwm_special_event_trigger_config(RSI_MCPWM_T *pMCPWM, boolean_t svtDir, RSI_MCPWM_SVT_CONFIG_T *pMCPWMSVTConfig);
952
953 rsi_error_t mcpwm_dead_time_value_set(RSI_MCPWM_T *pMCPWM,
954 RSI_MCPWM_DT_CONFIG_T *pMCPWMDeadTimeConfig,
955 uint8_t chnlNum);
956 rsi_error_t mcpwm_fault_avalue_set(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value);
957
958 rsi_error_t mcpwm_fault_bvalue_set(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value);
959
960 rsi_error_t mcpwm_set_base_timer_mode(RSI_MCPWM_T *pMCPWM, uint8_t mode, uint8_t chnlNum);
961
962 rsi_error_t mcpwm_set_output_mode(RSI_MCPWM_T *pMCPWM, boolean_t mode, uint8_t chnlNum);
963
964 void mcpwm_set_output_polarity(RSI_MCPWM_T *pMCPWM, boolean_t polL, boolean_t polH);
965
966 void mcpwm_interrupt_handler(RSI_MCPWM_T *pMCPWM, RSI_MCPWM_CALLBACK_T *pCallBack);
967
968 rsi_error_t mcpwm_period_control_config(RSI_MCPWM_T *pMCPWM, uint32_t postScale, uint32_t preScale, uint8_t chnlNum);
969 void SysTick_Handler(void);
970 uint32_t MCPWM_PercentageToTicks(uint8_t percent, uint8_t chnl_num);
971 void MCPWM_SetChannelPeriod(uint32_t freq);
972 void RSI_MCPWM_PinMux();
973
974 #ifdef __cplusplus
975 }
976 #endif
977 #endif // RSI_PWM_H
978
