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Searched refs:TIMER5_BASE (Results 1 – 25 of 62) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/service/device_manager/devices/
Dsl_device_peripheral_hal_efr32xg25.c390 #if defined(TIMER5_BASE)
392 const sl_peripheral_val_t sl_peripheral_val_timer5 = { .base = TIMER5_BASE,
Dsl_device_peripheral_hal_efr32xg26.c390 #if defined(TIMER5_BASE)
392 const sl_peripheral_val_t sl_peripheral_val_timer5 = { .base = TIMER5_BASE,
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b420f2048gl112.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048gl120.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048gm64.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048gq100.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048gq64.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048il112.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048il120.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048im64.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048iq100.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b420f2048iq64.h481 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
558 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048gl120.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048gl152.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048gl192.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048gm64.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048gq100.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048gq64.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048il120.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048il152.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048im64.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048iq100.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b820f2048iq64.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b840f1024gl120.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
Defm32gg11b840f1024gl152.h483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ macro
560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */

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