1 /******************************************************************************
2 * @file  rsi_efuse.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 *    claim that you wrote the original software. If you use this software
22 *    in a product, an acknowledgment in the product documentation would be
23 *    appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 *    misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29 
30 // Includes Files
31 
32 #include "rsi_ccp_common.h"
33 #include "base_types.h"
34 #include "rsi_error.h"
35 
36 #ifndef RSI_EFUSE_H
37 #define RSI_EFUSE_H
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 #define TA_EFUSE_BASE_ADDR 0x40010000
44 #define M4_EFUSE_BASE_ADDR 0x4600C000
45 
46 #define TA_EFUSE_IO_BASE_ADDR (TA_EFUSE_BASE_ADDR + 0x2000)
47 #define M4_EFUSE_IO_BASE_ADDR (M4_EFUSE_BASE_ADDR + 0x2000)
48 
49 #define EFUSE_DA_ADDR_REG_OFFSET           0x00
50 #define EFUSE_DA_CTRL_SET_REG_OFFSET       0x04
51 #define EFUSE_DA_CTRL_CLEAR_REG_OFFSET     0x08
52 #define EFUSE_CTRL_REG_OFFSET              0x0C
53 #define EFUSE_READ_ADDR_REG_OFFSET         0x10
54 #define EFUSE_READ_DATA_REG_OFFSET         0x14
55 #define EFUSE_STATUS_REG_OFFSET            0x18
56 #define EFUSE_RD_TMNG_PARAM_REG_OFFSET     0x1C
57 #define EFUSE_DA_ADDR_REG_DEFAULT_OFFSET   0x2C
58 #define EFUSE_MEM_MAP_LENGTH_OFFSET        0x24
59 #define EFUSE_DA_CLR_STROBE_REG_OFFSET     0x34
60 #define EFUSE_CLK_ENABLE_SET_REG2_OFFSET   0x38
61 #define EFUSE_CLK_ENABLE_CLEAR_REG2_OFFSET 0x3C
62 
63 #define TA_EFUSE_DA_ADDR_REG         (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_OFFSET)))
64 #define TA_EFUSE_DA_CTRL_SET_REG     (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_SET_REG_OFFSET)))
65 #define TA_EFUSE_DA_CTRL_CLEAR_REG   (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_CLEAR_REG_OFFSET)))
66 #define TA_EFUSE_CTRL_REG            (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_CTRL_REG_OFFSET)))
67 #define TA_EFUSE_READ_ADDR_REG       (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_READ_ADDR_REG_OFFSET)))
68 #define TA_EFUSE_READ_DATA_REG       (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_READ_DATA_REG_OFFSET)))
69 #define TA_EFUSE_STATUS_REG          (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_STATUS_REG_OFFSET)))
70 #define TA_EFUSE_RD_TMNG_PARAM_REG   (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_RD_TMNG_PARAM_REG_OFFSET)))
71 #define TA_EFUSE_DA_ADDR_REG_DEFAULT (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_DEFAULT_OFFSET)))
72 #define TA_EFUSE_MEM_MAP_LENGTH      (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_MEM_MAP_LENGTH_OFFSET)))
73 #define TA_EFUSE_DA_CLR_STROBE_REG   (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CLR_STROBE_REG_OFFSET)))
74 
75 #define M4_EFUSE_DA_ADDR_REG         (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_OFFSET)))
76 #define M4_EFUSE_DA_CTRL_SET_REG     (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_SET_REG_OFFSET)))
77 #define M4_EFUSE_DA_CTRL_CLEAR_REG   (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_CLEAR_REG_OFFSET)))
78 #define M4_EFUSE_CTRL_REG            (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_CTRL_REG_OFFSET)))
79 #define M4_EFUSE_READ_ADDR_REG       (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_READ_ADDR_REG_OFFSET)))
80 #define M4_EFUSE_READ_DATA_REG       (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_READ_DATA_REG_OFFSET)))
81 #define M4_EFUSE_STATUS_REG          (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_STATUS_REG_OFFSET)))
82 #define M4_EFUSE_RD_TMNG_PARAM_REG   (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_RD_TMNG_PARAM_REG_OFFSET)))
83 #define M4_EFUSE_DA_ADDR_REG_DEFAULT (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_DEFAULT_OFFSET)))
84 #define M4_EFUSE_MEM_MAP_LENGTH      (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_MEM_MAP_LENGTH_OFFSET)))
85 #define M4_EFUSE_DA_CLR_STROBE_REG   (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CLR_STROBE_REG_OFFSET)))
86 
87 #define EFUSE_CLK_BIT             BIT(5)
88 #define EFUSE_PCLK_BIT            BIT(19)
89 #define M4SS_CLK_ENABLE_SET_3_REG (*((volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x10)))
90 
91 // EFUSE_DA_CTRL_SET_REG
92 #define SET_LOAD_ENABLE    BIT(3)
93 #define SET_CHIP_ENABLE    BIT(1)
94 #define SET_PROGRAM_ENABLE BIT(0)
95 
96 #define READ_FSM_DONE BIT(15)
97 
98 // Address range for 32x8 eFUSE for M4SS
99 #define ADDRESS_MIN 0x00 // Start address
100 #define ADDRESS_MAX 0x31 // End address
101 
102 // Bit Positions range
103 #define BIT_POS_MIN 0x00 // Min Bit position
104 #define BIT_POS_MAX 0x07 // Max bit position
105 
106 void efuse_enable(EFUSE_Type *pstcEfuse);
107 
108 void efuse_Disable(EFUSE_Type *pstcEfuse);
109 
110 uint8_t efuse_read_data(EFUSE_Type *pstcEfuse);
111 
112 void efuse_write_addr(EFUSE_Type *pstcEfuse, uint16_t u16Addr);
113 
114 rsi_error_t efuse_get_addr(EFUSE_Type *pstcEfuse, uint16_t *u16AddrVal);
115 
116 rsi_error_t efuse_write_bit(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t u8BitPos, uint32_t hold_time);
117 
118 rsi_error_t efuse_fsm_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk);
119 
120 rsi_error_t efuse_mem_map_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk);
121 
122 rsi_error_t efuse_mem_map_read_word(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint16_t *pu16Word, uint32_t SocClk);
123 
124 rsi_error_t efuse_direct_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t hold_time);
125 
126 void efuse_write_address(EFUSE_Type *pstcEfuse, uint16_t u16Addr);
127 
128 #ifdef __cplusplus
129 }
130 #endif
131 
132 #endif // RSI_EFUSE_H
133