1 /* ----------------------------------------------------------------------------- 2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 * $Date: 02. March 2016 19 * $Revision: V2.2 20 * 21 * Project: SPI Driver Definitions for Silicon Labs MCU 22 * -------------------------------------------------------------------------- */ 23 24 #ifndef __SPI_H 25 #define __SPI_H 26 27 #include "rsi_pll.h" 28 #include "Driver_SPI.h" 29 #include "rsi_ccp_common.h" 30 31 #include "UDMA.h" 32 #include "rsi_ulpss_clk.h" 33 #ifdef SSI_INSTANCE_CONFIG 34 #include "sl_ssi_common_config.h" 35 #elif SSI_CONFIG 36 #include "sl_si91x_ssi_common_config.h" 37 #endif 38 39 #define SSI_DISABLE 0x00 /*!< Disable the SSI Operation*/ 40 #define SSI_ENABLE 0x01 /*!< Enable the SSI Operation*/ 41 #define TXEIM 0x1 42 #define TXOIM 0x2 43 #define RXUIM 0x4 44 #define RXOIM 0x8 45 #define RXFIM 0x10 46 #define TRANSMIT_AND_RECEIVE 0x00 47 #define TRANSMIT_ONLY 0x01 48 #define RECEIVE_ONLY 0x02 49 #define STANDARD_SPI_FORMAT 0x00 50 #define MOTOROLA_SPI 0x00 51 #define TEXAS_INSTRUMENTS_SSP 0x01 52 #define NATIONAL_SEMICONDUCTORS_MICROWIRE 0x02 53 #define SPI_MASTER_MODE 1U 54 #define SPI_SLAVE_MODE 2U 55 #define SPI_ULP_MASTER_MODE 3U 56 #define SSI_INSTANCE_BIT 30 // SSI Instance validation bits 57 #define SSI_INSTANCE_MASK 0x3FFFFFFF // Mask value for SSI instance 58 #define SSI_MASTER_INSTANCE 0 // SSI Master Instance 59 #define SSI_SLAVE_INSTANCE 1 // SSI Slave Instance 60 #define SSI_ULP_MASTER_INSTANCE 2 // SSI ULP Master Instance 61 62 #define SPI_ISR_TX_FIFO_EMPTY BIT(0) 63 #define SPI_ISR_TX_FIFO_OVERFLOW BIT(1) 64 #define SPI_ISR_RX_FIFO_UNDERFLOW BIT(2) 65 #define SPI_ISR_RX_FIFO_OVERFLOW BIT(3) 66 #define SPI_ISR_RX_FIFO_FULL BIT(4) 67 68 69 ARM_DRIVER_VERSION SPI_GetVersion(void); 70 ARM_SPI_CAPABILITIES SPI_GetCapabilities(void); 71 void IRQ047_Handler(void) ; 72 void IRQ044_Handler(void); 73 void IRQ016_Handler(void); 74 void mySPI_callback(uint32_t event); 75 76 #if ((defined(RTE_Drivers_SSI_MASTER) || \ 77 defined(RTE_Drivers_SSI_SLAVE) || \ 78 defined(RTE_Drivers_SSI_ULP_MASTER)) \ 79 && (RTE_SSI_MASTER == 0) \ 80 && (RTE_SSI_SLAVE == 0) \ 81 && (RTE_SSI_ULP_MASTER == 0)) 82 #error "SPI not configured in RTE_Device_917.h!" 83 #endif 84 85 86 #if defined(RTE_SSI_MASTER) && (RTE_SSI_MASTER == 1) 87 #define SSI_MASTER 1U 88 // Configuring DMA thresholds based on SSI instances. 89 #ifdef SSI_INSTANCE_CONFIG 90 #if defined (SL_SSI_PRIMARY_DMA_CONFIG_ENABLE) && (SL_SSI_PRIMARY_DMA_CONFIG_ENABLE == ENABLE) 91 #define RTE_SSI_MASTER_RX_DMA 1 92 #define RTE_SSI_MASTER_TX_DMA 1 93 #endif 94 95 #if defined (SL_SSI_SECONDARY_DMA_CONFIG_ENABLE) && (SL_SSI_SECONDARY_DMA_CONFIG_ENABLE == ENABLE) 96 #define RTE_SSI_SLAVE_RX_DMA 1 97 #define RTE_SSI_SLAVE_TX_DMA 1 98 #endif 99 100 #if defined (SL_SSI_ULP_PRIMARY_DMA_CONFIG_ENABLE) && (SL_SSI_ULP_PRIMARY_DMA_CONFIG_ENABLE == ENABLE) 101 #define RTE_SSI_ULP_MASTER_RX_DMA 1 102 #define RTE_SSI_ULP_MASTER_TX_DMA 1 103 #endif 104 // DMA threshold configuration based on SSI unknown instance name. 105 #elif SSI_CONFIG 106 #if defined (SL_SSI_MASTER_DMA_CONFIG_ENABLE) && (SL_SSI_MASTER_DMA_CONFIG_ENABLE == ENABLE) 107 #define RTE_SSI_MASTER_RX_DMA 1 108 #define RTE_SSI_MASTER_TX_DMA 1 109 #endif 110 111 #if defined (SL_SSI_SLAVE_DMA_CONFIG_ENABLE) && (SL_SSI_SLAVE_DMA_CONFIG_ENABLE == ENABLE) 112 #define RTE_SSI_SLAVE_RX_DMA 1 113 #define RTE_SSI_SLAVE_TX_DMA 1 114 #endif 115 116 #if defined (SL_SSI_ULP_MASTER_DMA_CONFIG_ENABLE) && (SL_SSI_ULP_MASTER_DMA_CONFIG_ENABLE == ENABLE) 117 #define RTE_SSI_ULP_MASTER_RX_DMA 1 118 #define RTE_SSI_ULP_MASTER_TX_DMA 1 119 #endif 120 #endif 121 122 #if defined(RTE_SSI_MASTER_RX_DMA) && (RTE_SSI_MASTER_RX_DMA == 1) 123 #define SSI_MASTER_RX_DMA_Instance 1U 124 #define SSI_MASTER_RX_DMA_Channel RTE_SSI_MASTER_UDMA_RX_CH 125 #endif 126 127 #if defined(RTE_SSI_MASTER_TX_DMA) && (RTE_SSI_MASTER_TX_DMA == 1) 128 #define SSI_MASTER_TX_DMA_Instance 1U 129 #define SSI_MASTER_TX_DMA_Channel RTE_SSI_MASTER_UDMA_TX_CH 130 #endif 131 132 #if defined(RTE_SSI_MASTER_MISO) && (RTE_SSI_MASTER_MISO == 1) 133 #define SSI_MASTER_MISO_SEL 1U 134 #define SSI_MASTER_MISO_PORT RTE_SSI_MASTER_MISO_PORT 135 #define SSI_MASTER_MISO_PIN RTE_SSI_MASTER_MISO_PIN 136 #define SSI_MASTER_MISO_MODE RTE_SSI_MASTER_MISO_MODE 137 #define SSI_MASTER_MISO_PADSEL RTE_SSI_MASTER_MISO_PADSEL 138 #endif 139 140 #if defined(RTE_SSI_MASTER_MOSI) && (RTE_SSI_MASTER_MOSI == 1) 141 #define SSI_MASTER_MOSI_SEL 1U 142 #define SSI_MASTER_MOSI_PORT RTE_SSI_MASTER_MOSI_PORT 143 #define SSI_MASTER_MOSI_PIN RTE_SSI_MASTER_MOSI_PIN 144 #define SSI_MASTER_MOSI_MODE RTE_SSI_MASTER_MOSI_MODE 145 #define SSI_MASTER_MOSI_PADSEL RTE_SSI_MASTER_MOSI_PADSEL 146 #endif 147 148 #if defined(RTE_SSI_MASTER_SCK) && (RTE_SSI_MASTER_SCK == 1) 149 #define SSI_MASTER_SCK_SEL 1U 150 #define SSI_MASTER_SCK_PORT RTE_SSI_MASTER_SCK_PORT 151 #define SSI_MASTER_SCK_PIN RTE_SSI_MASTER_SCK_PIN 152 #define SSI_MASTER_SCK_MODE RTE_SSI_MASTER_SCK_MODE 153 #define SSI_MASTER_SCK_PADSEL RTE_SSI_MASTER_SCK_PADSEL 154 #endif 155 156 #if defined(RTE_SSI_MASTER_CS0) && (RTE_SSI_MASTER_CS0 == 1) 157 #define SSI_MASTER_CS0_SEL 1U 158 #define SSI_MASTER_CS0_PORT RTE_SSI_MASTER_CS0_PORT 159 #define SSI_MASTER_CS0_PIN RTE_SSI_MASTER_CS0_PIN 160 #define SSI_MASTER_CS0_MODE RTE_SSI_MASTER_CS0_MODE 161 #define SSI_MASTER_CS0_PADSEL RTE_SSI_MASTER_CS0_PADSEL 162 #endif 163 164 #if defined(RTE_SSI_MASTER_CS1) && (RTE_SSI_MASTER_CS1 == 1) 165 #define SSI_MASTER_CS1_SEL 1U 166 #define SSI_MASTER_CS1_PORT RTE_SSI_MASTER_CS1_PORT 167 #define SSI_MASTER_CS1_PIN RTE_SSI_MASTER_CS1_PIN 168 #define SSI_MASTER_CS1_MODE RTE_SSI_MASTER_CS1_MODE 169 #define SSI_MASTER_CS1_PADSEL RTE_SSI_MASTER_CS1_PADSEL 170 #endif 171 172 #if defined(RTE_SSI_MASTER_CS2) && (RTE_SSI_MASTER_CS2 == 1) 173 #define SSI_MASTER_CS2_SEL 1U 174 #define SSI_MASTER_CS2_PORT RTE_SSI_MASTER_CS2_PORT 175 #define SSI_MASTER_CS2_PIN RTE_SSI_MASTER_CS2_PIN 176 #define SSI_MASTER_CS2_MODE RTE_SSI_MASTER_CS2_MODE 177 #define SSI_MASTER_CS2_PADSEL RTE_SSI_MASTER_CS2_PADSEL 178 #endif 179 180 #if defined(RTE_SSI_MASTER_CS3) && (RTE_SSI_MASTER_CS3 == 1) 181 #define SSI_MASTER_CS3_SEL 1U 182 #define SSI_MASTER_CS3_PORT RTE_SSI_MASTER_CS3_PORT 183 #define SSI_MASTER_CS3_PIN RTE_SSI_MASTER_CS3_PIN 184 #define SSI_MASTER_CS3_MODE RTE_SSI_MASTER_CS3_MODE 185 #define SSI_MASTER_CS3_PADSEL RTE_SSI_MASTER_CS3_PADSEL 186 #endif 187 #endif 188 189 #if defined(RTE_SSI_SLAVE) && (RTE_SSI_SLAVE == 1) 190 #define SSI_SLAVE 1U 191 192 #if defined(RTE_SSI_SLAVE_RX_DMA) && (RTE_SSI_SLAVE_RX_DMA == 1) 193 #define SSI_SLAVE_RX_DMA_Instance 1U 194 #define SSI_SLAVE_RX_DMA_Channel RTE_SSI_SLAVE_UDMA_RX_CH 195 #endif 196 197 #if defined(RTE_SSI_SLAVE_TX_DMA) && (RTE_SSI_SLAVE_TX_DMA == 1) 198 #define SSI_SLAVE_TX_DMA_Instance 1U 199 #define SSI_SLAVE_TX_DMA_Channel RTE_SSI_SLAVE_UDMA_TX_CH 200 #endif 201 202 #if defined(RTE_SSI_SLAVE_MISO) && (RTE_SSI_SLAVE_MISO == 1) 203 #define SSI_SLAVE_MISO_SEL 1U 204 #define SSI_SLAVE_MISO_PORT RTE_SSI_SLAVE_MISO_PORT 205 #define SSI_SLAVE_MISO_PIN RTE_SSI_SLAVE_MISO_PIN 206 #define SSI_SLAVE_MISO_MODE RTE_SSI_SLAVE_MISO_MODE 207 #define SSI_SLAVE_MISO_PADSEL RTE_SSI_SLAVE_MISO_PADSEL 208 #endif 209 210 #if defined(RTE_SSI_SLAVE_MOSI) && (RTE_SSI_SLAVE_MOSI == 1) 211 #define SSI_SLAVE_MOSI_SEL 1U 212 #define SSI_SLAVE_MOSI_PORT RTE_SSI_SLAVE_MOSI_PORT 213 #define SSI_SLAVE_MOSI_PIN RTE_SSI_SLAVE_MOSI_PIN 214 #define SSI_SLAVE_MOSI_MODE RTE_SSI_SLAVE_MOSI_MODE 215 #define SSI_SLAVE_MOSI_PADSEL RTE_SSI_SLAVE_MOSI_PADSEL 216 #endif 217 218 #if defined(RTE_SSI_SLAVE_SCK) && (RTE_SSI_SLAVE_SCK == 1) 219 #define SSI_SLAVE_SCK_SEL 1U 220 #define SSI_SLAVE_SCK_PORT RTE_SSI_SLAVE_SCK_PORT 221 #define SSI_SLAVE_SCK_PIN RTE_SSI_SLAVE_SCK_PIN 222 #define SSI_SLAVE_SCK_MODE RTE_SSI_SLAVE_SCK_MODE 223 #define SSI_SLAVE_SCK_PADSEL RTE_SSI_SLAVE_SCK_PADSEL 224 #endif 225 226 #if defined(RTE_SSI_SLAVE_CS) && (RTE_SSI_SLAVE_CS == 1) 227 #define SSI_SLAVE_CS0_SEL 1U 228 #define SSI_SLAVE_CS0_PORT RTE_SSI_SLAVE_CS_PORT 229 #define SSI_SLAVE_CS0_PIN RTE_SSI_SLAVE_CS_PIN 230 #define SSI_SLAVE_CS0_MODE RTE_SSI_SLAVE_CS_MODE 231 #define SSI_SLAVE_CS0_PADSEL RTE_SSI_SLAVE_CS_PADSEL 232 #endif 233 #endif 234 235 #if defined(RTE_SSI_ULP_MASTER) && (RTE_SSI_ULP_MASTER == 1) 236 #define SSI_ULP_MASTER 1U 237 238 #if defined(RTE_SSI_ULP_MASTER_RX_DMA) && (RTE_SSI_ULP_MASTER_RX_DMA == 1) 239 #define SSI_ULP_MASTER_RX_DMA_Instance 1U 240 #define SSI_ULP_MASTER_RX_DMA_Channel RTE_SSI_ULP_MASTER_UDMA_RX_CH 241 #endif 242 243 #if defined(RTE_SSI_ULP_MASTER_TX_DMA) && (RTE_SSI_ULP_MASTER_TX_DMA == 1) 244 #define SSI_ULP_MASTER_TX_DMA_Instance 1U 245 #define SSI_ULP_MASTER_TX_DMA_Channel RTE_SSI_ULP_MASTER_UDMA_TX_CH 246 #endif 247 248 #if defined(RTE_SSI_ULP_MASTER_MISO) && (RTE_SSI_ULP_MASTER_MISO == 1) 249 #define SSI_ULP_MASTER_MISO_SEL 1U 250 #define SSI_ULP_MASTER_MISO_PORT RTE_SSI_ULP_MASTER_MISO_PORT 251 #define SSI_ULP_MASTER_MISO_PIN RTE_SSI_ULP_MASTER_MISO_PIN 252 #define SSI_ULP_MASTER_MISO_MODE RTE_SSI_ULP_MASTER_MISO_MODE 253 #endif 254 255 #if defined(RTE_SSI_ULP_MASTER_MOSI) && (RTE_SSI_ULP_MASTER_MOSI == 1) 256 #define SSI_ULP_MASTER_MOSI_SEL 1U 257 #define SSI_ULP_MASTER_MOSI_PORT RTE_SSI_ULP_MASTER_MOSI_PORT 258 #define SSI_ULP_MASTER_MOSI_PIN RTE_SSI_ULP_MASTER_MOSI_PIN 259 #define SSI_ULP_MASTER_MOSI_MODE RTE_SSI_ULP_MASTER_MOSI_MODE 260 #endif 261 262 #if defined(RTE_SSI_ULP_MASTER_SCK) && (RTE_SSI_ULP_MASTER_SCK == 1) 263 #define SSI_ULP_MASTER_SCK_SEL 1U 264 #define SSI_ULP_MASTER_SCK_PORT RTE_SSI_ULP_MASTER_SCK_PORT 265 #define SSI_ULP_MASTER_SCK_PIN RTE_SSI_ULP_MASTER_SCK_PIN 266 #define SSI_ULP_MASTER_SCK_MODE RTE_SSI_ULP_MASTER_SCK_MODE 267 #endif 268 269 #if defined(RTE_SSI_ULP_MASTER_CS0) && (RTE_SSI_ULP_MASTER_CS0 == 1) 270 #define SSI_ULP_MASTER_CS0_SEL 1U 271 #define SSI_ULP_MASTER_CS0_PORT RTE_SSI_ULP_MASTER_CS0_PORT 272 #define SSI_ULP_MASTER_CS0_PIN RTE_SSI_ULP_MASTER_CS0_PIN 273 #define SSI_ULP_MASTER_CS0_MODE RTE_SSI_ULP_MASTER_CS0_MODE 274 #endif 275 #if defined(RTE_SSI_ULP_MASTER_CS1) && (RTE_SSI_ULP_MASTER_CS1 == 1) 276 #define SSI_ULP_MASTER_CS1_SEL 1U 277 #define SSI_ULP_MASTER_CS1_PORT RTE_SSI_ULP_MASTER_CS1_PORT 278 #define SSI_ULP_MASTER_CS1_PIN RTE_SSI_ULP_MASTER_CS1_PIN 279 #define SSI_ULP_MASTER_CS1_MODE RTE_SSI_ULP_MASTER_CS1_MODE 280 #endif 281 #if defined(RTE_SSI_ULP_MASTER_CS2) && (RTE_SSI_ULP_MASTER_CS2 == 1) 282 #define SSI_ULP_MASTER_CS2_SEL 1U 283 #define SSI_ULP_MASTER_CS2_PORT RTE_SSI_ULP_MASTER_CS2_PORT 284 #define SSI_ULP_MASTER_CS2_PIN RTE_SSI_ULP_MASTER_CS2_PIN 285 #define SSI_ULP_MASTER_CS2_MODE RTE_SSI_ULP_MASTER_CS2_MODE 286 #endif 287 #endif 288 289 290 /* SPI Register Interface Definitions */ 291 #ifdef SSI_MASTER 292 #if (defined(SSI_MASTER_RX_DMA_Instance) || defined(SSI_MASTER_TX_DMA_Instance)) 293 #ifndef SSI_MASTER_RX_DMA_Instance 294 #error "SSI_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" 295 #endif 296 #ifndef SSI_MASTER_TX_DMA_Instance 297 #error "SSI_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" 298 #endif 299 #endif 300 #endif 301 302 #ifdef SSI_SLAVE 303 #if (defined(SSI_SLAVE_RX_DMA_Instance) || defined(SSI_SLAVE_TX_DMA_Instance)) 304 #ifndef SSI_SLAVE_RX_DMA_Instance 305 #error "SSI_SLAVE using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" 306 #endif 307 #ifndef SSI_SLAVE_TX_DMA_Instance 308 #error "SSI_SLAVE using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" 309 #endif 310 #endif 311 #endif 312 313 #ifdef SSI_ULP_MASTER 314 #if (defined(SSI_ULP_MASTER_RX_DMA_Instance) || defined(SSI_ULP_MASTER_TX_DMA_Instance)) 315 #ifndef SSI_ULP_MASTER_RX_DMA_Instance 316 #error "SSI_ULP_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" 317 #endif 318 #ifndef SSI_ULP_MASTER_TX_DMA_Instance 319 #error "SSI_ULP_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" 320 #endif 321 #endif 322 #endif 323 324 325 #if ((defined(SSI_MASTER) && defined(SSI_MASTER_RX_DMA_Instance)) || \ 326 (defined(SSI_SLAVE) && defined(SSI_SLAVE_RX_DMA_Instance)) || \ 327 (defined(SSI_ULP_MASTER) && defined(SSI_ULP_MASTER_RX_DMA_Instance))) 328 #define __SPI_DMA_RX 329 #endif 330 #if ((defined(SSI_MASTER) && defined(SSI_MASTER_TX_DMA_Instance)) || \ 331 (defined(SSI_SLAVE) && defined(SSI_SLAVE_TX_DMA_Instance)) || \ 332 (defined(SSI_ULP_MASTER) && defined(SSI_ULP_MASTER_TX_DMA_Instance))) 333 #define __SPI_DMA_TX 334 #endif 335 #if (defined(__SPI_DMA_RX) && defined(__SPI_DMA_TX)) 336 #define __SPI_DMA 337 #endif 338 339 /* Current driver status flag definition */ 340 #define SPI_INITIALIZED (1 << 0) // SPI initialized 341 #define SPI_POWERED (1 << 1) // SPI powered on 342 #define SPI_CONFIGURED (1 << 2) // SPI configured 343 #define SPI_DATA_LOST (1 << 3) // SPI data lost occurred 344 #define SPI_MODE_FAULT (1 << 4) // SPI mode fault occurred 345 346 347 #define SPI_CS0 0 348 #define SPI_CS1 1 349 #define SPI_CS2 2 350 #define SPI_CS3 3 351 352 /* SPI Pins Configuration */ 353 typedef const struct _SPI_PIN { 354 uint8_t port; ///< SPI GPIO port 355 uint8_t pin; ///< SPI GPIO pin 356 uint8_t mode; ///< SPI GPIO mode 357 uint8_t pad_sel; ///< SPI GPIO pad selection 358 }SPI_PIN; 359 360 // SPI Input/Output Configuration 361 typedef const struct _SPI_IO { 362 SPI_PIN *mosi; // Pointer to MOSI pin configuration 363 SPI_PIN *miso; // Pointer to MISO pin configuration 364 SPI_PIN *sck; // Pointer to SCK pin configuration 365 SPI_PIN *cs0; // Pointer to CS(CHIP SELECT) pin configuration 366 #ifdef SPI_MULTI_SLAVE 367 SPI_PIN *cs1; // Pointer to CS(CHIP SELECT) pin configuration 368 SPI_PIN *cs2; // Pointer to CS(CHIP SELECT) pin configuration 369 SPI_PIN *cs3; // Pointer to CS(CHIP SELECT) pin configuration 370 #endif 371 } SPI_IO; 372 373 // SPI DMA 374 typedef struct SPI_DMA 375 { 376 RSI_UDMA_CHA_CFG_T chnl_cfg; 377 uint8_t channel; // DMA Channel number 378 UDMA_SignalEvent_t cb_event; // DMA Event callback 379 } SPI_DMA; 380 381 /* SPI status */ 382 typedef struct SPI_STATUS { 383 uint8_t busy; // Transmitter/Receiver busy flag 384 uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) 385 uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) 386 } SPI_STATUS; 387 388 /* SPI Information (Run-time) */ 389 typedef struct SPI_INFO { 390 ARM_SPI_SignalEvent_t cb_event; // Event Callback 391 SPI_STATUS status; // Status flags 392 uint8_t state; // Current SPI state 393 uint32_t mode; // Current SPI mode 394 } SPI_INFO; 395 396 /* SPI Transfer Information (Run-Time) */ 397 typedef struct SPI_TRANSFER_INFO { 398 uint32_t num; // Total number of transfers 399 uint8_t *rx_buf; // Pointer to in data buffer 400 uint8_t *tx_buf; // Pointer to out data buffer 401 uint32_t rx_cnt; // Number of data received 402 uint32_t tx_cnt; // Number of data sent 403 uint32_t dump_val; // Variable for dumping DMA data 404 uint16_t def_val; // Default transfer value 405 } SPI_TRANSFER_INFO; 406 407 typedef struct _SPI_CLOCK 408 { 409 SSI_MST_CLK_SRC_SEL_T spi_clk_src; 410 ULP_SSI_CLK_SELECT_T ulp_spi_clk_src; 411 uint32_t divfact; 412 }SPI_CLOCK; 413 414 /* SPI Resources */ 415 typedef struct { 416 SSI0_Type *reg; // SPI peripheral register interface 417 SPI_IO io; // SPI pins configuration 418 IRQn_Type irq_num; // SPI IRQ number 419 SPI_DMA *rx_dma; // Receive stream register interface 420 SPI_DMA *tx_dma; // Transmit stream register interface 421 SPI_INFO *info; // SPI Run-time information 422 SPI_TRANSFER_INFO *xfer; // SPI transfer information 423 uint8_t instance_mode; 424 SPI_CLOCK clock; 425 426 } const SPI_RESOURCES; 427 428 void RSI_SPI_SetSlaveSelectNumber(uint8_t slavenumber); 429 void RSI_SPI_Slave_Disable(void); 430 void RSI_SPI_Slave_Set_CS_Init_State(void); 431 #endif /* __SPI_H */ 432
