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Searched refs:SRAM_BASE (Results 1 – 25 of 418) sorted by relevance

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/hal_silabs-latest/gecko/emlib/inc/
Dem_bus.h76 BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); in BUS_RamBitWrite()
113 BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); in BUS_RamBitRead()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_bus.h76 BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); in BUS_RamBitWrite()
113 BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); in BUS_RamBitRead()
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_core.c423 EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE)
424 && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE)));
/hal_silabs-latest/gecko/emlib/src/
Dem_core.c905 EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE)
906 && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE)));
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b100f128gm32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b100f128im32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b100f256gm32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b100f256im32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f128gm32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f128gm48.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f128im32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f256im32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f256im48.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f256gm32.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32pg1b200f256gm48.h182 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg309f32.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg309f64.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg310f32.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg310f64.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg322f32.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg322f64.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg350f32.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defm32hg350f64.h157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p133f256gm32.h196 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro
Defr32fg1p133f256gm48.h196 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ macro

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