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Searched refs:SOC_PLL_500_CTRL_REG9 (Results 1 – 3 of 3) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_pll.h211 #define SOC_PLL_500_CTRL_REG9 0x18 /* Address for SOC_PLL_500_CTRL_REG9 register Access*/ macro
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/
Drsi_rom_clks.h151 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = 0xD900; in RSI_CLK_SetSocPllFreq()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c2753 reg_read = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9); in clk_config_pll_lock()
2756 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = (uint16_t)reg_read; in clk_config_pll_lock()