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Searched refs:SOC_PLL_500_CTRL_REG7 (Results 1 – 2 of 2) sorted by relevance

/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/
Drsi_pll.c171 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; in clk_set_soc_pll_freq()
172 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); in clk_set_soc_pll_freq()
338 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; in clk_soc_pll_set_freq_div()
339 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); in clk_soc_pll_set_freq_div()
/hal_silabs-latest/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/
Drsi_pll.h209 #define SOC_PLL_500_CTRL_REG7 0x16 /* Address for SOC_PLL_500_CTRL_REG7 register Access*/ macro