1 /******************************************************************************
2 * @file  si91x_device.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
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19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 *    claim that you wrote the original software. If you use this software
22 *    in a product, an acknowledgment in the product documentation would be
23 *    appreciated but is not required.
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25 *    misrepresented as being the original software.
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28 ******************************************************************************/
29 
30 /** @addtogroup Silicon Lab Inc.
31  * @{
32  */
33 
34 /** @addtogroup RS1xxxx
35  * @{
36  */
37 
38 #ifndef __RS1XXXX_H__
39 #define __RS1XXXX_H__
40 
41 #include "base_types.h"
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
47 /** @addtogroup Configuration_of_CMSIS
48  * @{
49  */
50 
51 /* ===========================================================================================================================
52  */
53 /* ================                                Interrupt Number Definition
54  * ================ */
55 /* ===========================================================================================================================
56  */
57 
58 typedef enum {
59   /* =======================================  ARM Cortex-M4 Specific Interrupt
60      Numbers  ======================================== */
61   Reset_IRQn            = -15, /*!< -15  Reset Vector, invoked on Power up and warm reset */
62   NonMaskableInt_IRQn   = -14, /*!< -14  Non maskable Interrupt, cannot be stopped or preempted */
63   HardFault_IRQn        = -13, /*!< -13  Hard Fault, all classes of Fault        */
64   MemoryManagement_IRQn = -12, /*!< -12  Memory Management, MPU mismatch,
65                                   including Access Violation and No Match */
66   BusFault_IRQn         = -11, /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault,
67                              other address/memory    related Fault    */
68   UsageFault_IRQn       = -10, /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal
69                              State Transition        */
70   SVCall_IRQn           = -5,  /*!< -5 System Service Call via SVC instruction       */
71   DebugMonitor_IRQn     = -4,  /*!< -4 Debug Monitor */
72   PendSV_IRQn           = -2,  /*!< -2 Pendable request for system service       */
73   SysTick_IRQn          = -1,  /*!< -1 System Tick Timer      */
74   /* ==========================================  RS1xxxx Specific Interrupt
75      Numbers  =========================================== */
76   TIMER0_IRQn                = 2,  /*!< 2  TIMER0                 */
77   TIMER1_IRQn                = 3,  /*!< 3  TIMER1                 */
78   TIMER2_IRQn                = 4,  /*!< 4  TIMER2                 */
79   TIMER3_IRQn                = 5,  /*!< 5  TIMER3                 */
80   CAP_SENSOR_IRQn            = 6,  /*!< 6  CAP_SENSOR             */
81   COMP2_IRQn                 = 7,  /*!< 7  COMP2                  */
82   COMP1_IRQn                 = 8,  /*!< 8  COMP1                  */
83   UDMA1_IRQn                 = 10, /*!< 10 UDMA1                 */
84   ADC_IRQn                   = 11, /*!< 11 ADC                   */
85   ULPSS_UART_IRQn            = 12, /*!< 12 ULPSS_UART            */
86   I2C2_IRQn                  = 13, /*!< 13 I2C2                  */
87   I2S1_IRQn                  = 14, /*!< 14 I2S1                  */
88   IR_DECODER_IRQn            = 15, /*!< 15 IR_DECODER            */
89   SSI2_IRQn                  = 16, /*!< 16 SSI2                  */
90   FIM_IRQn                   = 17, /*!< 17 FIM                   */
91   ULP_EGPIO_PIN_IRQn         = 18, /*!< 18 ULP_EGPIO_PIN         */
92   ULP_EGPIO_GROUP_IRQn       = 19, /*!< 19 ULP_EGPIO_GROUP       */
93   NPSS_TO_MCU_WDT_INTR_IRQn  = 20, /*!< 20 NPSS_TO_MCU_WDT_INTR  */
94   NPSS_TO_MCU_GPIO_INTR_IRQn = 21, /*!< 21 NPSS_TO_MCU_GPIO_INTR */
95 #if defined(SLI_SI917B0) || defined(SLI_SI915)
96   NPSS_TO_MCU_SYRTC_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_SYSRTC_INTR */
97 #else
98   NPSS_TO_MCU_CMP_RF_WKP_INTR_IRQn = 22,               /*!< 22 NPSS_TO_MCU_CMP_RF_WKP_INTR                           */
99 #endif
100   NPSS_TO_MCU_BOD_INTR_IRQn      = 23, /*!< 23 NPSS_TO_MCU_BOD_INTR      */
101   NPSS_TO_MCU_BUTTON_INTR_IRQn   = 24, /*!< 24 NPSS_TO_MCU_BUTTON_INTR   */
102   NPSS_TO_MCU_SDC_INTR_IRQn      = 25, /*!< 25 NPSS_TO_MCU_SDC_INTR      */
103   NPSS_TO_MCU_WIRELESS_INTR_IRQn = 26, /*!< 26 NPSS_TO_MCU_WIRELESS_INTR */
104   NPSS_MCU_INTR_IRQn             = 27, /*!< 27 NPSS_MCU_INTR             */
105   MCU_CAL_ALARM_IRQn             = 28, /*!< 28 MCU_CAL_ALARM             */
106   MCU_CAL_RTC_IRQn               = 29, /*!< 29 MCU_CAL_RTC               */
107   GPDMA_IRQn                     = 31, /*!< 31 GPDMA                     */
108   UDMA0_IRQn                     = 33, /*!< 33 UDMA0                     */
109   CT_IRQn                        = 34, /*!< 34 CT                        */
110   HIF0_IRQn                      = 35, /*!< 35 HIF0                      */
111   HIF1_IRQn                      = 36, /*!< 36 HIF1                      */
112   SIO_IRQn                       = 37, /*!< 37 SIO                       */
113   USART0_IRQn                    = 38, /*!< 38 USART0                    */
114   UART1_IRQn                     = 39, /*!< 39 UART1                     */
115   EGPIO_WAKEUP_IRQn              = 41, /*!<  41  EGPIO_WAKEUP                  */
116   I2C0_IRQn                      = 42, /*!<  42  I2C0          */
117   SSISlave_IRQn                  = 44, /*!< 44 SSISlave      */
118   GSPI0_IRQn                     = 46, /*!< 46 GSPI0         */
119   SSI0_IRQn                      = 47, /*!< 47 SSI0          */
120   MCPWM_IRQn                     = 48, /*!< 48 MCPWM         */
121   QEI_IRQn                       = 49, /*!< 49 QEI           */
122   EGPIO_GROUP_0_IRQn             = 50, /*!< 50 EGPIO_GROUP_0 */
123   EGPIO_GROUP_1_IRQn             = 51, /*!< 51 EGPIO_GROUP_1 */
124   EGPIO_PIN_0_IRQn               = 52, /*!< 52 EGPIO_PIN_0   */
125   EGPIO_PIN_1_IRQn               = 53, /*!< 53 EGPIO_PIN_1   */
126   EGPIO_PIN_2_IRQn               = 54, /*!< 54 EGPIO_PIN_2   */
127   EGPIO_PIN_3_IRQn               = 55, /*!< 55 EGPIO_PIN_3   */
128   EGPIO_PIN_4_IRQn               = 56, /*!< 56 EGPIO_PIN_4   */
129   EGPIO_PIN_5_IRQn               = 57, /*!< 57 EGPIO_PIN_5   */
130   EGPIO_PIN_6_IRQn               = 58, /*!< 58 EGPIO_PIN_6   */
131   EGPIO_PIN_7_IRQn               = 59, /*!< 59 EGPIO_PIN_7   */
132   QSPI_IRQn                      = 60, /*!< 60 QSPI          */
133   I2C1_IRQn                      = 61, /*!< 61 I2C1          */
134 #if defined(SLI_SI917B0) || defined(SLI_SI915)
135   MVP_IRQn        = 62, /*!< 62  MVP        */
136   MVP_WAKEUP_IRQn = 63, /*!< 63  MVP_WAKEUP */
137 #endif
138   I2S0_IRQn      = 64, /*!< 64 I2S0      */
139   PLL_CLOCK_IRQn = 69, /*!< 69 PLL_CLOCK */
140   TASS_P2P_IRQn  = 74  /*!< 74 TASS_P2P   */
141 } IRQn_Type;
142 
143 /* ===========================================================================================================================
144  */
145 /* ================                           Processor and Core Peripheral
146  * Section                           ================ */
147 /* ===========================================================================================================================
148  */
149 
150 /* ===========================  Configuration of the ARM Cortex-M4 Processor and
151  * Core Peripherals  =========================== */
152 #define __CM4_REV              0x0100U /*!< CM4 Core Revision */
153 #define __NVIC_PRIO_BITS       6       /*!< Number of Bits used for Priority Levels */
154 #define __Vendor_SysTickConfig 0       /*!< Set to 1 if different SysTick Config is used */
155 #define __MPU_PRESENT          1       /*!< MPU present */
156 #define __FPU_PRESENT          1       /*!< FPU present */
157 
158 /** @} */ /* End of group Configuration_of_CMSIS */
159 
160 #include "core_cm4.h"     /*!< ARM Cortex-M4 processor and core peripherals                              */
161 #include "system_si91x.h" /*!< RS1xxxx System                                                            */
162 
163 #ifndef __IM /*!< Fallback for older CMSIS versions */
164 #define __IM __I
165 #endif
166 #ifndef __OM /*!< Fallback for older CMSIS versions */
167 #define __OM __O
168 #endif
169 #ifndef __IOM /*!< Fallback for older CMSIS versions */
170 #define __IOM __IO
171 #endif
172 
173 /* ========================================  Start of section using anonymous
174  * unions  ======================================== */
175 #if defined(__CC_ARM)
176 #pragma push
177 #pragma anon_unions
178 #elif defined(__ICCARM__)
179 #pragma language = extended
180 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
181 #pragma clang diagnostic push
182 #pragma clang diagnostic ignored "-Wc11-extensions"
183 #pragma clang diagnostic ignored "-Wreserved-id-macro"
184 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
185 #pragma clang diagnostic ignored "-Wnested-anon-types"
186 #elif defined(__GNUC__)
187 /* anonymous unions are enabled by default */
188 #elif defined(__TMS470__)
189 /* anonymous unions are enabled by default */
190 #elif defined(__TASKING__)
191 #pragma warning 586
192 #elif defined(__CSMC__)
193 /* anonymous unions are enabled by default */
194 #else
195 #warning Not supported compiler type
196 #endif
197 
198 /* ===========================================================================================================================
199  */
200 /* ================                              Device Specific Cluster Section
201  * ================ */
202 /* ===========================================================================================================================
203  */
204 
205 /** @addtogroup Device_Peripheral_clusters
206  * @{
207  */
208 
209 /**
210  * @brief MCPWM_PWM_DEADTIME [PWM_DEADTIME] ([0..3])
211  */
212 typedef struct {
213   union {
214     __IOM unsigned int PWM_DEADTIME_A; /*!< (@ 0x00000000) PWM deadtime for A and
215                                       channel varies from 0 to 3 */
216 
217     struct {
218       __IOM unsigned int DEADTIME_A_CH : 6; /*!< [5..0] Dead time A value to load into dead
219                                 time counter A of channel0 to channel3 */
220       __IOM unsigned int RESERVED1 : 26;    /*!< [31..6] reserved1 */
221     } PWM_DEADTIME_A_b;
222   };
223 
224   union {
225     __IOM unsigned int PWM_DEADTIME_B; /*!< (@ 0x00000004) PWM deadtime for B and
226                                       channel varies from 0 to 3 */
227 
228     struct {
229       __IOM unsigned int DEADTIME_B_CH : 6; /*!< [5..0] Dead time B value to load into deadtime
230                                 counter B of channel0 to channel3 */
231       __IOM unsigned int RESERVED1 : 26;    /*!< [31..6] reserved1 */
232     } PWM_DEADTIME_B_b;
233   };
234 } MCPWM_PWM_DEADTIME_Type; /*!< Size = 8 (0x8) */
235 
236 /**
237  * @brief GPDMA_G_GLOBAL [GLOBAL] (GLOBAL)
238  */
239 typedef struct {
240   union {
241     __IOM unsigned int INTERRUPT_REG; /*!< (@ 0x00000000) Interrupt Register */
242 
243     struct {
244       __IOM unsigned int GPDMAC_INT_STAT : 8; /*!< [7..0] Interrupt Status */
245       __IM unsigned int RESERVED1 : 24;       /*!< [31..8] reserved1       */
246     } INTERRUPT_REG_b;
247   };
248 
249   union {
250     __IOM unsigned int INTERRUPT_MASK_REG; /*!< (@ 0x00000004) Interrupt Mask Register */
251 
252     struct {
253       __IOM unsigned int RESERVED1 : 8;            /*!< [7..0] reserved1 */
254       __IOM unsigned int LINK_LIST_FETCH_MASK : 8; /*!< [15..8] Linked list fetch done
255                                            interrupt bit mask control. By     default,
256                                            descriptor fetch done interrupt is
257                                            masked.                       */
258       __IOM unsigned int TFR_DONE_MASK : 8;        /*!< [23..16] Transfer done interrupt
259                                            bit mask control. */
260       __IOM unsigned int RESERVED2 : 8;            /*!< [31..24] reserved2     */
261     } INTERRUPT_MASK_REG_b;
262   };
263 
264   union {
265     __IOM unsigned int INTERRUPT_STAT_REG; /*!< (@ 0x00000008) Interrupt status register */
266 
267     struct {
268       __IOM unsigned int HRESP_ERR0 : 1;            /*!< [0..0] DMA error bit */
269       __IOM unsigned int LINK_LIST_FETCH_DONE0 : 1; /*!< [1..1] This bit indicates the status
270                                         of linked list descriptor
271                                           fetch done for channel 0 */
272       __IOM unsigned int TFR_DONE0 : 1;             /*!< [2..2] This bit indicates the status of DMA
273                             transfer done interrupt for channel 0 */
274       __IOM unsigned int GPDMAC_ERR0 : 1;           /*!< [3..3] transfer size or burst size or
275                                          h size mismatch error               */
276       __IOM unsigned int HRESP_ERR1 : 1;            /*!< [4..4] HRESP error bit  */
277       __IOM unsigned int LINK_LIST_FETCH_DONE1 : 1; /*!< [5..5] This bit indicates the status
278                                         of linked list descriptor
279                                           fetch done for channel 1 */
280       __IOM unsigned int TFR_DONE1 : 1;             /*!< [6..6] This bit indicates the status of DMA
281                             transfer done interrupt for channel 1. */
282       __IOM unsigned int GPDMAC_ERR1 : 1;           /*!< [7..7] transfer size or burst size or
283                                          h size mismatch error               */
284       __IOM unsigned int HRESP_ERR2 : 1;            /*!< [8..8] HRESP error bit  */
285       __IOM unsigned int LINK_LIST_FETCH_DONE2 : 1; /*!< [9..9] This bit indicates the status
286                                         of linked list descriptor
287                                           fetch done for channel 2. */
288       __IOM unsigned int TFR_DONE2 : 1;             /*!< [10..10] This bit indicates the status of DMA
289                             transfer done interrupt for channel 2. */
290       __IOM unsigned int GPDMAC_ERR2 : 1;           /*!< [11..11] transfer size or burst size
291                                          or h size mismatch error             */
292       __IOM unsigned int HRESP_ERR3 : 1;            /*!< [12..12] HRESP error bit  */
293       __IOM unsigned int LINK_LIST_FETCH_DONE3 : 1; /*!< [13..13] This bit indicates the status
294                                         of linked list descriptor
295                                           fetch done for channel 3. */
296       __IOM unsigned int TFR_DONE3 : 1;             /*!< [14..14] This bit indicates the status of DMA
297                             transfer done interrupt for channel 3. */
298       __IOM unsigned int GPDMAC_ERR3 : 1;           /*!< [15..15] transfer size or burst size
299                                          or h size mismatch error             */
300       __IOM unsigned int HRESP_ERR4 : 1;            /*!< [16..16] HRESP error bit  */
301       __IOM unsigned int LINK_LIST_FETCH_DONE4 : 1; /*!< [17..17] This bit indicates the status
302                                         of linked list descriptor
303                                           fetch done for channel 4. */
304       __IOM unsigned int TFR_DONE4 : 1;             /*!< [18..18] This bit indicates the status of DMA
305                             transfer done interrupt for channel 4. */
306       __IOM unsigned int GPDMAC_ERR4 : 1;           /*!< [19..19] transfer size or burst size
307                                          or h size mismatch error             */
308       __IOM unsigned int HRESP_ERR5 : 1;            /*!< [20..20] HRESP error bit  */
309       __IOM unsigned int LINK_LIST_FETCH_DONE5 : 1; /*!< [21..21] This bit indicates the status
310                                         of linked list descriptor
311                                           fetch done for channel 5. */
312       __IOM unsigned int TFR_DONE5 : 1;             /*!< [22..22] This bit indicates the status of DMA
313                             transfer done interrupt for channel 5. */
314       __IOM unsigned int GPDMAC_ERR5 : 1;           /*!< [23..23] transfer size or burst size
315                                          or h size mismatch error             */
316       __IM unsigned int HRESP_ERR6 : 1;             /*!< [24..24] HRESP error bit   */
317       __IOM unsigned int LINK_LIST_FETCH_DONE6 : 1; /*!< [25..25] This bit indicates the status
318                                         of linked list descriptor
319                                           fetch done for channel 6. */
320       __IOM unsigned int TFR_DONE6 : 1;             /*!< [26..26] This bit indicates the status of DMA
321                             transfer done interrupt for channel 6. */
322       __IOM unsigned int GPDMAC_ERR6 : 1;           /*!< [27..27] transfer size or burst size
323                                          or h size mismatch error             */
324       __IOM unsigned int HRESP_ERR7 : 1;            /*!< [28..28] HRESP error bit  */
325       __IOM unsigned int LINK_LIST_FETCH_DONE7 : 1; /*!< [29..29] This bit indicates the status
326                                         of linked list descriptor
327                                           fetch done for channel 7. */
328       __IOM unsigned int TFR_DONE7 : 1;             /*!< [30..30] This bit indicates the status of DMA
329                             transfer done interrupt for channel 7. */
330       __IOM unsigned int GPDMAC_ERR7 : 1;           /*!< [31..31] transfer size or burst size
331                                          or h size mismatch error             */
332     } INTERRUPT_STAT_REG_b;
333   };
334 
335   union {
336     __IOM unsigned int DMA_CHNL_ENABLE_REG; /*!< (@ 0x0000000C) This register used
337                                            for enable DMA channel */
338 
339     struct {
340       __IOM unsigned int CH_ENB : 8;    /*!< [7..0] CWhen a bit is set to one, it indicates,
341                          corresponding channel is enabled for dma operation */
342       __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */
343     } DMA_CHNL_ENABLE_REG_b;
344   };
345 
346   union {
347     __IOM unsigned int DMA_CHNL_SQUASH_REG; /*!< (@ 0x00000010) This register used
348                                            for enable DMA channel squash */
349 
350     struct {
351       __IOM unsigned int CH_DIS : 8;    /*!< [7..0] CPU Will be masked to write zeros,
352                                     CPU is allowed write 1 only */
353       __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */
354     } DMA_CHNL_SQUASH_REG_b;
355   };
356 
357   union {
358     __IOM unsigned int DMA_CHNL_LOCK_REG; /*!< (@ 0x00000014) This register used for
359                                          enable DMA channel squash           */
360 
361     struct {
362       __IOM unsigned int CHNL_LOCK : 8; /*!< [7..0] When set entire DMA block transfer is done,
363                             before other DMA request is serviced */
364       __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */
365     } DMA_CHNL_LOCK_REG_b;
366   };
367 } GPDMA_G_GLOBAL_Type; /*!< Size = 24 (0x18) */
368 
369 /**
370  * @brief GPDMA_C_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..7])
371  */
372 typedef struct {
373   union {
374     __IOM unsigned int LINK_LIST_PTR_REGS; /*!< (@ 0x00000000) Link List Register
375                                           for channel 0 to 7 */
376 
377     struct {
378       __IOM unsigned int LINK_LIST_PTR_REG_CHNL : 32; /*!< [31..0] This is the address of the
379                                           memory location from which
380                                           we get our next descriptor */
381     } LINK_LIST_PTR_REGS_b;
382   };
383 
384   union {
385     __IOM unsigned int SRC_ADDR_REG_CHNL; /*!< (@ 0x00000004) Source Address
386                                          Register for channel 0 to 7 */
387 
388     struct {
389       __IOM unsigned int SRC_ADDR : 32; /*!< [31..0] This is the address of the memory location
390                             from which we get our next descriptor */
391     } SRC_ADDR_REG_CHNL_b;
392   };
393 
394   union {
395     __IOM unsigned int DEST_ADDR_REG_CHNL; /*!< (@ 0x00000008) Source Address
396                                           Register for channel 0 to 7 */
397 
398     struct {
399       __IOM unsigned int DEST_ADDR : 32; /*!< [31..0] This is the destination
400                                         address to whih the data is sent */
401     } DEST_ADDR_REG_CHNL_b;
402   };
403 
404   union {
405     __IOM unsigned int CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x0000000C) Channel Control
406                                              Register for channel 0 to 7 */
407 
408     struct {
409       __IOM unsigned int DMA_BLK_SIZE : 12;        /*!< [11..0] This is data to be transmitted. Loaded
410                                 at the beginning of the DMA transfer and
411                                 decremented at every dma transaction. */
412       __IOM unsigned int TRNS_TYPE : 2;            /*!< [13..12] DMA transfer type     */
413       __IOM unsigned int DMA_FLOW_CTRL : 2;        /*!< [15..14] DMA flow control */
414       __IOM unsigned int MSTR_IF_FETCH_SEL : 1;    /*!< [16..16] This selects the MASTER IF from
415                                     which data to be fetched         */
416       __IOM unsigned int MSTR_IF_SEND_SEL : 1;     /*!< [17..17] This selects the MASTER
417                                               IF from which data to be sent */
418       __IOM unsigned int DEST_DATA_WIDTH : 2;      /*!< [19..18] Data transfer to destination. */
419       __IOM unsigned int SRC_DATA_WIDTH : 2;       /*!< [21..20] Data transfer from source. */
420       __IOM unsigned int SRC_ALIGN : 1;            /*!< [22..22] Reserved.Value set to 0 We do not do any
421                             singles. We just do burst, save first 3 bytes in to
422                             residue buffer in one cycle,  In the next cycle send
423                             4 bytes to fifo, save 3 bytes in to residue. This
424                             continues on.                            */
425       __IOM unsigned int LINK_LIST_ON : 1;         /*!< [23..23] This mode is set, when we
426                                           do link listed operation */
427       __IOM unsigned int LINK_LIST_MSTR_SEL : 1;   /*!< [24..24] This mode is set, when we do
428                                      link listed operation               */
429       __IOM unsigned int SRC_ADDR_CONTIGUOUS : 1;  /*!< [25..25] Indicates Address is
430                                                  contiguous from previous */
431       __IOM unsigned int DEST_ADDR_CONTIGUOUS : 1; /*!< [26..26] Indicates Address is
432                                             contiguous from previous      */
433       __IOM unsigned int RETRY_ON_ERROR : 1;       /*!< [27..27] When this bit is set, if
434                                             we recieve HRESPERR, We will retry
435                                             the DMA for that channel. */
436       __IOM unsigned int LINK_INTERRUPT : 1;       /*!< [28..28] This bit is set in link list
437                                  descriptor.Hard ware will send an interrupt
438                                  when the DMA transfer is done for the
439                                           corresponding link list address */
440       __IOM unsigned int SRC_FIFO_MODE : 1;        /*!< [29..29] If set to 1; source address will not
441                                 be incremented(means fifo mode for source) */
442       __IOM unsigned int DEST_FIFO_MODE : 1;       /*!< [30..30] If set to 1; destination address
443                                  will not be incremented(means fifo mode for
444                                  destination) */
445       __IM unsigned int RESERVED1 : 1;             /*!< [31..31] Reserved1 */
446     } CHANNEL_CTRL_REG_CHNL_b;
447   };
448 
449   union {
450     __IOM unsigned int MISC_CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x00000010) Misc Channel Control
451                                        Register for channel 0                */
452 
453     struct {
454       __IOM unsigned int AHB_BURST_SIZE : 3;  /*!< [2..0] Burst size  */
455       __IOM unsigned int DEST_DATA_BURST : 6; /*!< [8..3] Burst writes in beats to
456                                              destination.(000000-64 beats
457                                                      .....111111-63 beats) */
458       __IOM unsigned int SRC_DATA_BURST : 6;  /*!< [14..9] Burst writes in beats from
459                                             source(000000-64 beats
460                                             .....111111-63 beats) */
461       __IOM unsigned int DEST_CHNL_ID : 6;    /*!< [20..15] This is the destination channel Id to
462                                which the data is sent. Must be set up prior to
463                                DMA_CHANNEL_ENABLE                       */
464       __IOM
465       unsigned int SRC_CHNL_ID : 6;           /*!< [26..21] This is the source channel Id,
466                                        from which the data is fetched. must be
467                                        set up prior to DMA_CHANNEL_ENABLE */
468       __IOM unsigned int DMA_PROT : 3;        /*!< [29..27] Protection level to go with the data. It
469                            will be concatenated with 1 b1 as there will be no
470                            opcode fetching and directly assign to hprot in AHB
471                            interface                                          */
472       __IOM unsigned int MEM_FILL_ENABLE : 1; /*!< [30..30] Enable for memory
473                                              filling with either 1s or 0s. */
474       __IOM unsigned int MEM_ONE_FILL : 1;    /*!< [31..31] Select for memory filling
475                                           with either 1s or 0s. */
476     } MISC_CHANNEL_CTRL_REG_CHNL_b;
477   };
478 
479   union {
480     __IOM unsigned int FIFO_CONFIG_REGS; /*!< (@ 0x00000014) FIFO Configuration
481                                         Register for channel 1 */
482 
483     struct {
484       __IOM unsigned int FIFO_STRT_ADDR : 6; /*!< [5..0] Starting row address of channel */
485       __IOM unsigned int FIFO_SIZE : 6;      /*!< [11..6] Channel size */
486       __IM unsigned int RESERVED1 : 20;      /*!< [31..12] Reserved1 */
487     } FIFO_CONFIG_REGS_b;
488   };
489 
490   union {
491     __IOM unsigned int PRIORITY_CHNL_REGS; /*!< (@ 0x00000018) Priority Register for
492                                           channel 0 to 7 */
493 
494     struct {
495       __IOM unsigned int PRIORITY_CH : 2; /*!< [1..0] Set a value between 2 b00 to 2 b11. The
496                               channel having highest number is the highest
497                               priority channel.                           */
498       __IM unsigned int RESERVED1 : 30;   /*!< [31..2] Reserved1 */
499     } PRIORITY_CHNL_REGS_b;
500   };
501   __IM unsigned int RESERVED[57];
502 } GPDMA_C_CHANNEL_CONFIG_Type; /*!< Size = 256 (0x100) */
503 
504 /**
505  * @brief TIMERS_MATCH_CTRL [MATCH_CTRL] ([0..3])
506  */
507 typedef struct {
508   union {
509     __IOM unsigned int MCUULP_TMR_MATCH; /*!< (@ 0x00000000) Timer Match Register */
510 
511     struct {
512       __IOM unsigned int TMR_MATCH : 32; /*!< [31..0] This bits are used to program the lower
513                              significant 16-bits of  timer time out value in
514                              millisecond or number of system clocks */
515     } MCUULP_TMR_MATCH_b;
516   };
517 
518   union {
519     __IOM unsigned int MCUULP_TMR_CNTRL; /*!< (@ 0x00000004) Timer Control Register */
520 
521     struct {
522       __OM unsigned int TMR_START : 1;        /*!< [0..0] This Bit are Used to start the timer timer
523                             gets reset upon setting this bit */
524       __OM unsigned int TMR_INTR_CLR : 1;     /*!< [1..1] This Bit are Used to clear the
525                                          timer                               */
526       __IOM unsigned int TMR_INTR_ENABLE : 1; /*!< [2..2] This Bit are Used to
527                                              enable the time out interrupt */
528       __IOM unsigned int TMR_TYPE : 2;        /*!< [4..3] This Bit are Used to select the
529                                       type of timer                      */
530       __IOM unsigned int TMR_MODE : 1;        /*!< [5..5] This Bit are Used to select the
531                                       mode working of timer              */
532       __OM unsigned int TMR_STOP : 1;         /*!< [6..6] This Bit are Used to stop the timer */
533       __IOM unsigned int COUNTER_UP : 1;      /*!< [7..7] For reading/tracking counter in
534                                         up counting this bit has to be set */
535       __IOM unsigned int RESERVED1 : 24;      /*!< [31..8] reserved1 */
536     } MCUULP_TMR_CNTRL_b;
537   };
538 } TIMERS_MATCH_CTRL_Type; /*!< Size = 8 (0x8) */
539 
540 /**
541  * @brief I2S0_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..3])
542  */
543 typedef struct {
544   union {
545     union {
546       __IM unsigned int I2S_LRBR; /*!< (@ 0x00000000) Left Receive Buffer Register */
547 
548       struct {
549         __IM unsigned int LRBR : 24;     /*!< [23..0] Data received serially from the
550                                     received channel input            */
551         __IM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */
552       } I2S_LRBR_b;
553     };
554 
555     union {
556       __OM unsigned int I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */
557 
558       struct {
559         __OM unsigned int LTHR : 24;     /*!< [23..0] The Left Stereo Data to be transmitted
560                           serially from the Transmitted channel output */
561         __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */
562       } I2S_LTHR_b;
563     };
564   };
565 
566   union {
567     union {
568       __IM unsigned int I2S_RRBR; /*!< (@ 0x00000004) Right Receive Buffer Register */
569 
570       struct {
571         __IM unsigned int RRBR : 24;     /*!< [23..0] The Right Stereo Data received serially from
572                           the received channel input through this register */
573         __IM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */
574       } I2S_RRBR_b;
575     };
576 
577     union {
578       __OM unsigned int I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */
579 
580       struct {
581         __OM unsigned int RTHR : 24;     /*!< [23..0] The Right Stereo Data to be transmitted
582                           serially from the Transmit channel output written
583                           through this register                 */
584         __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */
585       } I2S_RTHR_b;
586     };
587   };
588 
589   union {
590     __IOM unsigned int I2S_RER; /*!< (@ 0x00000008) Receive Enable Register */
591 
592     struct {
593       __IOM unsigned int RXCHEN : 1;     /*!< [0..0] This Bit enables/disables a receive channel
594                          independently of all other channels */
595       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
596     } I2S_RER_b;
597   };
598 
599   union {
600     __IOM unsigned int I2S_TER; /*!< (@ 0x0000000C) Transmit Enable Register */
601 
602     struct {
603       __IOM unsigned int TXCHEN : 1;     /*!< [0..0] This Bit enables/disables a transmit channel
604                          independently of all other channels */
605       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
606     } I2S_TER_b;
607   };
608 
609   union {
610     __IOM unsigned int I2S_RCR; /*!< (@ 0x00000010) Receive Configuration Register */
611 
612     struct {
613       __IOM unsigned int WLEN : 3;       /*!< [2..0] This Bits are used to program the desired data
614                        resolution of the receiver and enables LSB of the
615                        incoming left or right word */
616       __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */
617     } I2S_RCR_b;
618   };
619 
620   union {
621     __IOM unsigned int I2S_TCR; /*!< (@ 0x00000014) Transmit Configuration Register */
622 
623     struct {
624       __IOM unsigned int WLEN : 3;       /*!< [2..0] This Bits are used to program the desired data
625                        resolution of the transmitter and ensure that MSB of the
626                        data is transmitted first. */
627       __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */
628     } I2S_TCR_b;
629   };
630 
631   union {
632     __IM unsigned int I2S_ISR; /*!< (@ 0x00000018) Interrupt Status Register */
633 
634     struct {
635       __IM unsigned int RXDA : 1;       /*!< [0..0] Receive Data Available       */
636       __IM unsigned int RXFO : 1;       /*!< [1..1] Receive Data FIFO       */
637       __IM unsigned int RESERVED1 : 2;  /*!< [3..2] Reserved for future use  */
638       __IM unsigned int TXFE : 1;       /*!< [4..4] Transmit FIFO Empty       */
639       __IM unsigned int TXFO : 1;       /*!< [5..5] Transmit FIFO       */
640       __IM unsigned int RESERVED2 : 26; /*!< [31..6] Reserved for future use */
641     } I2S_ISR_b;
642   };
643 
644   union {
645     __IOM unsigned int I2S_IMR; /*!< (@ 0x0000001C) Interrupt Mask Register */
646 
647     struct {
648       __IOM unsigned int RXDAM : 1;      /*!< [0..0] RX Data Available Mask Interrupt            */
649       __IOM unsigned int RXFOM : 1;      /*!< [1..1] RX FIFO Overrun Mask Interrupt */
650       __IOM unsigned int RESERVED1 : 2;  /*!< [3..2] Reserved for future use  */
651       __IOM unsigned int TXFEM : 1;      /*!< [4..4] TX FIFO Empty Interrupt      */
652       __IOM unsigned int TXFOM : 1;      /*!< [5..5] TX FIFO Overrun Interrupt      */
653       __IOM unsigned int RESERVED2 : 26; /*!< [31..6] Reserved for future use */
654     } I2S_IMR_b;
655   };
656 
657   union {
658     __IM unsigned int I2S_ROR; /*!< (@ 0x00000020) Receive Overrun Register */
659 
660     struct {
661       __IM unsigned int RXCHO : 1;      /*!< [0..0] Read this bit to clear the RX FIFO
662                                   data overrun interrupt          */
663       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
664     } I2S_ROR_b;
665   };
666 
667   union {
668     __IM unsigned int I2S_TOR; /*!< (@ 0x00000024) Transmit Overrun Register */
669 
670     struct {
671       __IM unsigned int TXCHO : 1;      /*!< [0..0] Read this bit to clear the TX FIFO
672                                   data overrun interrupt          */
673       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
674     } I2S_TOR_b;
675   };
676 
677   union {
678     __IOM unsigned int I2S_RFCR; /*!< (@ 0x00000028) Receive FIFO Configuration Register0 */
679 
680     struct {
681       __IOM unsigned int RXCHDT : 4;     /*!< [3..0] This bits program the trigger level in the RX
682                          FIFO  at which the data available interrupt is
683                          generated                           */
684       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
685     } I2S_RFCR_b;
686   };
687 
688   union {
689     __IOM unsigned int I2S_TXFCR; /*!< (@ 0x0000002C) Transmit FIFO Configuration Register */
690 
691     struct {
692       __IOM
693       unsigned int TXCHET : 4;          /*!< [3..0] This bits program the trigger level
694                                   in the TX FIFO  at which the Empty Threshold
695                                   Reached interrupt is generated */
696       __IM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
697     } I2S_TXFCR_b;
698   };
699 
700   union {
701     __OM unsigned int I2S_RFF; /*!< (@ 0x00000030) Receive FIFO Flush */
702 
703     struct {
704       __OM unsigned int RXCHFR : 1;     /*!< [0..0] Writing a 1 to this register flushes an
705                          individual RX FIFO RX channel or block must be disable
706                          prior to writing to this bit */
707       __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
708     } I2S_RFF_b;
709   };
710 
711   union {
712     __OM unsigned int I2S_TFF; /*!< (@ 0x00000034) Transmit FIFO Flush */
713 
714     struct {
715       __OM unsigned int TXCHFR : 1;     /*!< [0..0] Writing a 1 to this register flushes an
716                          individual TX FIFO TX channel or block must be disable
717                          prior to writing to this bit */
718       __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
719     } I2S_TFF_b;
720   };
721   __IM unsigned int RSVD0;  /*!< (@ 0x00000038) none      */
722   __IM unsigned int RSVD1;  /*!< (@ 0x0000003C) none      */
723 } I2S0_CHANNEL_CONFIG_Type; /*!< Size = 64 (0x40) */
724 
725 /**
726  * @brief EGPIO_PIN_CONFIG [PIN_CONFIG] ([0..79])
727  */
728 typedef struct {
729   union {
730     __IOM unsigned int GPIO_CONFIG_REG; /*!< (@ 0x00000000) GPIO Configuration Register */
731 
732     struct {
733       __IOM unsigned int DIRECTION : 1;                 /*!< [0..0] Direction of the GPIO pin */
734       __IOM unsigned int PORTMASK : 1;                  /*!< [1..1] Port mask value  */
735       __IOM unsigned int MODE : 4;                      /*!< [5..2] GPIO Pin Mode Used for GPIO Pin Muxing */
736       __IOM unsigned int RESERVED1 : 2;                 /*!< [7..6] Reserved1 */
737       __IOM unsigned int GROUP_INTERRUPT1_ENABLE : 1;   /*!< [8..8] When set, the corresponding
738                                         GPIO is pin is selected for
739                                         group intr 1 generation */
740       __IOM unsigned int GROUP_INTERRUPT1_POLARITY : 1; /*!< [9..9] Decides the active value of
741                                           the pin to be considered for group
742                                           interrupt 1 generation */
743       __IOM unsigned int GROUP_INTERRUPT2_ENABLE : 1;   /*!< [10..10] When set, the corresponding
744                                         GPIO is pin is selected
745                                         for group intr 2 generation */
746       __IOM unsigned int GROUP_INTERRUPT2_POLARITY : 1; /*!< [11..11] Decides the active value
747                                           of the pin to be considered
748                                           for group interrupt 2 generation */
749       __IOM unsigned int RESERVED2 : 4;                 /*!< [15..12] Reserved2      */
750       __IOM unsigned int RESERVED3 : 16;                /*!< [31..16] Reserved3     */
751     } GPIO_CONFIG_REG_b;
752   };
753 
754   union {
755     __IOM unsigned int BIT_LOAD_REG; /*!< (@ 0x00000004) Bit Load */
756 
757     struct {
758       __IOM unsigned int BIT_LOAD : 1;   /*!< [0..0] Loads 0th bit on to the pin on write. And
759                            reads the value on pin on read into 0th bit */
760       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */
761     } BIT_LOAD_REG_b;
762   };
763 
764   union {
765     __IOM unsigned int WORD_LOAD_REG; /*!< (@ 0x00000008) Word Load */
766 
767     struct {
768       __IOM unsigned int WORD_LOAD : 16; /*!< [15..0] Loads 1 on the pin when any of the bit in
769                              load value is 1. On read pass the bit status into
770                              all bits.                          */
771       __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */
772     } WORD_LOAD_REG_b;
773   };
774   __IM unsigned int RESERVED;
775 } EGPIO_PIN_CONFIG_Type; /*!< Size = 16 (0x10) */
776 
777 /**
778  * @brief EGPIO_PORT_CONFIG [PORT_CONFIG] ([0..5])
779  */
780 typedef struct {
781   union {
782     __IOM unsigned int PORT_LOAD_REG; /*!< (@ 0x00000000) Port Load */
783 
784     struct {
785       __IOM unsigned int PORT_LOAD : 16; /*!< [15..0] Loads the value on to pin on write. And
786                              reads the value of load register on read */
787       __IM unsigned int RES : 16;        /*!< [31..16] RES */
788     } PORT_LOAD_REG_b;
789   };
790 
791   union {
792     __OM unsigned int PORT_SET_REG; /*!< (@ 0x00000004) Port Set Register */
793 
794     struct {
795       __OM unsigned int PORT_SET : 16;  /*!< [15..0] Sets the pin when corresponding bit is
796                             high. Writing zero has no effect. */
797       __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */
798     } PORT_SET_REG_b;
799   };
800 
801   union {
802     __OM unsigned int PORT_CLEAR_REG; /*!< (@ 0x00000008) Port Clear Register */
803 
804     struct {
805       __OM unsigned int PORT_CLEAR : 16; /*!< [15..0] Clears the pin when corresponding bit is
806                               high. Writing zero has no effect. */
807       __OM unsigned int RESERVED1 : 16;  /*!< [31..16] Reserved1 */
808     } PORT_CLEAR_REG_b;
809   };
810 
811   union {
812     __OM unsigned int PORT_MASKED_LOAD_REG; /*!< (@ 0x0000000C) Port Masked Load Register */
813 
814     struct {
815       __OM unsigned int PORT_MASKED_LOAD : 16; /*!< [15..0] Only loads into pins which are not
816                                     masked. On read, pass only status unmasked
817                                     pins */
818       __OM unsigned int RESERVED1 : 16;        /*!< [31..16] Reserved1 */
819     } PORT_MASKED_LOAD_REG_b;
820   };
821 
822   union {
823     __OM unsigned int PORT_TOGGLE_REG; /*!< (@ 0x00000010) Port Toggle Register */
824 
825     struct {
826       __OM unsigned int PORT_TOGGLE : 16; /*!< [15..0] Toggles the pin when corresponding bit
827                                is high. Writing zero has not effect. */
828       __OM unsigned int RESERVED1 : 16;   /*!< [31..16] Reserved1 */
829     } PORT_TOGGLE_REG_b;
830   };
831 
832   union {
833     __IM unsigned int PORT_READ_REG; /*!< (@ 0x00000014) Port Read Register */
834 
835     struct {
836       __IM unsigned int PORT_READ : 16; /*!< [15..0] Reads the value on GPIO pins
837                                        irrespective of the pin mode. */
838       __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */
839     } PORT_READ_REG_b;
840   };
841   __IM unsigned int RESERVED[2];
842 } EGPIO_PORT_CONFIG_Type; /*!< Size = 32 (0x20) */
843 
844 /**
845  * @brief EGPIO_INTR [INTR] ([0..5])
846  */
847 typedef struct {
848   union {
849     __IOM unsigned int GPIO_INTR_CTRL; /*!< (@ 0x00000000) GPIO Interrupt Control Register */
850 
851     struct {
852       __IOM unsigned int LEVEL_HIGH_ENABLE : 1; /*!< [0..0] enables interrupt generation when
853                                     pin level is 1                   */
854       __IOM unsigned int LEVEL_LOW_ENABLE : 1;  /*!< [1..1] enables interrupt generation when
855                                    pin level is 0                   */
856       __IOM unsigned int RISE_EDGE_ENABLE : 1;  /*!< [2..2] enables interrupt generation when
857                                    rising edge is detected on pin */
858       __IOM unsigned int FALL_EDGE_ENABLE : 1;  /*!< [3..3] enables interrupt generation when
859                                    Falling edge is detected on pin */
860       __IOM unsigned int MASK : 1;              /*!< [4..4] Masks the interrupt. Interrupt will still be
861                        seen in status register when enabled */
862       __IOM unsigned int RESERVED1 : 3;         /*!< [7..5] Reserved1   */
863       __IOM unsigned int PIN_NUMBER : 4;        /*!< [11..8] GPIO Pin to be chosen for
864                                          interrupt generation  */
865       __IOM unsigned int PORT_NUMBER : 2;       /*!< [13..12] GPIO Port to be chosen for
866                                          interrupt generation */
867       __IOM unsigned int RESERVED2 : 18;        /*!< [31..14] Reserved2  */
868     } GPIO_INTR_CTRL_b;
869   };
870 
871   union {
872     __IOM unsigned int GPIO_INTR_STATUS; /*!< (@ 0x00000004) GPIO Interrupt Status
873                                         Register                             */
874 
875     struct {
876       __IOM unsigned int INTERRUPT_STATUS : 1; /*!< [0..0] Gets set when interrupt
877                                               is enabled and occurs. */
878       __IOM unsigned int RISE_EDGE_STATUS : 1; /*!< [1..1] Gets set when rise edge
879                                               is enabled and occurs. */
880       __IOM unsigned int FALL_EDGE_STATUS : 1; /*!< [2..2] Gets set when Fall edge
881                                               is enabled and occurs. */
882       __OM unsigned int MASK_SET : 1;          /*!< [3..3] Mask set          */
883       __OM unsigned int MASK_CLEAR : 1;        /*!< [4..4] Mask Clear        */
884       __IOM unsigned int RESERVED1 : 27;       /*!< [31..5] Reserved1       */
885     } GPIO_INTR_STATUS_b;
886   };
887 } EGPIO_INTR_Type; /*!< Size = 8 (0x8) */
888 
889 /**
890  * @brief EGPIO_GPIO_GRP_INTR [GPIO_GRP_INTR] ([0..3])
891  */
892 typedef struct {
893   union {
894     __IOM unsigned int GPIO_GRP_INTR_CTRL_REG; /*!< (@ 0x00000000) GPIO Interrupt 0
895                                               Control Register */
896 
897     struct {
898       __IOM unsigned int AND_OR : 1;           /*!< [0..0] AND/OR     */
899       __IOM unsigned int LEVEL_EDGE : 1;       /*!< [1..1] Level/Edge */
900       __IOM unsigned int ENABLE_WAKEUP : 1;    /*!< [2..2] For wakeup generation, actual pin
901                                 status has to be seen(before double ranking
902                                 point) */
903       __IOM unsigned int ENABLE_INTERRUPT : 1; /*!< [3..3] Enable Interrupt */
904       __IOM unsigned int MASK : 1;             /*!< [4..4] Mask             */
905       __IOM unsigned int RESERVED1 : 27;       /*!< [31..5] Reserved1       */
906     } GPIO_GRP_INTR_CTRL_REG_b;
907   };
908 
909   union {
910     __IOM unsigned int GPIO_GRP_INTR_STS; /*!< (@ 0x00000004) GPIO Interrupt 0
911                                          Status Register */
912 
913     struct {
914       __IOM unsigned int INTERRUPT_STATUS : 1; /*!< [0..0] Interrupt status is available in
915                                        this bit when interrupt     is enabled and
916                                        generated.  When 1 is written, interrupt
917                                               gets cleared.     */
918       __IM unsigned int WAKEUP : 1;            /*!< [1..1] Double ranked version of wakeup.
919                                        Gets set when wakeup     is enabled and occurs.
920                                        When 1 is written it gets cleared     */
921       __IOM unsigned int RESERVED1 : 1;        /*!< [2..2] Reserved1 */
922       __IOM unsigned int MASK_SET : 1;         /*!< [3..3] Gives zero on read  */
923       __IOM unsigned int MASK_CLEAR : 1;       /*!< [4..4] Gives zero on read */
924       __IOM unsigned int RESERVED2 : 27;       /*!< [31..5] Reserved2 */
925     } GPIO_GRP_INTR_STS_b;
926   };
927 } EGPIO_GPIO_GRP_INTR_Type; /*!< Size = 8 (0x8) */
928 
929 /**
930  * @brief MCU_RET_NPSS_GPIO_CNTRL [NPSS_GPIO_CNTRL] ([0..4])
931  */
932 typedef struct {
933   union {
934     __IOM unsigned int NPSS_GPIO_CTRLS; /*!< (@ 0x00000000) NPSS GPIO Control register */
935 
936     struct {
937       __IOM unsigned int NPSS_GPIO_MODE : 3;     /*!< [2..0] NPSS GPIO 0 mode select.           */
938       __IOM unsigned int NPSS_GPIO_REN : 1;      /*!< [3..3] NPSS GPIO 0 Input Buffer
939                                            Enable.  1- Enable 0- Disable. */
940       __IOM unsigned int NPSS_GPIO_OEN : 1;      /*!< [4..4] NPSS GPIO 0 Output Buffer Enable.  1-
941                                 Input Direction 0- Output Direction. */
942       __IOM unsigned int NPSS_GPIO_OUT : 1;      /*!< [5..5] NPSS GPIO 0 Output value.        */
943       __IOM unsigned int RESERVED1 : 2;          /*!< [7..6] Reserved1 */
944       __IOM unsigned int NPSS_GPIO_POLARITY : 1; /*!< [8..8] NPSS GPIO 0 Polarity 1
945                                                 - When signal is High 0 - When
946                                                      signal is Ligh. */
947       __IOM unsigned int RESERVED2 : 7;          /*!< [15..9] Reserved2          */
948       __IOM unsigned int USE_ULPSS_PAD : 1;      /*!< [16..16] Input from ULPSS GPIOs.         */
949       __IOM unsigned int RESERVED3 : 15;         /*!< [31..17] Reserved3 */
950     } NPSS_GPIO_CTRLS_b;
951   };
952 } MCU_RET_NPSS_GPIO_CNTRL_Type; /*!< Size = 4 (0x4) */
953 
954 /**
955  * @brief ULPCLK_ULP_SOC_GPIO_MODE_REG [ULP_SOC_GPIO_MODE_REG] ([0..15])
956  */
957 typedef struct {
958   union {
959     __IOM unsigned int ULP_SOC_GPIO_MODE_REG; /*!< (@ 0x00000000) ulp soc gpio mode
960                                              register */
961 
962     struct {
963       __IOM unsigned int ULP_SOC_GPIO_MODE_REG : 3; /*!< [2..0] mode bits for soc gpio. */
964       __IOM unsigned int RESERVED1 : 29;            /*!< [31..3] reserved1 */
965     } ULP_SOC_GPIO_MODE_REG_b;
966   };
967 } ULPCLK_ULP_SOC_GPIO_MODE_REG_Type; /*!< Size = 4 (0x4) */
968 
969 /**
970  * @brief AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG [ADC_CH_BIT_MAP_CONFIG]
971  * ([0..15])
972  */
973 typedef struct {
974   union {
975     __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_0; /*!< (@ 0x00000000) This is configuration
976                                     register0 to explain the bit map for ADC
977                                     channels */
978 
979     struct {
980       __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */
981     } ADC_CH_BIT_MAP_CONFIG_0_b;
982   };
983 
984   union {
985     __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_1; /*!< (@ 0x00000004) This is configuration
986                                     register1 to explain the bit map for ADC
987                                     channels */
988 
989     struct {
990       __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */
991     } ADC_CH_BIT_MAP_CONFIG_1_b;
992   };
993 
994   union {
995     __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_2; /*!< (@ 0x00000008) This is configuration
996                                     register2 to explain the bit map for ADC
997                                     channels */
998 
999     struct {
1000       __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */
1001     } ADC_CH_BIT_MAP_CONFIG_2_b;
1002   };
1003 
1004   union {
1005     __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_3; /*!< (@ 0x0000000C) This is configuration
1006                                     register3 to explain the bit map for ADC
1007                                     channels */
1008 
1009     struct {
1010       __IOM unsigned int CHANNEL_BITMAP : 5; /*!< [4..0] ADC Channels bit map */
1011       __IOM unsigned int RESERVED1 : 27;     /*!< [31..5] Reserved1     */
1012     } ADC_CH_BIT_MAP_CONFIG_3_b;
1013   };
1014 } AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type; /*!< Size = 16 (0x10) */
1015 
1016 /** @} */ /* End of group Device_Peripheral_clusters */
1017 
1018 /* ===========================================================================================================================
1019  */
1020 /* ================                            Device Specific Peripheral
1021  * Section                             ================ */
1022 /* ===========================================================================================================================
1023  */
1024 
1025 /** @addtogroup Device_Peripheral_peripherals
1026  * @{
1027  */
1028 
1029 /* ===========================================================================================================================
1030  */
1031 /* ================                                           I2C0
1032  * ================ */
1033 /* ===========================================================================================================================
1034  */
1035 
1036 /**
1037   * @brief Inter Integrated Circuit(I2C) is programmable control bus that
1038   provides support for the communications link between integrated circuits in a
1039   system (I2C0)
1040   */
1041 
1042 typedef struct { /*!< (@ 0x44010000) I2C0 Structure */
1043 
1044   union {
1045     __IOM unsigned int IC_CON; /*!< (@ 0x00000000) This register can be written only
1046                               when the i2c is disabled, which corresponds to
1047                               IC_ENABLE[0] being set to 0. Writes at other times
1048                               have no effect. */
1049 
1050     struct {
1051       __IOM unsigned int MASTER_MODE : 1;                /*!< [0..0] This bit controls whether the
1052                                          I2C master is enabled.               */
1053       __IOM unsigned int SPEED : 2;                      /*!< [2..1] These bits control at which speed
1054                                    the I2C operates. Hardware protects against
1055                                    illegal values being programmed by software.
1056                                  */
1057       __IOM unsigned int IC_10BITADDR_SLAVE : 1;         /*!< [3..3] When acting as a slave,
1058                                                 this bit controls whether the
1059                                                      I2C responds  to 7- or
1060                                                 10-bit addresses. */
1061       __IM unsigned int IC_10BITADDR_MASTER_RD_ONLY : 1; /*!< [4..4] the function of this bit
1062                                               is handled by bit 12 of IC_TAR
1063                                                        register, and becomes  a
1064                                               read-only copy called
1065                                               IC_10BITADDR_MASTER_rd_onl
1066                                                                                                                                  */
1067       __IOM unsigned int IC_RESTART_EN : 1;              /*!< [5..5] Determines whether RESTART conditions
1068                                 may be sent when acting as a master */
1069       __IOM unsigned int IC_SLAVE_DISABLE : 1;           /*!< [6..6] This bit controls whether
1070                                               I2C has its slave disabled */
1071       __IOM unsigned int STOP_DET_IFADDRESSED : 1;       /*!< [7..7] The STOP DETECTION interrupt is
1072                                        generated only when the transmitted
1073                                        address matches the slave address of SAR
1074                                      */
1075       __IOM unsigned int TX_EMPTY_CTRL : 1;              /*!< [8..8] This bit controls the
1076                                            generation of the TX EMPTY interrupt,
1077                                               as described in the IC RAW INTR
1078                                            STAT register. */
1079       __IM unsigned int RESERVED1 : 1;                   /*!< [9..9] reserved1      */
1080       __IOM unsigned int STOP_DET_IF_MASTER_ACTIVE : 1;  /*!< [10..10] In Master mode. */
1081       __IOM unsigned int BUS_CLEAR_FEATURE_CTRL : 1;     /*!< [11..11] In Master mode. */
1082       __IOM unsigned int RESERVED2 : 20;                 /*!< [31..12] reserved2  */
1083     } IC_CON_b;
1084   };
1085 
1086   union {
1087     __IOM unsigned int IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register */
1088 
1089     struct {
1090       __IOM unsigned int IC_TAR : 10;             /*!< [9..0] This is the target address for any
1091                                      master transaction              */
1092       __IOM unsigned int GC_OR_START : 1;         /*!< [10..10] If bit 11 (SPECIAL) is set
1093                                          to 1, then this bit indicates whether a
1094                                          General Call or START byte command  is
1095                                          to be performed by the DW_apb_i2c */
1096       __IOM unsigned int SPECIAL : 1;             /*!< [11..11] This bit indicates whether software
1097                           performs a General Call or START BYTE command */
1098       __IOM unsigned int IC_10BITADDR_MASTER : 1; /*!< [12..12] This bit controls
1099                                                  whether the i2c starts its
1100                                                  transfers in 7-or 10-bit
1101                                                  addressing mode when acting as
1102                                                  a master                    */
1103       __IOM unsigned int DEVICE_ID : 1;           /*!< [13..13] If bit 11 (SPECIAL) is set to 1, then
1104                             this bit indicates whether a Device-ID of a
1105                             particular slave mentioned in IC_TAR[6:0] is to be
1106                             performed by the I2C Master */
1107       __IM unsigned int RESERVED1 : 18;           /*!< [31..14] reserved1 */
1108     } IC_TAR_b;
1109   };
1110 
1111   union {
1112     __IOM unsigned int IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */
1113 
1114     struct {
1115       __IOM unsigned int IC_SAR : 10;   /*!< [9..0] The IC_SAR holds the slave address when the
1116                           I2C is operating as a slave. For 7-bit addressing,
1117                           only IC_SAR[6:0] is used.               */
1118       __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */
1119     } IC_SAR_b;
1120   };
1121 
1122   union {
1123     __IOM unsigned int IC_HS_MADDR; /*!< (@ 0x0000000C) I2C High Speed Master Mode
1124                                    Code Address Register           */
1125 
1126     struct {
1127       __IOM unsigned int IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value
1128                                        of the I2C HS mode master code */
1129       __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */
1130     } IC_HS_MADDR_b;
1131   };
1132 
1133   union {
1134     __IOM unsigned int IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and
1135                                    Command Register                 */
1136 
1137     struct {
1138       __IOM unsigned int DAT : 8;            /*!< [7..0] This register contains the data to be
1139                                  transmitted or received on the I2C bus */
1140       __OM unsigned int CMD : 1;             /*!< [8..8] This bit controls whether a read or a
1141                                  write is performed           */
1142       __OM unsigned int STOP : 1;            /*!< [9..9] This bit controls whether a STOP is
1143                                  issued after the byte is sent or received */
1144       __OM unsigned int RESTART : 1;         /*!< [10..10] This bit controls whether a RESTART is
1145                           issued before the byte is sent or received */
1146       __IM unsigned int FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte
1147                                        received after the address      phase for receive
1148                                        transfer in Master receiver or Slave
1149                                                 receiver mode      */
1150       __IM unsigned int RESERVED1 : 20;      /*!< [31..12] reserved1 */
1151     } IC_DATA_CMD_b;
1152   };
1153 
1154   union {
1155     __IOM unsigned int IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock
1156                                       SCL High Count Register           */
1157 
1158     struct {
1159       __IOM unsigned int IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any
1160                                   I2C bus transaction can take place to ensure
1161                                   proper I/O timing */
1162       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1 */
1163     } IC_SS_SCL_HCNT_b;
1164   };
1165 
1166   union {
1167     __IOM unsigned int IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock
1168                                       SCL Low Count Register            */
1169 
1170     struct {
1171       __IOM unsigned int IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any
1172                                   I2C bus transaction can take place to ensure
1173                                   proper I/O timing */
1174       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1 */
1175     } IC_SS_SCL_LCNT_b;
1176   };
1177 
1178   union {
1179     __IOM unsigned int IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL
1180                                       High Count Register               */
1181 
1182     struct {
1183       __IOM unsigned int IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any
1184                                   I2C bus transaction can take place to ensure
1185                                   proper I/O timing */
1186       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1 */
1187     } IC_FS_SCL_HCNT_b;
1188   };
1189 
1190   union {
1191     __IOM unsigned int IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL
1192                                       Low Count Register                */
1193 
1194     struct {
1195       __IOM unsigned int IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any
1196                                   I2C bus transaction can take place to ensure
1197                                   proper I/O timing */
1198       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1 */
1199     } IC_FS_SCL_LCNT_b;
1200   };
1201 
1202   union {
1203     __IOM unsigned int IC_HS_SCL_HCNT; /*!< (@ 0x00000024) High Speed I2C Clock SCL
1204                                       High Count Register               */
1205 
1206     struct {
1207       __IOM unsigned int IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any
1208                                   I2C bus transaction can take place to ensure
1209                                   proper I/O timing */
1210       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1 */
1211     } IC_HS_SCL_HCNT_b;
1212   };
1213 
1214   union {
1215     __IOM unsigned int IC_HS_SCL_LCNT; /*!< (@ 0x00000028) High Speed I2C Clock SCL
1216                                       Low Count Register                */
1217 
1218     struct {
1219       __IOM unsigned int IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any
1220                                   I2C bus transaction can take place to ensure
1221                                   proper I/O timing */
1222       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1 */
1223     } IC_HS_SCL_LCNT_b;
1224   };
1225 
1226   union {
1227     __IM unsigned int IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register */
1228 
1229     struct {
1230       __IM unsigned int R_RX_UNDER : 1;         /*!< [0..0] Set if the processor attempts to
1231                                        read the receive buffer
1232                                                   when it is empty by reading
1233                                        from the IC_DATA_CMD register */
1234       __IM unsigned int R_RX_OVER : 1;          /*!< [1..1] Set if the receive buffer is completely
1235                             filled to IC_RX_BUFFER_DEPTH and an additional byte
1236                             is received from an external I2C device */
1237       __IM unsigned int R_RX_FULL : 1;          /*!< [2..2] Set when the receive buffer
1238                                       reaches or goes above the  RX_TL threshold
1239                                       in the IC_RX_TL register.  */
1240       __IM unsigned int R_TX_OVER : 1;          /*!< [3..3] Set during transmit if the
1241                                       transmit buffer is filled to
1242                                       IC_TX_BUFFER_DEPTH and the processor
1243                                       attempts to issue another I2C command by
1244                                       writing to the IC_DATA_CMD register. */
1245       __IM unsigned int R_TX_EMPTY : 1;         /*!< [4..4] This bit is set to 1 when the transmit
1246                              buffer is at or below the threshold value set in
1247                              the IC_TX_TL register.                   */
1248       __IM unsigned int R_RD_REQ : 1;           /*!< [5..5] This bit is set to 1 when DW_apb_i2c is
1249                            acting as a slave and another I2C master is
1250                            attempting to read data from DW_apb_i2c. */
1251       __IM unsigned int R_TX_ABRT : 1;          /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C
1252                             transmitter, is unable to complete the intended
1253                             actions on the contents of the transmit FIFO */
1254       __IM unsigned int R_RX_DONE : 1;          /*!< [7..7] When the DW_apb_i2c is acting as a
1255                             slave-transmitter, this bit is set to 1 if the
1256                             master does not acknowledge a transmitted byte */
1257       __IM unsigned int R_ACTIVITY : 1;         /*!< [8..8] This bit captures DW_apb_i2c activity and
1258                              stays set until it is cleared */
1259       __IM unsigned int R_STOP_DET : 1;         /*!< [9..9] Indicates whether a STOP
1260                                         condition has occurred on the   I2C
1261                                         interface regardless of whether DW_apb_i2c
1262                                         is operating   in slave or master mode.   */
1263       __IM unsigned int R_START_DET : 1;        /*!< [10..10] Indicates whether a START or
1264                                         RESTART condition has occurred on the
1265                                         I2C interface regardless of  whether
1266                                         DW_apb_i2c is operating in slave or
1267                                         master mode. */
1268       __IM unsigned int R_GEN_CALL : 1;         /*!< [11..11] Set only when a General Call address is
1269                              received and it is acknowledged */
1270       __IM unsigned int R_RESTART_DET : 1;      /*!< [12..12] Indicates whether a RESTART condition
1271                                 has occurred on the I2C interface when
1272                                 DW_apb_i2c is operating in slave mode and the
1273                                 slave is the addressed slave */
1274       __IM unsigned int R_MST_ON_HOLD : 1;      /*!< [13..13] Indicates whether a master is holding
1275                                 the bus and the Tx FIFO is empty. */
1276       __IM unsigned int M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the
1277                                                SCL Line is stuck at low for
1278                                                      the IC_SCL_STUCK_LOW_TIMOUT
1279                                                number of ic_clk periods */
1280       __IM unsigned int RESERVED1 : 17;         /*!< [31..15] reserved1         */
1281     } IC_INTR_STAT_b;
1282   };
1283 
1284   union {
1285     __IOM unsigned int IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register */
1286 
1287     struct {
1288       __IOM unsigned int M_RX_UNDER : 1;         /*!< [0..0] This bit mask their
1289                                         corresponding interrupt status bits in
1290                                         the IC_INTR_STAT register. */
1291       __IOM unsigned int M_RX_OVER : 1;          /*!< [1..1] This bit mask their corresponding interrupt
1292                             status bits in the IC_INTR_STAT register. */
1293       __IOM unsigned int M_RX_FULL : 1;          /*!< [2..2] This bit mask their corresponding interrupt
1294                             status bits in the IC_INTR_STAT register. */
1295       __IOM unsigned int M_TX_OVER : 1;          /*!< [3..3] This bit mask their corresponding interrupt
1296                             status bits in the IC_INTR_STAT register */
1297       __IOM unsigned int M_TX_EMPTY : 1;         /*!< [4..4] This bit mask their
1298                                         corresponding interrupt status bits in
1299                                         the IC_INTR_STAT register. */
1300       __IOM unsigned int M_RD_REQ : 1;           /*!< [5..5] This bit mask their corresponding interrupt
1301                            status bits in the IC_INTR_STAT register. */
1302       __IOM unsigned int M_TX_ABRT : 1;          /*!< [6..6] This bit mask their corresponding interrupt
1303                             status bits in the IC_INTR_STAT register. */
1304       __IOM unsigned int M_RX_DONE : 1;          /*!< [7..7] This bit mask their corresponding interrupt
1305                             status bits in the IC_INTR_STAT register. */
1306       __IOM unsigned int M_ACTIVITY : 1;         /*!< [8..8] This bit mask their
1307                                         corresponding interrupt status bits in
1308                                         the IC_INTR_STAT register. */
1309       __IOM unsigned int M_STOP_DET : 1;         /*!< [9..9] This bit mask their
1310                                         corresponding interrupt status bits in
1311                                         the IC_INTR_STAT register. */
1312       __IOM unsigned int M_START_DET : 1;        /*!< [10..10] This bit mask their corresponding
1313                               interrupt status bits in the IC_INTR_STAT
1314                               register. */
1315       __IOM unsigned int M_GEN_CALL : 1;         /*!< [11..11] This bit mask their
1316                                         corresponding interrupt status bits in
1317                                         the IC_INTR_STAT register. */
1318       __IOM unsigned int M_RESTART_DET : 1;      /*!< [12..12] Indicates whether a RESTART condition
1319                                 has occurred on the I2C interface when
1320                                 DW_apb_i2c is operating in slave mode and the
1321                                 slave is the addressed slave */
1322       __IOM unsigned int M_MST_ON_HOLD : 1;      /*!< [13..13] Indicates whether a master is holding
1323                                 the bus and the Tx FIFO is empty. */
1324       __IOM unsigned int M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the
1325                                                 SCL Line is stuck at low for
1326                                                      the IC_SCL_STUCK_LOW_TIMOUT
1327                                                 number of ic_clk periods */
1328       __IM unsigned int RESERVED1 : 17;          /*!< [31..15] reserved1          */
1329     } IC_INTR_MASK_b;
1330   };
1331 
1332   union {
1333     __IM unsigned int IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status
1334                                        Register                          */
1335 
1336     struct {
1337       __IM unsigned int RX_UNDER : 1;         /*!< [0..0] Set if the processor attempts to read the
1338                            receive buffer when it is empty by reading from the
1339                            IC_DATA_CMD register                 */
1340       __IM unsigned int RX_OVER : 1;          /*!< [1..1] Set if the receive buffer is completely
1341                           filled to IC_RX_BUFFER_DEPTH and an additional byte is
1342                           received from an external I2C device */
1343       __IM unsigned int RX_FULL : 1;          /*!< [2..2] Set when the receive buffer reaches
1344                                     or goes above the RX_TL threshold in the
1345                                     IC_RX_TL register. */
1346       __IM unsigned int TX_OVER : 1;          /*!< [3..3] Set during transmit if the transmit buffer is
1347                           filled to IC_TX_BUFFER_DEPTH and the processor
1348                           attempts to issue another I2C command by writing to
1349                           the IC_DATA_CMD register.               */
1350       __IM unsigned int TX_EMPTY : 1;         /*!< [4..4] This bit is set to 1 when the
1351                                      transmit buffer is at or below the
1352                                      threshold value set in the IC_TX_TL
1353                                      register.                   */
1354       __IM unsigned int RD_REQ : 1;           /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting
1355                          as a slave and another I2C master is attempting to read
1356                          data from DW_apb_i2c. */
1357       __IM unsigned int TX_ABRT : 1;          /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C
1358                           transmitter, is unable to complete the intended
1359                           actions on the contents of the transmit FIFO */
1360       __IM unsigned int RX_DONE : 1;          /*!< [7..7] When the DW_apb_i2c is acting as a
1361                           slave-transmitter, this bit is set to 1 if the master
1362                           does not acknowledge a transmitted byte */
1363       __IM unsigned int ACTIVITY : 1;         /*!< [8..8] This bit captures DW_apb_i2c activity and
1364                            stays set until it is cleared */
1365       __IM unsigned int STOP_DET : 1;         /*!< [9..9] Indicates whether a STOP condition has
1366                            occurred on the I2C interface regardless of whether
1367                            DW_apb_i2c is operating in slave or master mode. */
1368       __IM unsigned int START_DET : 1;        /*!< [10..10] Indicates whether a START or RESTART
1369                             condition has occurred on the I2C interface
1370                             regardless of  whether DW_apb_i2c is operating in
1371                             slave or master mode. */
1372       __IM unsigned int GEN_CALL : 1;         /*!< [11..11] Set only when a General Call address is
1373                            received and it is acknowledged */
1374       __IM unsigned int RESTART_DET : 1;      /*!< [12..12] Indicates whether a RESTART condition
1375                               has occurred on the I2C interface when DW_apb_i2c
1376                               is operating in slave mode and the slave is the
1377                               addressed slave                                 */
1378       __IM unsigned int MST_ON_HOLD : 1;      /*!< [13..13] Indicates whether a master is holding
1379                               the bus and the Tx FIFO is empty. */
1380       __IM unsigned int SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the
1381                                              SCL Line is stuck at low for the
1382                                              IC_SCL_STUCK_LOW_TIMOUT number of
1383                                              ic_clk periods */
1384       __IM unsigned int RESERVED1 : 17;       /*!< [31..15] reserved1       */
1385     } IC_RAW_INTR_STAT_b;
1386   };
1387 
1388   union {
1389     __IOM unsigned int IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */
1390 
1391     struct {
1392       __IOM unsigned int RX_TL : 8;     /*!< [7..0] Receive FIFO Threshold Level     */
1393       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
1394     } IC_RX_TL_b;
1395   };
1396 
1397   union {
1398     __IOM unsigned int IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */
1399 
1400     struct {
1401       __IOM unsigned int TX_TL : 8;     /*!< [7..0] Transmit FIFO Threshold Level     */
1402       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
1403     } IC_TX_TL_b;
1404   };
1405 
1406   union {
1407     __IM unsigned int IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual
1408                                   Interrupt Register           */
1409 
1410     struct {
1411       __IM unsigned int CLR_INTR : 1;   /*!< [0..0] Read this register to clear the combined
1412                            interrupt, all individual interrupts, and the
1413                            IC_TXABRT_SOURCE register                  */
1414       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
1415     } IC_CLR_INTR_b;
1416   };
1417 
1418   union {
1419     __IM unsigned int IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt
1420                                       Register                          */
1421 
1422     struct {
1423       __IM unsigned int CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear
1424                                          the RX_UNDER interrupt (bit 0) of the
1425                                          IC_RAW_INTR_STAT register. */
1426       __IM unsigned int RESERVED1 : 31;   /*!< [31..1] reserved1   */
1427     } IC_CLR_RX_UNDER_b;
1428   };
1429 
1430   union {
1431     __IM unsigned int IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt
1432                                      Register                           */
1433 
1434     struct {
1435       __IM unsigned int CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the
1436                                         RX_OVER interrupt (bit 1) of the
1437                                         IC_RAW_INTR_STAT register */
1438       __IM unsigned int RESERVED1 : 31;  /*!< [31..1] reserved1  */
1439     } IC_CLR_RX_OVER_b;
1440   };
1441 
1442   union {
1443     __IM unsigned int IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt
1444                                      Register                           */
1445 
1446     struct {
1447       __IM unsigned int CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the
1448                                         TX_OVER interrupt (bit 3) of the
1449                                         IC_RAW_INTR_STAT register. */
1450       __IM unsigned int RESERVED1 : 31;  /*!< [31..1] reserved1  */
1451     } IC_CLR_TX_OVER_b;
1452   };
1453 
1454   union {
1455     __IM unsigned int IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */
1456 
1457     struct {
1458       __IM unsigned int CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the
1459                                        RD_REQ interrupt (bit 5) of the
1460                                        IC_RAW_INTR_STAT register. */
1461       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
1462     } IC_CLR_RD_REQ_b;
1463   };
1464 
1465   union {
1466     __IM unsigned int IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt
1467                                      Register                           */
1468 
1469     struct {
1470       __IM unsigned int CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT
1471                               interrupt (bit 6) of the C_RAW_INTR_STAT register,
1472                               and the IC_TX_ABRT_SOURCE register */
1473       __IM unsigned int RESERVED1 : 31;  /*!< [31..1] reserved1 */
1474     } IC_CLR_TX_ABRT_b;
1475   };
1476 
1477   union {
1478     __IM unsigned int IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt
1479                                      Register                           */
1480 
1481     struct {
1482       __IM unsigned int CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the
1483                                         RX_DONE interrupt (bit 7) of the
1484                                         IC_RAW_INTR_STAT register */
1485       __IM unsigned int RESERVED1 : 31;  /*!< [31..1] reserved1  */
1486     } IC_CLR_RX_DONE_b;
1487   };
1488 
1489   union {
1490     __IM unsigned int IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt
1491                                       Register                          */
1492 
1493     struct {
1494       __IM unsigned int CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears
1495                                          the ACTIVITY interrupt if the I2C is
1496                                          not active any more */
1497       __IM unsigned int RESERVED1 : 31;   /*!< [31..1] reserved1   */
1498     } IC_CLR_ACTIVITY_b;
1499   };
1500 
1501   union {
1502     __IM unsigned int IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt
1503                                       Register                          */
1504 
1505     struct {
1506       __IM unsigned int CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear
1507                                          the STOP_DET interrupt (bit 9) of the
1508                                          IC_RAW_INTR_STAT register. */
1509       __IM unsigned int RESERVED1 : 31;   /*!< [31..1] reserved1   */
1510     } IC_CLR_STOP_DET_b;
1511   };
1512 
1513   union {
1514     __IM unsigned int IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET
1515                                        Interrupt Register */
1516 
1517     struct {
1518       __IM unsigned int CLR_START_DET : 1; /*!< [0..0] Read this register to clear
1519                                           the START_DET interrupt (bit 10) of
1520                                           the IC_RAW_INTR_STAT register */
1521       __IM unsigned int RESERVED1 : 31;    /*!< [31..1] reserved1    */
1522     } IC_CLR_START_DET_b;
1523   };
1524 
1525   union {
1526     __IM unsigned int IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt
1527                                       Register                          */
1528 
1529     struct {
1530       __IM unsigned int CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear
1531                                          the GEN_CALL interrupt (bit 11) of
1532                                          IC_RAW_INTR_STAT register */
1533       __IM unsigned int RESERVED1 : 31;   /*!< [31..1] reserved1   */
1534     } IC_CLR_GEN_CALL_b;
1535   };
1536 
1537   union {
1538     __IOM unsigned int IC_ENABLE; /*!< (@ 0x0000006C) Clear GEN_CALL Interrupt Register */
1539 
1540     struct {
1541       __IOM unsigned int EN : 1;                        /*!< [0..0] Controls whether the DW_apb_i2c is enabled */
1542       __IOM unsigned int ABORT : 1;                     /*!< [1..1] When set, the controller initiates
1543                                    the transfer abort              */
1544       __IOM unsigned int TX_CMD_BLOCK : 1;              /*!< [2..2] none              */
1545       __IOM unsigned int SDA_STUCK_RECOVERY_ENABLE : 1; /*!< [3..3] SDA STUCK
1546                                                        RECOVERY ENABLE */
1547       __IM unsigned int RESERVED1 : 28;                 /*!< [31..4] reserved1                 */
1548     } IC_ENABLE_b;
1549   };
1550 
1551   union {
1552     __IM unsigned int IC_STATUS; /*!< (@ 0x00000070) I2C Status Register */
1553 
1554     struct {
1555       __IM unsigned int ACTIVITY : 1;                /*!< [0..0] I2C Activity Status */
1556       __IM unsigned int TFNF : 1;                    /*!< [1..1] Transmit FIFO Not Full     */
1557       __IM unsigned int TFE : 1;                     /*!< [2..2] Transmit FIFO Completely Empty      */
1558       __IM unsigned int RFNE : 1;                    /*!< [3..3] Receive FIFO Not Empty     */
1559       __IM unsigned int RFF : 1;                     /*!< [4..4] Receive FIFO Completely Full      */
1560       __IM unsigned int MST_ACTIVITY : 1;            /*!< [5..5] Master FSM Activity Status           */
1561       __IM unsigned int SLV_ACTIVITY : 1;            /*!< [6..6] Slave FSM Activity Status */
1562       __IM unsigned int MST_HOLD_TX_FIFO_EMPTY : 1;  /*!< [7..7] The I2C master stalls the
1563                                          write transfer when Tx FIFO is empty,
1564                                          and  the the last byte does not have
1565                                          the Stop bit set. */
1566       __IM unsigned int MST_HOLD_RX_FIFO_FULL : 1;   /*!< [8..8] This bit indicates the BUS Hold
1567                                         in Master mode due to Rx FIFO is Full
1568                                         and additional byte has been received.
1569                                       */
1570       __IM unsigned int SLV_HOLD_TX_FIFO_EMPTY : 1;  /*!< [9..9] This bit indicates the BUS
1571                                          Hold in Slave mode for the
1572                                           Read request when the  Tx FIFO is
1573                                          empty. */
1574       __IM unsigned int SLV_HOLD_RX_FIFO_FULL : 1;   /*!< [10..10] This bit indicates the BUS
1575                                         Hold in Slave mode due to the Rx FIFO
1576                                         being Full and  an additional byte being
1577                                         received.            */
1578       __IM unsigned int SDA_STUCK_NOT_RECOVERED : 1; /*!< [11..11] This bit indicates that an
1579                                           SDA stuck at low is not recovered
1580                                           after the  recovery mechanism. */
1581       __IM unsigned int RESERVED1 : 20;              /*!< [31..12] reserved1    */
1582     } IC_STATUS_b;
1583   };
1584 
1585   union {
1586     __IM unsigned int IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */
1587 
1588     struct {
1589       __IM unsigned int TXFLR : 4;      /*!< [3..0] Contains the number of valid data
1590                                   entries in the transmit FIFO. */
1591       __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */
1592     } IC_TXFLR_b;
1593   };
1594 
1595   union {
1596     __IM unsigned int IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */
1597 
1598     struct {
1599       __IM unsigned int RXFLR : 4;      /*!< [3..0] Receive FIFO Level. Contains the number of
1600                         valid data entries in the receive FIFO */
1601       __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */
1602     } IC_RXFLR_b;
1603   };
1604 
1605   union {
1606     __IOM unsigned int IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */
1607 
1608     struct {
1609       __IOM unsigned int IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in
1610                                   units of ic_clk period,when I2C  acts as a
1611                                   transmitter. */
1612       __IOM unsigned int IC_SDA_RX_HOLD : 8;  /*!< [23..16] Sets the required SDA hold time in
1613                                  units of ic_clk period,when  I2C acts as a
1614                                  receiver. */
1615       __IM unsigned int RESERVED1 : 8;        /*!< [31..24] reserved1 */
1616     } IC_SDA_HOLD_b;
1617   };
1618 
1619   union {
1620     __IM unsigned int IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort
1621                                         Source Register */
1622 
1623     struct {
1624       __IM unsigned int ABRT_7B_ADDR_NOACK : 1;        /*!< [0..0] 1: Master is in 7-bit addressing
1625                                      mode and the address sent was not
1626                                      acknowledged by any slave */
1627       __IM unsigned int ABRT_10ADDR1_NOACK : 1;        /*!< [1..1] 1: Master is in 10-bit
1628                                                address mode and the first 10-bit
1629                                                    address byte was not
1630                                                acknowledged by any slave */
1631       __IM unsigned int ABRT_10ADDR2_NOACK : 1;        /*!< [2..2] 1: Master is in 10-bit address
1632                                      mode and the second address byte of the
1633                                      10-bit address was not acknowledged by any
1634                                          slave */
1635       __IM unsigned int ABRT_TXDATA_NOACK : 1;         /*!< [3..3] 1: This is a master-mode only bit.
1636                                     Master has received an acknowledgement for
1637                                     the address, but when it sent data byte(s)
1638                                     following the address, it did not receive an
1639                                     acknowledge from the remote slave(s) */
1640       __IM unsigned int ABRT_GCALL_NOACK : 1;          /*!< [4..4] 1: DW_apb_i2c in master mode sent a
1641                                    General Call and no slave on the bus
1642                                    acknowledged the General Call */
1643       __IM unsigned int ABRT_GCALL_READ : 1;           /*!< [5..5] 1: DW_apb_i2c in master mode sent a
1644                                   General Call but the user programmed the byte
1645                                   following the  General Call
1646                                       to be a read from the bus (IC_DATA_CMD[9]
1647                                   is set to 1)                    */
1648       __IM unsigned int ABRT_HS_ACKDET : 1;            /*!< [6..6] 1: Master is in High Speed
1649                                            mode and the High Speed Master code
1650                                            was acknowledged */
1651       __IM unsigned int ABRT_SBYTE_ACKDET : 1;         /*!< [7..7] 1: Master has sent a START Byte and
1652                                     the START Byte was acknowledged (wrong
1653                                     behavior) */
1654       __IM unsigned int ABRT_HS_NORSTRT : 1;           /*!< [8..8] 1: The restart is disabled
1655                                   (IC_RESTART_EN bit (IC_CON[5]) = 0) and the
1656                                   user is trying to use the master to transfer
1657                                       data in High Speed mode */
1658       __IM unsigned int ABRT_SBYTE_NORSTRT : 1;        /*!< [9..9] 1: The restart is disabled
1659                                      (IC_RESTART_EN bit (IC_CON[5])
1660                                          = 0) and the user is trying to send a
1661                                      START Byte                          */
1662       __IM unsigned int ABRT_10B_RD_NORSTRT : 1;       /*!< [10..10] 1: The restart is disabled
1663                                       (IC_RESTART_EN bit (IC_CON[5]) = 0) and
1664                                       the master sends a read command in 10-bit
1665                                       addressing mode */
1666       __IM unsigned int ABRT_MASTER_DIS : 1;           /*!< [11..11] 1: User tries to initiate a Master
1667                                   operation with the Master mode disabled */
1668       __IM unsigned int ARB_LOST : 1;                  /*!< [12..12] 1: Master has lost arbitration, or if
1669                            IC_TX_ABRT_SOURCE[14] is also set, then the slave
1670                            transmitter has lost arbitration              */
1671       __IM unsigned int ABRT_SLVFLUSH_TXFIFO : 1;      /*!< [13..13] 1: Slave has received a
1672                                              read command and some data   exists in
1673                                              the TX FIFO so the slave issues a
1674                                              TX_ABRT interrupt   to flush old data
1675                                              in TX FIFO   */
1676       __IM unsigned int ABRT_SLV_ARBLOST : 1;          /*!< [14..14] 1: Slave lost the bus
1677                                              while transmitting data to a remote
1678                                              master. IC_TX_ABRT_SOURCE[12] is
1679                                              set at the same time */
1680       __IM unsigned int ABRT_SLVRD_INTX : 1;           /*!< [15..15] 1: When the processor side responds
1681                                   to a slave mode request for data to be
1682                                   transmitted to a remote master and
1683                                       user writes a 1 in CMD (bit 8) of
1684                                   IC_DATA_CMD register                    */
1685       __IM unsigned int ABRT_USER_ABRT : 1;            /*!< [16..16] This is a master-mode-only bit.
1686                                  Master has detected the transfer abort
1687                                  (IC_ENABLE[1]). */
1688       __IM unsigned int ABRT_SDA_STUCK_AT_LOW : 1;     /*!< [17..17] Master detects the
1689                                                   SDA is Stuck at low for the
1690                                                   IC_SDA_STUCK_AT_LOW_TI EOUT
1691                                                   value of ic_clks */
1692       __IM unsigned int ABRT_DEVICE_NOACK : 1;         /*!< [18..18] Master initiates the DEVICE_ID
1693                                    transfer and the device ID sent is not
1694                                    acknowledged by any slave */
1695       __IM unsigned int ABRT_DEVICE_SLVADDR_NOACK : 1; /*!< [19..19] Master is initiating the
1696                                            DEVICE_ID transfer and the slave
1697                                            address  sent was not acknowledged by
1698                                            any slave                     */
1699       __IM unsigned int ABRT_DEVICE_WRITE : 1;         /*!< [20..20] Master is initiating the
1700                                      DEVICE_ID transfer and the
1701                                      Tx- FIFO consists of write commands.   */
1702       __IM unsigned int RESERVED1 : 2;                 /*!< [22..21] reserved1 */
1703       __IM unsigned int TX_FLUSH_CNT : 9;              /*!< [31..23] This field indicates the number of Tx
1704                                FIFO data commands that are flushed due to
1705                                TX_ABRT interrupt */
1706     } IC_TX_ABRT_SOURCE_b;
1707   };
1708 
1709   union {
1710     __IOM unsigned int IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave
1711                                              Data NACK Register */
1712 
1713     struct {
1714       __IOM unsigned int NACK : 1;      /*!< [0..0] Generate NACK. This NACK generation only occurs
1715                        when DW_apb_i2c is a slave receiver. */
1716       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
1717     } IC_SLV_DATA_NACK_ONLY_b;
1718   };
1719 
1720   union {
1721     __IOM unsigned int IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register */
1722 
1723     struct {
1724       __IOM unsigned int RDMAE : 1;     /*!< [0..0] Receive DMA Enable */
1725       __IOM unsigned int TDMAE : 1;     /*!< [1..1] Transmit DMA Enable.This bit enables/disables
1726                         the transmit FIFO DMA channel */
1727       __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */
1728     } IC_DMA_CR_b;
1729   };
1730 
1731   union {
1732     __IOM unsigned int IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */
1733 
1734     struct {
1735       __IOM unsigned int DMATDL : 4;    /*!< [3..0] This bit field controls the level at which a
1736                          DMA request is made by the transmit logic */
1737       __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */
1738     } IC_DMA_TDLR_b;
1739   };
1740 
1741   union {
1742     __IOM unsigned int IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */
1743 
1744     struct {
1745       __IOM unsigned int DMARDL : 4;    /*!< [3..0] This bit field controls the level at which a
1746                          DMA request is made by the receive logic */
1747       __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */
1748     } IC_DMA_RDLR_b;
1749   };
1750 
1751   union {
1752     __IOM unsigned int IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register */
1753 
1754     struct {
1755       __IOM unsigned int SDA_SETUP : 8; /*!< [7..0] This register controls the amount of time
1756                             delay (in terms of number of ic_clk clock periods)
1757                           */
1758       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
1759     } IC_SDA_SETUP_b;
1760   };
1761 
1762   union {
1763     __IOM unsigned int IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call
1764                                            Register */
1765 
1766     struct {
1767       __IOM unsigned int ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call */
1768       __IM unsigned int RESERVED1 : 31;    /*!< [31..1] reserved1    */
1769     } IC_ACK_GENERAL_CALL_b;
1770   };
1771 
1772   union {
1773     __IM unsigned int IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register */
1774 
1775     struct {
1776       __IM unsigned int IC_EN : 1;                   /*!< [0..0] This bit always reflects the value
1777                                   driven on the output port ic_en. */
1778       __IM unsigned int SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] This bit indicates if a
1779                                           potential or active Slave operation
1780                                                        has been aborted due to
1781                                           the setting of the IC_ENABLE register
1782                                                        from 1 to 0 */
1783       __IM unsigned int SLV_RX_DATA_LOST : 1;        /*!< [2..2] Slave Received Data Lost     */
1784       __IM unsigned int RESERVED1 : 29;              /*!< [31..3] reserved1 */
1785     } IC_ENABLE_STATUS_b;
1786   };
1787 
1788   union {
1789     __IOM unsigned int IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS and FS Spike
1790                                     Suppression Limit Register             */
1791 
1792     struct {
1793       __IOM unsigned int IC_FS_SPKLEN : 8; /*!< [7..0] This register sets the
1794                                           duration, measured in ic_clk cycles,
1795                                                      of the longest spike in the
1796                                           SCL or SDA lines that are filtered
1797                                                      out by the spike
1798                                           suppression logic */
1799       __IM unsigned int RESERVED1 : 24;    /*!< [31..8] reserved1    */
1800     } IC_FS_SPKLEN_b;
1801   };
1802 
1803   union {
1804     __IOM unsigned int IC_HS_SPKLEN; /*!< (@ 0x000000A4) I2C HS Spike Suppression
1805                                     Limit Register                    */
1806 
1807     struct {
1808       __IOM unsigned int IC_HS_SPKLEN : 8; /*!< [7..0] This register sets the
1809                                           duration, measured in ic_clk cycles,
1810                                                      of the longest spike in the
1811                                           SCL or SDA lines that are filtered
1812                                                      out by the spike
1813                                           suppression logic */
1814       __IM unsigned int RESERVED1 : 24;    /*!< [31..8] reserved1    */
1815     } IC_HS_SPKLEN_b;
1816   };
1817 
1818   union {
1819     __IM unsigned int IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET
1820                                          Interrupt Register */
1821 
1822     struct {
1823       __IM unsigned int CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear
1824                                             the RESTART_DET interrupt (bit 12)
1825                                             of the IC_RAW_INTR_STAT registe */
1826       __IM unsigned int RESERVED1 : 31;      /*!< [31..1] reserved1      */
1827     } IC_CLR_RESTART_DET_b;
1828   };
1829 
1830   union {
1831     __IOM unsigned int IC_SCL_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000AC) I2C SCL
1832                                                    Stuck at Low Timeout */
1833 
1834     struct {
1835       __IOM unsigned int IC_SCL_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Generates the interrupt to
1836                                           indicate SCL stuck at low if it
1837                                           detects the SCL stuck at low for the
1838                                           IC_SCL_STUCK_LOW_TIMEOUT in units of
1839                                           ic_clk period */
1840     } IC_SCL_STUCK_AT_LOW_TIMEOUT_b;
1841   };
1842 
1843   union {
1844     __IOM unsigned int IC_SDA_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000B0) I2C SDA
1845                                                    Stuck at Low Timeout */
1846 
1847     struct {
1848       __IOM unsigned int IC_SDA_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Initiates the recovery of
1849                                           SDA line , if it detects the SDA stuck
1850                                           at low for the
1851                                           IC_SDA_STUCK_LOW_TIMEOUT in units of
1852                                           ic_clk period. */
1853     } IC_SDA_STUCK_AT_LOW_TIMEOUT_b;
1854   };
1855 
1856   union {
1857     __IM unsigned int IC_CLR_SCL_STUCK_DET; /*!< (@ 0x000000B4) Clear SCL Stuck at
1858                                            Low Detect Interrupt Register */
1859 
1860     struct {
1861       __IM unsigned int CLR_SCL_STUCK : 1; /*!< [0..0] Read this register to clear
1862                                           the SCL_STUCK_DET interrupt */
1863       __IM unsigned int RESERVED1 : 31;    /*!< [31..1] reserved1    */
1864     } IC_CLR_SCL_STUCK_DET_b;
1865   };
1866 
1867   union {
1868     __IM unsigned int IC_DEVICE_ID; /*!< (@ 0x000000B8) I2C Device ID */
1869 
1870     struct {
1871       __IM unsigned int DEVICE_ID : 24; /*!< [23..0] Contains the Device-ID of the component
1872                              assigned through the configuration parameter */
1873       __IM unsigned int RESERVED1 : 8;  /*!< [31..24] reserved1 */
1874     } IC_DEVICE_ID_b;
1875   };
1876 
1877   union {
1878     __IOM unsigned int IC_SMBUS_CLOCK_LOW_SEXT; /*!< (@ 0x000000BC) SMBUS Slave Clock Extend
1879                                     Timeout Register                  */
1880 
1881     struct {
1882       __IOM unsigned int SMBUS_CLK_LOW_SEXT_TIMEOUT : 32; /*!< [31..0] The values in this
1883                                               register are in units of ic_clk
1884                                               period.   */
1885     } IC_SMBUS_CLOCK_LOW_SEXT_b;
1886   };
1887 
1888   union {
1889     __IOM unsigned int IC_SMBUS_CLOCK_LOW_MEXT; /*!< (@ 0x000000C0) SMBUS Master extend clock
1890                                     Timeout Register                 */
1891 
1892     struct {
1893       __IOM unsigned int SMBUS_CLK_LOW_MEXT_TIMEOUT : 32; /*!< [31..0] The values in this
1894                                               register are in units of ic_clk
1895                                               period..  */
1896     } IC_SMBUS_CLOCK_LOW_MEXT_b;
1897   };
1898 
1899   union {
1900     __IOM unsigned int IC_SMBUS_THIGH_MAX_IDLE_COUNT; /*!< (@ 0x000000C4) SMBus Thigh MAX
1901                                           Bus-Idle count Register */
1902 
1903     struct {
1904       __IOM unsigned int SMBUS_THIGH_MAX_BUS_IDLE_CNT : 16; /*!< [15..0] The values in this
1905                                                 register are in units of ic_clk
1906                                                 period. */
1907       __IOM unsigned int RESERVED1 : 16;                    /*!< [31..16] Reserved1         */
1908     } IC_SMBUS_THIGH_MAX_IDLE_COUNT_b;
1909   };
1910 
1911   union {
1912     __IOM unsigned int IC_SMBUS_INTR_STAT; /*!< (@ 0x000000C8) SMBUS Interrupt
1913                                           Status Register */
1914 
1915     struct {
1916       __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1 */
1917     } IC_SMBUS_INTR_STAT_b;
1918   };
1919 
1920   union {
1921     __IOM unsigned int IC_SMBUS_INTR_MASK; /*!< (@ 0x000000CC) Interrupt Mask Register */
1922 
1923     struct {
1924       __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1 */
1925     } IC_SMBUS_INTR_MASK_b;
1926   };
1927 
1928   union {
1929     __IOM unsigned int IC_SMBUS_INTR_RAW_STATUS; /*!< (@ 0x000000D0) SMBUS Raw
1930                                                 Interrupt Status Register */
1931 
1932     struct {
1933       __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1. */
1934     } IC_SMBUS_INTR_RAW_STATUS_b;
1935   };
1936 
1937   union {
1938     __IOM unsigned int IC_CLR_SMBUS_INTR; /*!< (@ 0x000000D4) Clear SMBUS Interrupt
1939                                          Register                             */
1940 
1941     struct {
1942       __IOM unsigned int RESERVED1 : 32; /*!< [31..0] RESERVED1 */
1943     } IC_CLR_SMBUS_INTR_b;
1944   };
1945 
1946   union {
1947     __IOM unsigned int IC_OPTIONAL_SAR; /*!< (@ 0x000000D8) Optional Slave Address
1948                                        Register                            */
1949 
1950     struct {
1951       __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1. */
1952     } IC_OPTIONAL_SAR_b;
1953   };
1954 
1955   union {
1956     __IOM unsigned int IC_SMBUS_UDID_LSB; /*!< (@ 0x000000DC) SMBUS ARP UDID LSB Register */
1957 
1958     struct {
1959       __IOM unsigned int IC_SMBUS_ARP_UDID_LSB : 32; /*!< [31..0] This field is used to store
1960                                          the LSB 32 bit value of slave unique
1961                                          device identifier used in Address
1962                                          Resolution Protocol. */
1963     } IC_SMBUS_UDID_LSB_b;
1964   };
1965   __IM unsigned int RESERVED[5];
1966 
1967   union {
1968     __IM unsigned int IC_COMP_PARAM_1; /*!< (@ 0x000000F4) I2C HS Spike Suppression
1969                                       Limit Register                    */
1970 
1971     struct {
1972       __IM unsigned int CLR_RESTART_DET : 2;    /*!< [1..0] Read this register to clear the
1973                                   RESTART_DET interrupt (bit 12) of the
1974                                   IC_RAW_INTR_STAT register */
1975       __IM unsigned int MAX_SPEED_MODE : 2;     /*!< [3..2] Maximum Speed Mode */
1976       __IM unsigned int HC_COUNT_VALUES : 1;    /*!< [4..4] Hard Code the count values   */
1977       __IM unsigned int INTR_IO : 1;            /*!< [5..5] Single Interrupt Output port */
1978       __IM unsigned int HAS_DMA : 1;            /*!< [6..6] DMA Handshake Interface signal */
1979       __IM unsigned int ADD_ENCODED_PARAMS : 1; /*!< [7..7] Add Encoded Parameters */
1980       __IM unsigned int RX_BUFFER_DEPTH : 8;    /*!< [15..8] Depth of receive buffer;the buffer
1981                                   is 8 bits wide;2 to 256 */
1982       __IM unsigned int TX_BUFFER_DEPTH : 8;    /*!< [23..16] Depth of Transmit buffer;the buffer
1983                                   is 8 bits wide;2 to 256 */
1984       __IM unsigned int RESERVED1 : 8;          /*!< [31..24] reserved1 */
1985     } IC_COMP_PARAM_1_b;
1986   };
1987 
1988   union {
1989     __IM unsigned int IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */
1990 
1991     struct {
1992       __IM unsigned int IC_COMP_VERSION : 32; /*!< [31..0] Signifies the component
1993                                              version */
1994     } IC_COMP_VERSION_b;
1995   };
1996 
1997   union {
1998     __IM unsigned int IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */
1999 
2000     struct {
2001       __IM unsigned int IC_COMP_TYPE : 32; /*!< [31..0] Design ware Component Type
2002                                           number = 0x44_57_01_40 */
2003     } IC_COMP_TYPE_b;
2004   };
2005 } I2C0_Type; /*!< Size = 256 (0x100) */
2006 
2007 /* ===========================================================================================================================
2008  */
2009 /* ================                                           MCPWM
2010  * ================ */
2011 /* ===========================================================================================================================
2012  */
2013 
2014 /**
2015   * @brief The Motor Control PWM (MCPWM) controller is used to generate a
2016   periodic pulse waveform, which is useful in motor control and power control
2017   applications (MCPWM)
2018   */
2019 
2020 typedef struct { /*!< (@ 0x47070000) MCPWM Structure */
2021 
2022   union {
2023     __IM unsigned int PWM_INTR_STS; /*!< (@ 0x00000000) PWM Interrupt Status Register */
2024 
2025     struct {
2026       __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : 1; /*!< [0..0] This time base
2027                                                       interrupt for 0th channel
2028                                                       without considering
2029                                                        postscaler */
2030       __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH0 : 1;         /*!< [1..1] This time base interrupt
2031                                               for 0th channel, which considers
2032                                                        postscaler value */
2033       __IM unsigned int FLT_A_INTR : 1;                          /*!< [2..2] When the fault A pin is driven
2034                                        low, this interrupt is raised. */
2035       __IM unsigned int FLT_B_INTR : 1;                          /*!< [3..3] When the fault B pin is driven
2036                                        low, this interrupt is raised. */
2037       __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : 1; /*!< [4..4] This time base
2038                                                       interrupt for 1st channel
2039                                                       without considering
2040                                                        postscaler value */
2041       __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH1 : 1;         /*!< [5..5] This time base interrupt
2042                                               for 1st channel, which considers
2043                                                        postscaler value. */
2044       __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : 1; /*!< [6..6] This time base
2045                                                       interrupt for 2nd channel
2046                                                       without considering
2047                                                        postscaler value. */
2048       __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH2 : 1;         /*!< [7..7] This time base interrupt
2049                                               for 2nd channel, which considers
2050                                                        postscaler value */
2051       __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : 1; /*!< [8..8] This time base
2052                                                       interrupt for 3rd channel
2053                                                       without considering
2054                                                        postscaler value. */
2055       __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH3 : 1;         /*!< [9..9] This time base interrupt
2056                                               for 3rd channel, which considers
2057                                                        postscaler value. */
2058       __IM unsigned int RESERVED1 : 22;                          /*!< [31..10] reserved1        */
2059     } PWM_INTR_STS_b;
2060   };
2061 
2062   union {
2063     __IOM unsigned int PWM_INTR_UNMASK; /*!< (@ 0x00000004) PWM Interrupt Unmask Register */
2064 
2065     struct {
2066       __IOM unsigned int PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Unmask */
2067       __IOM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1       */
2068     } PWM_INTR_UNMASK_b;
2069   };
2070 
2071   union {
2072     __IOM unsigned int PWM_INTR_MASK; /*!< (@ 0x00000008) PWM Interrupt mask Register */
2073 
2074     struct {
2075       __IOM unsigned int PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Mask */
2076       __IOM unsigned int RESERVED1 : 16;       /*!< [31..16] reserved1       */
2077     } PWM_INTR_MASK_b;
2078   };
2079 
2080   union {
2081     __IOM unsigned int PWM_INTR_ACK; /*!< (@ 0x0000000C) PWM Interrupt
2082                                     Acknowledgement Register */
2083 
2084     struct {
2085       __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : 1; /*!< [0..0] pwm time
2086                                                                period match
2087                                                                interrupt for 0th
2088                                                                channel will be
2089                                                                cleared. */
2090       __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH0_ACK : 1;    /*!< [1..1] pwm time period match
2091                                                   interrupt for 0th channel will
2092                                                        be cleared */
2093       __OM unsigned int FLT_A_INTR_ACK : 1;                     /*!< [2..2] pwm fault A interrupt will
2094                                            be cleared. */
2095       __OM unsigned int FLT_B_INTR_ACK : 1;                     /*!< [3..3] pwm fault B interrupt will
2096                                            be cleared. */
2097       __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : 1; /*!< [4..4] pwm time
2098                                                                period match
2099                                                                interrupt for 1st
2100                                                                channel will be
2101                                                                cleared */
2102       __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH1_ACK : 1;    /*!< [5..5] pwm time period match
2103                                                   interrupt for 1st channel will
2104                                                        be cleared. */
2105       __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : 1; /*!< [6..6] pwm time
2106                                                                period match
2107                                                                interrupt for 2nd
2108                                                                channel will be
2109                                                                cleared. */
2110       __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH2_ACK : 1;    /*!< [7..7] pwm time period match
2111                                                   interrupt for 2nd channel will
2112                                                        be cleared. */
2113       __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : 1; /*!< [8..8] pwm time
2114                                                                period match
2115                                                                interrupt for 3rd
2116                                                                channel will be
2117                                                                cleared. */
2118       __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH3_ACK : 1;    /*!< [9..9] pwm time period match
2119                                                   interrupt for 3rd channel will
2120                                                        be cleared. */
2121       __IOM unsigned int RESERVED1 : 22;                        /*!< [31..10] reserved1           */
2122     } PWM_INTR_ACK_b;
2123   };
2124   __IM unsigned int RESERVED[6];
2125 
2126   union {
2127     __IOM unsigned int PWM_TIME_PRD_WR_REG_CH0; /*!< (@ 0x00000028) Base timer
2128                                                period register of channel 0 */
2129 
2130     struct {
2131       __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH0 : 16; /*!< [15..0] Value to update the
2132                                                  base timer period register of
2133                                                  channel
2134                                                        0 */
2135       __IOM unsigned int RESERVED1 : 16;                     /*!< [31..16] reserved1          */
2136     } PWM_TIME_PRD_WR_REG_CH0_b;
2137   };
2138 
2139   union {
2140     __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH0; /*!< (@ 0x0000002C) Base time
2141                                                     counter initial value
2142                                                     register for channel 0 */
2143 
2144     struct {
2145       __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH0 : 16; /*!< [15..0] To update the base
2146                                                 time counter initial value for
2147                                                 channel
2148                                                        0 */
2149       __IOM unsigned int RESERVED1 : 16;                    /*!< [31..16] reserved1         */
2150     } PWM_TIME_PRD_CNTR_WR_REG_CH0_b;
2151   };
2152 
2153   union {
2154     __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH0; /*!< (@ 0x00000030) Base time period config
2155                                        parameter's register for channel0 */
2156 
2157     struct {
2158       __IOM unsigned int TMR_OPEARATING_MODE_CH0 : 3;            /*!< [2..0] Base timer operating mode for
2159                                           channel0                            */
2160       __IOM unsigned int RESERVED1 : 1;                          /*!< [3..3] reserved1    */
2161       __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : 3;  /*!< [6..4] Base timer input
2162                                                     clock pre scale select value
2163                                                     for channel0. */
2164       __IOM unsigned int RESERVED2 : 1;                          /*!< [7..7] reserved2              */
2165       __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : 4; /*!< [11..8] Time base output
2166                                                      post scale bits for
2167                                                      channel0         */
2168       __IOM unsigned int RESERVED3 : 20;                         /*!< [31..12] reserved3              */
2169     } PWM_TIME_PRD_PARAM_REG_CH0_b;
2170   };
2171 
2172   union {
2173     __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH0; /*!< (@ 0x00000034) Base time counter initial
2174                                       value register for channel 0 */
2175 
2176     struct {
2177       __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter
2178                                                 soft reset */
2179       __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH0 : 1;  /*!< [1..1] Base timer enable for
2180                                                channnel0 */
2181       __IOM unsigned int PWM_SFT_RST : 1;                   /*!< [2..2] MC PWM soft reset       */
2182       __IM unsigned int RESERVED1 : 29;                     /*!< [31..3] reserved1         */
2183     } PWM_TIME_PRD_CTRL_REG_CH0_b;
2184   };
2185 
2186   union {
2187     __IM unsigned int PWM_TIME_PRD_STS_REG_CH0; /*!< (@ 0x00000038) Base time period
2188                                                status register for channel0 */
2189 
2190     struct {
2191       __IM unsigned int PWM_TIME_PRD_DIR_STS_CH0 : 1; /*!< [0..0] Time period counter
2192                                            direction status for channel0 */
2193       __IM unsigned int RESERVED1 : 31;               /*!< [31..1] reserved1     */
2194     } PWM_TIME_PRD_STS_REG_CH0_b;
2195   };
2196 
2197   union {
2198     __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH0; /*!< (@ 0x0000003C) Base Time
2199                                                   period counter current value
2200                                                   register for channel0 */
2201 
2202     struct {
2203       __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH0 : 16; /*!< [15..0] Time period counter
2204                                                current value for channel0 */
2205       __IM unsigned int RESERVED1 : 16;                   /*!< [31..16] reserved1         */
2206     } PWM_TIME_PRD_CNTR_VALUE_CH0_b;
2207   };
2208   __IM unsigned int RESERVED1[4];
2209 
2210   union {
2211     __IOM unsigned int PWM_DUTYCYCLE_CTRL_SET_REG; /*!< (@ 0x00000050) Duty cycle
2212                                                   Control Set Register */
2213 
2214     struct {
2215       __IOM unsigned int IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty
2216                                            cycle immediately */
2217       __IOM unsigned int DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle register updation
2218                                            disable. There is a separate
2219                                                        bit for each channel */
2220       __IM unsigned int RESERVED1 : 24;                /*!< [31..8] reserved1     */
2221     } PWM_DUTYCYCLE_CTRL_SET_REG_b;
2222   };
2223 
2224   union {
2225     __IOM unsigned int PWM_DUTYCYCLE_CTRL_RESET_REG; /*!< (@ 0x00000054) Duty cycle
2226                                                     Control Reset Register */
2227 
2228     struct {
2229       __IOM unsigned int IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty
2230                                            cycle immediately */
2231       __IOM unsigned int DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle
2232                                                       register updation disable.
2233                                                       There is a separate bit
2234                                                       for each channel. */
2235       __IM unsigned int RESERVED1 : 24;                /*!< [31..8] reserved1                */
2236     } PWM_DUTYCYCLE_CTRL_RESET_REG_b;
2237   };
2238 
2239   union {
2240     __IOM unsigned int PWM_DUTYCYCLE_REG_WR_VALUE[4]; /*!< (@ 0x00000058) Duty cycle Value
2241                                           Register for Channel0 to channel3 */
2242 
2243     struct {
2244       __IOM unsigned int PWM_DUTYCYCLE_REG_WR_VALUE_CH : 16; /*!< [15..0] Duty cycle value for
2245                                                  channel0 to channel3 */
2246       __IM unsigned int RESERVED1 : 16;                      /*!< [31..16] reserved1           */
2247     } PWM_DUTYCYCLE_REG_WR_VALUE_b[4];
2248   };
2249   __IM unsigned int RESERVED2[4];
2250 
2251   union {
2252     __IOM unsigned int PWM_DEADTIME_CTRL_SET_REG; /*!< (@ 0x00000078) Dead time
2253                                                  Control Set Register */
2254 
2255     struct {
2256       __IOM unsigned int DEADTIME_SELECT_ACTIVE : 4;   /*!< [3..0] Dead time select bits for PWM
2257                                          going active                         */
2258       __IOM unsigned int DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for
2259                                            PWM going inactive */
2260       __IOM unsigned int DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft
2261                                            reset for each channel. */
2262       __IM unsigned int RESERVED1 : 20;                /*!< [31..12] reserved1     */
2263     } PWM_DEADTIME_CTRL_SET_REG_b;
2264   };
2265 
2266   union {
2267     __IOM unsigned int PWM_DEADTIME_CTRL_RESET_REG; /*!< (@ 0x0000007C) Dead time
2268                                                    Control Reset Register */
2269 
2270     struct {
2271       __IOM unsigned int DEADTIME_SELECT_ACTIVE : 4;   /*!< [3..0] Dead time select bits for PWM
2272                                          going active                         */
2273       __IOM unsigned int DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for
2274                                            PWM going inactive */
2275       __IOM unsigned int DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft
2276                                            reset for each channel. */
2277       __IM unsigned int RESERVED1 : 20;                /*!< [31..12] reserved1     */
2278     } PWM_DEADTIME_CTRL_RESET_REG_b;
2279   };
2280 
2281   union {
2282     __IOM unsigned int PWM_DEADTIME_PRESCALE_SELECT_A; /*!< (@ 0x00000080) Dead time Prescale
2283                                            Select Register for A */
2284 
2285     struct {
2286       __IOM unsigned int DEADTIME_PRESCALE_SELECT_A : 8; /*!< [7..0] Dead time prescale
2287                                              selection bits for unit A. */
2288       __IM unsigned int RESERVED1 : 24;                  /*!< [31..8] reserved1       */
2289     } PWM_DEADTIME_PRESCALE_SELECT_A_b;
2290   };
2291 
2292   union {
2293     __IOM unsigned int PWM_DEADTIME_PRESCALE_SELECT_B; /*!< (@ 0x00000084) Dead time Prescale
2294                                            Select Register for B */
2295 
2296     struct {
2297       __IOM unsigned int DEADTIME_PRESCALE_SELECT_B : 8; /*!< [7..0] Dead time prescale
2298                                              selection bits for unit B */
2299       __IM unsigned int RESERVED1 : 24;                  /*!< [31..8] reserved1       */
2300     } PWM_DEADTIME_PRESCALE_SELECT_B_b;
2301   };
2302   __IOM MCPWM_PWM_DEADTIME_Type PWM_DEADTIME[4]; /*!< (@ 0x00000088) [0..3] */
2303   __IM unsigned int RESERVED3[8];
2304 
2305   union {
2306     __IOM unsigned int PWM_OP_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000C8) output override
2307                                          control set register */
2308 
2309     struct {
2310       __IOM unsigned int OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm
2311                                    time period depending on operating mode */
2312       __IM unsigned int RESERVED1 : 31;        /*!< [31..1] reserved1 */
2313     } PWM_OP_OVERRIDE_CTRL_SET_REG_b;
2314   };
2315 
2316   union {
2317     __IOM unsigned int PWM_OP_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000CC) output override
2318                                            control reset register */
2319 
2320     struct {
2321       __IOM unsigned int OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm
2322                                    time period depending on operating mode */
2323       __IOM unsigned int RESERVED1 : 31;       /*!< [31..1] reserved1 */
2324     } PWM_OP_OVERRIDE_CTRL_RESET_REG_b;
2325   };
2326 
2327   union {
2328     __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_SET_REG; /*!< (@ 0x000000D0) output override
2329                                            enable set register */
2330 
2331     struct {
2332       __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over
2333                                                         ride enable */
2334       __IOM unsigned int RESERVED1 : 24;                 /*!< [31..8] reserved1                 */
2335     } PWM_OP_OVERRIDE_ENABLE_SET_REG_b;
2336   };
2337 
2338   union {
2339     __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_RESET_REG; /*!< (@ 0x000000D4) output override
2340                                              enable reset register */
2341 
2342     struct {
2343       __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over
2344                                                         ride enable */
2345       __IOM unsigned int RESERVED1 : 24;                 /*!< [31..8] reserved1                 */
2346     } PWM_OP_OVERRIDE_ENABLE_RESET_REG_b;
2347   };
2348 
2349   union {
2350     __IOM unsigned int PWM_OP_OVERRIDE_VALUE_SET_REG; /*!< (@ 0x000000D8) output override value
2351                                           set register                        */
2352 
2353     struct {
2354       __IOM unsigned int OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value.     */
2355       __IOM unsigned int RESERVED1 : 24;        /*!< [31..8] reserved1 */
2356     } PWM_OP_OVERRIDE_VALUE_SET_REG_b;
2357   };
2358 
2359   union {
2360     __IOM unsigned int PWM_OP_OVERRIDE_VALUE_RESET_REG; /*!< (@ 0x000000DC) output override
2361                                             enable reset register */
2362 
2363     struct {
2364       __IOM unsigned int OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value.     */
2365       __IOM unsigned int RESERVED1 : 24;        /*!< [31..8] reserved1 */
2366     } PWM_OP_OVERRIDE_VALUE_RESET_REG_b;
2367   };
2368 
2369   union {
2370     __IOM unsigned int PWM_FLT_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000E0) fault override
2371                                           control set register */
2372 
2373     struct {
2374       __IOM unsigned int FLT_A_MODE : 1;         /*!< [0..0] Fault A mode    */
2375       __IOM unsigned int FLT_B_MODE : 1;         /*!< [1..1] Fault B mode    */
2376       __IOM unsigned int OP_POLARITY_H : 1;      /*!< [2..2] Ouput polarity for high (H3,
2377                                            H2, H1, H0) side signals */
2378       __IOM unsigned int OP_POLARITY_L : 1;      /*!< [3..3] Ouput polarity for low (L3,
2379                                            L2, L1, L0) side signals. */
2380       __IOM unsigned int FLT_A_ENABLE : 4;       /*!< [7..4] Fault A enable. Separate
2381                                            enable bit is present for channel  */
2382       __IOM unsigned int FLT_B_ENABLE : 4;       /*!< [11..8] Fault B enable. Separate
2383                                            enable bit is present for channel  */
2384       __IOM unsigned int COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode    */
2385       __IOM unsigned int RESERVED1 : 16;         /*!< [31..16] reserved1 */
2386     } PWM_FLT_OVERRIDE_CTRL_SET_REG_b;
2387   };
2388 
2389   union {
2390     __IOM unsigned int PWM_FLT_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000E4) fault override
2391                                             control reset register */
2392 
2393     struct {
2394       __IOM unsigned int FLT_A_MODE : 1;         /*!< [0..0] Fault B mode    */
2395       __IOM unsigned int FLT_B_MODE : 1;         /*!< [1..1] Fault B mode    */
2396       __IOM unsigned int OP_POLARITY_H : 1;      /*!< [2..2] Ouput polarity for high (H3,
2397                                            H2, H1, H0) side signals */
2398       __IOM unsigned int OP_POLARITY_L : 1;      /*!< [3..3] Ouput polarity for low (L3,
2399                                            L2, L1, L0) side signals. */
2400       __IOM unsigned int FLT_A_ENABLE : 4;       /*!< [7..4] Fault A enable. Separate
2401                                            enable bit is present for channel  */
2402       __IOM unsigned int FLT_B_ENABLE : 4;       /*!< [11..8] Fault B enable. Separate
2403                                            enable bit is present for channel  */
2404       __IOM unsigned int COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode    */
2405       __IOM unsigned int RESERVED1 : 16;         /*!< [31..16] reserved1 */
2406     } PWM_FLT_OVERRIDE_CTRL_RESET_REG_b;
2407   };
2408 
2409   union {
2410     __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_REG; /*!< (@ 0x000000E8) Fault input
2411                                                     A PWM override value */
2412 
2413     struct {
2414       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */
2415       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */
2416       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */
2417       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */
2418       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */
2419       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */
2420       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */
2421       __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */
2422       __IOM unsigned int RESERVED1 : 24;                  /*!< [31..8] reserved1       */
2423     } PWM_FLT_A_OVERRIDE_VALUE_REG_b;
2424   };
2425 
2426   union {
2427     __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_REG; /*!< (@ 0x000000EC) Fault input
2428                                                     B PWM override value */
2429 
2430     struct {
2431       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */
2432       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */
2433       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */
2434       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */
2435       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */
2436       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */
2437       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */
2438       __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */
2439       __IOM unsigned int RESERVED1 : 24;                  /*!< [31..8] reserved1       */
2440     } PWM_FLT_B_OVERRIDE_VALUE_REG_b;
2441   };
2442 
2443   union {
2444     __IOM unsigned int PWM_SVT_CTRL_SET_REG; /*!< (@ 0x000000F0) NONE */
2445 
2446     struct {
2447       __IOM unsigned int SVT_ENABLE_FRM : 1;    /*!< [0..0] Special event trigger enable. This is
2448                                  used to enable
2449                                           generation special event trigger */
2450       __IOM unsigned int SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger
2451                                                for time base direction */
2452       __IOM unsigned int RESERVED1 : 30;        /*!< [31..2] reserved1        */
2453     } PWM_SVT_CTRL_SET_REG_b;
2454   };
2455 
2456   union {
2457     __IOM unsigned int PWM_SVT_CTRL_RESET_REG; /*!< (@ 0x000000F4) Special event
2458                                               control reset register */
2459 
2460     struct {
2461       __IOM unsigned int SVT_ENABLE_FRM : 1;    /*!< [0..0] Special event trigger enable. This is
2462                                  used to enable
2463                                           generation special event trigger */
2464       __IOM unsigned int SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger
2465                                                for time base direction */
2466       __IOM unsigned int RESERVED1 : 30;        /*!< [31..2] reserved1        */
2467     } PWM_SVT_CTRL_RESET_REG_b;
2468   };
2469 
2470   union {
2471     __IOM unsigned int PWM_SVT_PARAM_REG; /*!< (@ 0x000000F8) Special event
2472                                          parameter register */
2473 
2474     struct {
2475       __IOM unsigned int SVT_POSTSCALER_SELECT : 4; /*!< [3..0] PWM special event trigger
2476                                         output postscale select bits */
2477       __IOM unsigned int RESERVED1 : 28;            /*!< [31..4] reserved1 */
2478     } PWM_SVT_PARAM_REG_b;
2479   };
2480 
2481   union {
2482     __IOM unsigned int PWM_SVT_COMPARE_VALUE_REG; /*!< (@ 0x000000FC) Special event
2483                                                  compare value register */
2484 
2485     struct {
2486       __IOM unsigned int PWM_SVT_COMPARE_VALUE : 16; /*!< [15..0] Special event compare value.
2487                                          This is used to compare with pwm time
2488                                          period counter to generate special
2489                                          event trigger */
2490       __IOM unsigned int RESERVED1 : 16;             /*!< [31..16] reserved1  */
2491     } PWM_SVT_COMPARE_VALUE_REG_b;
2492   };
2493 
2494   union {
2495     __IOM unsigned int PWM_TIME_PRD_WR_REG_CH1; /*!< (@ 0x00000100) Base timer
2496                                                period register of channel1 */
2497 
2498     struct {
2499       __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH1 : 16; /*!< [15..0] Value to update the
2500                                                  base timer period register of
2501                                                  channel
2502                                                        1 */
2503       __IOM unsigned int RESERVED1 : 16;                     /*!< [31..16] reserved1          */
2504     } PWM_TIME_PRD_WR_REG_CH1_b;
2505   };
2506 
2507   union {
2508     __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH1; /*!< (@ 0x00000104) Base time
2509                                                     counter initial value
2510                                                     register for channel1 */
2511 
2512     struct {
2513       __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH1 : 16; /*!< [15..0] To update the base
2514                                                 time counter initial value for
2515                                                 channel
2516                                                        1 */
2517       __IOM unsigned int RESERVED1 : 16;                    /*!< [31..16] reserved1         */
2518     } PWM_TIME_PRD_CNTR_WR_REG_CH1_b;
2519   };
2520 
2521   union {
2522     __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH1; /*!< (@ 0x00000108) NONE */
2523 
2524     struct {
2525       __IOM unsigned int TMR_OPEARATING_MODE_CH1 : 3;            /*!< [2..0] Base timer operating mode for
2526                                           channel1                            */
2527       __IOM unsigned int RESERVED1 : 1;                          /*!< [3..3] reserved1    */
2528       __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : 3;  /*!< [6..4] Base timer input
2529                                                     clock prescale select value
2530                                                     for channel1. */
2531       __IOM unsigned int RESERVED2 : 1;                          /*!< [7..7] reserved2              */
2532       __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : 4; /*!< [11..8] Time base output
2533                                                      post scale bits for
2534                                                      channel1         */
2535       __IOM unsigned int RESERVED3 : 20;                         /*!< [31..12] reserved3              */
2536     } PWM_TIME_PRD_PARAM_REG_CH1_b;
2537   };
2538 
2539   union {
2540     __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH1; /*!< (@ 0x0000010C) Base time period control
2541                                       register for channel1             */
2542 
2543     struct {
2544       __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter
2545                                                 soft reset */
2546       __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH1 : 1;  /*!< [1..1] Base timer enable for
2547                                                channnel1 */
2548       __IOM unsigned int PWM_SFT_RST : 1;                   /*!< [2..2] MC PWM soft reset       */
2549       __IOM unsigned int RESERVED1 : 29;                    /*!< [31..3] reserved1        */
2550     } PWM_TIME_PRD_CTRL_REG_CH1_b;
2551   };
2552 
2553   union {
2554     __IM unsigned int PWM_TIME_PRD_STS_REG_CH1; /*!< (@ 0x00000110) Base time period
2555                                                status register for channel1 */
2556 
2557     struct {
2558       __IM unsigned int PWM_TIME_PRD_DIR_STS_CH1 : 1; /*!< [0..0] Time period counter
2559                                            direction status for channel1. */
2560       __IM unsigned int RESERVED1 : 31;               /*!< [31..1] reserved1     */
2561     } PWM_TIME_PRD_STS_REG_CH1_b;
2562   };
2563 
2564   union {
2565     __IOM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH1; /*!< (@ 0x00000114) Time period counter
2566                                         current value for channel1 */
2567 
2568     struct {
2569       __IOM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH1 : 1; /*!< [0..0] Time period counter
2570                                               current value for channel1 */
2571       __IM unsigned int RESERVED1 : 31;                   /*!< [31..1] reserved1        */
2572     } PWM_TIME_PRD_CNTR_VALUE_CH1_b;
2573   };
2574 
2575   union {
2576     __IOM unsigned int PWM_TIME_PRD_WR_REG_CH2; /*!< (@ 0x00000118) Base timer
2577                                                period register of channel2 */
2578 
2579     struct {
2580       __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH2 : 16; /*!< [15..0] Value to update the
2581                                                  base timer period register of
2582                                                  channel
2583                                                        2 */
2584       __IOM unsigned int RESERVED1 : 16;                     /*!< [31..16] reserved1          */
2585     } PWM_TIME_PRD_WR_REG_CH2_b;
2586   };
2587 
2588   union {
2589     __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH2; /*!< (@ 0x0000011C) Base time
2590                                                     counter initial value
2591                                                     register for channel2 */
2592 
2593     struct {
2594       __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH2 : 16; /*!< [15..0] To update the base
2595                                                 time counter initial value for
2596                                                 channel
2597                                                        2 */
2598       __IOM unsigned int RESERVED1 : 16;                    /*!< [31..16] reserved1         */
2599     } PWM_TIME_PRD_CNTR_WR_REG_CH2_b;
2600   };
2601 
2602   union {
2603     __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH2; /*!< (@ 0x00000120) Base time period config
2604                                        parameter's register for channel2 */
2605 
2606     struct {
2607       __IOM unsigned int TMR_OPEARATING_MODE_CH2 : 3;            /*!< [2..0] Base timer operating mode for
2608                                           channel2                            */
2609       __IOM unsigned int RESERVED1 : 1;                          /*!< [3..3] reserved1    */
2610       __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : 3;  /*!< [6..4] Base timer input
2611                                                     clock pre scale select value
2612                                                     for channel2. */
2613       __IOM unsigned int RESERVED2 : 1;                          /*!< [7..7] reserved2              */
2614       __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : 4; /*!< [11..8] Time base output
2615                                                      post scale bits for
2616                                                      channel2         */
2617       __IOM unsigned int RESERVED3 : 20;                         /*!< [31..12] reserved3              */
2618     } PWM_TIME_PRD_PARAM_REG_CH2_b;
2619   };
2620 
2621   union {
2622     __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH2; /*!< (@ 0x00000124) Base time period control
2623                                       register for channel2             */
2624 
2625     struct {
2626       __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter
2627                                                 soft reset */
2628       __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH2 : 1;  /*!< [1..1] Base timer enable for
2629                                                channnel2 */
2630       __IOM unsigned int PWM_SFT_RST : 1;                   /*!< [2..2] MC PWM soft reset       */
2631       __IOM unsigned int RESERVED1 : 29;                    /*!< [31..3] reserved1        */
2632     } PWM_TIME_PRD_CTRL_REG_CH2_b;
2633   };
2634 
2635   union {
2636     __IM unsigned int PWM_TIME_PRD_STS_REG_CH2; /*!< (@ 0x00000128) Base time period
2637                                                status register for channel2 */
2638 
2639     struct {
2640       __IM unsigned int PWM_TIME_PRD_DIR_STS_CH2 : 1; /*!< [0..0] Time period counter
2641                                            direction status for channel2. */
2642       __IM unsigned int RESERVED1 : 31;               /*!< [31..1] reserved1     */
2643     } PWM_TIME_PRD_STS_REG_CH2_b;
2644   };
2645 
2646   union {
2647     __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH2; /*!< (@ 0x0000012C) Time period counter
2648                                         current value register for channel2 */
2649 
2650     struct {
2651       __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH2 : 1; /*!< [0..0] Time period counter
2652                                               current value for channel2 */
2653       __IM unsigned int RESERVED1 : 11;                  /*!< [11..1] reserved1        */
2654       __IM unsigned int RESERVED2 : 20;                  /*!< [31..12] reserved2        */
2655     } PWM_TIME_PRD_CNTR_VALUE_CH2_b;
2656   };
2657 
2658   union {
2659     __IOM unsigned int PWM_TIME_PRD_WR_REG_CH3; /*!< (@ 0x00000130) Base timer
2660                                                period register of channel3 */
2661 
2662     struct {
2663       __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH3 : 16; /*!< [15..0] To update the base
2664                                                  time counter initial value for
2665                                                  channel
2666                                                        3 */
2667       __IOM unsigned int RESERVED1 : 16;                     /*!< [31..16] reserved1          */
2668     } PWM_TIME_PRD_WR_REG_CH3_b;
2669   };
2670 
2671   union {
2672     __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH3; /*!< (@ 0x00000134) Base time
2673                                                     counter initial value
2674                                                     register for channel3 */
2675 
2676     struct {
2677       __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH3 : 16; /*!< [15..0] Value to update the
2678                                                 base timer period register of
2679                                                 channel
2680                                                        3 */
2681       __IOM unsigned int RESERVED1 : 16;                    /*!< [31..16] reserved1         */
2682     } PWM_TIME_PRD_CNTR_WR_REG_CH3_b;
2683   };
2684 
2685   union {
2686     __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH3; /*!< (@ 0x00000138) Base time period config
2687                                        parameter's register for channel3 */
2688 
2689     struct {
2690       __IOM unsigned int TMR_OPEARATING_MODE_CH3 : 3;            /*!< [2..0] Base timer operating mode for
2691                                           channel3                            */
2692       __IOM unsigned int RESERVED1 : 1;                          /*!< [3..3] reserved1    */
2693       __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : 3;  /*!< [6..4] Base timer input
2694                                                     clock pre scale select value
2695                                                     for channel2. */
2696       __IOM unsigned int RESERVED2 : 1;                          /*!< [7..7] reserved2              */
2697       __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : 4; /*!< [11..8] Time base output
2698                                                      post scale bits for
2699                                                      channel3         */
2700       __IOM unsigned int RESERVED3 : 20;                         /*!< [31..12] reserved3              */
2701     } PWM_TIME_PRD_PARAM_REG_CH3_b;
2702   };
2703 
2704   union {
2705     __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH3; /*!< (@ 0x0000013C) Base time period control
2706                                       register for channel3             */
2707 
2708     struct {
2709       __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter
2710                                                 soft reset */
2711       __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH3 : 1;  /*!< [1..1] Base timer enable for
2712                                                channnel3 */
2713       __IOM unsigned int PWM_SFT_RST : 1;                   /*!< [2..2] MC PWM soft reset       */
2714       __IOM unsigned int RESERVED1 : 29;                    /*!< [31..3] reserved1        */
2715     } PWM_TIME_PRD_CTRL_REG_CH3_b;
2716   };
2717 
2718   union {
2719     __IM unsigned int PWM_TIME_PRD_STS_REG_CH3; /*!< (@ 0x00000140) Base time period
2720                                                status register for channel3 */
2721 
2722     struct {
2723       __IM unsigned int PWM_TIME_PRD_DIR_STS_CH3 : 1; /*!< [0..0] Time period counter
2724                                            direction status for channel3. */
2725       __IM unsigned int RESERVED1 : 15;               /*!< [15..1] reserved1     */
2726       __IM unsigned int RESERVED2 : 16;               /*!< [31..16] reserved2     */
2727     } PWM_TIME_PRD_STS_REG_CH3_b;
2728   };
2729 
2730   union {
2731     __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH3; /*!< (@ 0x00000144) Time period counter
2732                                         current value register for channel3 */
2733 
2734     struct {
2735       __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH3 : 16; /*!< [15..0] Time period counter
2736                                                current value for channe3 */
2737       __IM unsigned int RESERVED1 : 16;                   /*!< [31..16] reserved1         */
2738     } PWM_TIME_PRD_CNTR_VALUE_CH3_b;
2739   };
2740 
2741   union {
2742     __IOM unsigned int PWM_TIME_PRD_COMMON_REG; /*!< (@ 0x00000148) Time period
2743                                                common register */
2744 
2745     struct {
2746       __IOM unsigned int PWM_TIME_PRD_USE_0TH_TIMER_ONLY : 1; /*!< [0..0] Instead of use four
2747                                                   base timers for four channels,
2748                                                   use only one base timer for
2749                                                   all channels. */
2750       __IOM unsigned int PWM_TIME_PRD_COMMON_TIMER_VALUE : 2; /*!< [2..1] Base timers select to
2751                                                   generate special event trigger
2752                                                 */
2753       __IOM unsigned int USE_EXT_TIMER_TRIG_FRM_REG : 1;      /*!< [3..3] Enable to use external
2754                                           trigger for base time counter
2755                                           increment or decrement. */
2756       __IOM unsigned int RESERVED1 : 28;                      /*!< [31..4] reserved1      */
2757     } PWM_TIME_PRD_COMMON_REG_b;
2758   };
2759 } MCPWM_Type; /*!< Size = 332 (0x14c) */
2760 
2761 /* ===========================================================================================================================
2762  */
2763 /* ================                                           UDMA0
2764  * ================ */
2765 /* ===========================================================================================================================
2766  */
2767 
2768 /**
2769  * @brief DMA Performs data transfers along with Addresses and control
2770  * information (UDMA0)
2771  */
2772 
2773 typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */
2774 
2775   union {
2776     __IM unsigned int DMA_STATUS; /*!< (@ 0x00000000) UDMA Status Register */
2777 
2778     struct {
2779       __IM unsigned int MASTER_ENABLE : 1; /*!< [0..0] Enable status of controller       */
2780       __IM unsigned int RESERVED1 : 3;     /*!< [3..1] Reserved1 */
2781       __IM unsigned int STATE : 4;         /*!< [7..4] Current state of the control state machine */
2782       __IM unsigned int RESERVED2 : 8;     /*!< [15..8] Reserved2    */
2783       __IM unsigned int CHNLS_MINUS1 : 5;  /*!< [20..16] Number of available DMA
2784                                          channels minus one */
2785       __IM unsigned int RESERVED3 : 7;     /*!< [27..21] Reserved3    */
2786       __IM unsigned int TEST_STATUS : 4;   /*!< [31..28] To reduce the gate count you
2787                                          can configure the controller        */
2788     } DMA_STATUS_b;
2789   };
2790 
2791   union {
2792     __OM unsigned int DMA_CFG; /*!< (@ 0x00000004) DMA Configuration */
2793 
2794     struct {
2795       __OM unsigned int MASTER_ENABLE : 1;  /*!< [0..0] Enable for the controller       */
2796       __OM unsigned int RESERVED1 : 4;      /*!< [4..1] Reserved1 */
2797       __OM unsigned int CHNL_PROT_CTRL : 3; /*!< [7..5] Sets the AHB-Lite protection by
2798                                        controlling the HPROT[3:1]]       signal levels as
2799                                        follows Bit[7]-Controls HPROT[3] to indicate       if
2800                                        cacheable access is occurring Bit[6]-Controls
2801                                        HPROT[2]       to indicate if cacheable access is
2802                                        occurring Bit[5]-Controls
2803                                                  HPROT[1] to indicate if cacheable
2804                                        access is occurring                     */
2805       __OM unsigned int RESERVED2 : 24;     /*!< [31..8] Reserved2 */
2806     } DMA_CFG_b;
2807   };
2808 
2809   union {
2810     __IOM unsigned int CTRL_BASE_PTR; /*!< (@ 0x00000008) Channel Control Data Base
2811                                      Pointer                          */
2812 
2813     struct {
2814       __OM unsigned int RESERVED1 : 10;      /*!< [9..0] Reserved1 */
2815       __IOM unsigned int CTRL_BASE_PTR : 22; /*!< [31..10] Pointer to the base address of the
2816                                  primary data structure        */
2817     } CTRL_BASE_PTR_b;
2818   };
2819 
2820   union {
2821     __IM unsigned int ALT_CTRL_BASE_PTR; /*!< (@ 0x0000000C) Channel Alternate
2822                                         Control Data Base Pointer */
2823 
2824     struct {
2825       __IM unsigned int ALT_CTRL_BASE_PTR : 32; /*!< [31..0] Base address of the
2826                                                alternative data structure */
2827     } ALT_CTRL_BASE_PTR_b;
2828   };
2829 
2830   union {
2831     __IM unsigned int DMA_WAITONREQUEST_STATUS; /*!< (@ 0x00000010) Channel Wait on
2832                                                request status register */
2833 
2834     struct {
2835       __IM unsigned int DMA_WAITONREQ_STATUS : 32; /*!< [31..0] Per Channel wait on
2836                                                   request status */
2837     } DMA_WAITONREQUEST_STATUS_b;
2838   };
2839 
2840   union {
2841     __OM unsigned int CHNL_SW_REQUEST; /*!< (@ 0x00000014) Channel Software Request */
2842 
2843     struct {
2844       __OM unsigned int CHNL_SW_REQUEST : 32; /*!< [31..0] Set the appropriate bit to generate
2845                                    a software DMA request on the corresponding
2846                                    DMA channel */
2847     } CHNL_SW_REQUEST_b;
2848   };
2849 
2850   union {
2851     __IOM unsigned int CHNL_USEBURST_SET; /*!< (@ 0x00000018) UDMA Channel use burst set */
2852 
2853     struct {
2854       __IOM unsigned int CHNL_USEBURST_SET : 32; /*!< [31..0] The use burst status,
2855                                                 or disables dma_sreq[C] from
2856                                                 generating DMA requests. */
2857     } CHNL_USEBURST_SET_b;
2858   };
2859 
2860   union {
2861     __OM unsigned int CHNL_USEBURST_CLR; /*!< (@ 0x0000001C) UDMA Channel use burst clear */
2862 
2863     struct {
2864       __OM unsigned int CHNL_USEBURST_CLR : 32; /*!< [31..0] Set the appropriate bit to enable
2865                                      dma_sreq[] to generate requests */
2866     } CHNL_USEBURST_CLR_b;
2867   };
2868 
2869   union {
2870     __IOM unsigned int CHNL_REQ_MASK_SET; /*!< (@ 0x00000020) UDMA Channel request
2871                                          mask set Register */
2872 
2873     struct {
2874       __IOM unsigned int CHNL_REQ_MASK_SET : 32; /*!< [31..0] Returns the request mask status
2875                                      of dma_req[] and dma_sreq[], or disables
2876                                      the corresponding channel from generating
2877                                      DMA requests */
2878     } CHNL_REQ_MASK_SET_b;
2879   };
2880 
2881   union {
2882     __OM unsigned int CHNL_REQ_MASK_CLR; /*!< (@ 0x00000024) UDMA Channel request
2883                                         mask clear                            */
2884 
2885     struct {
2886       __OM unsigned int CHNL_REQ_MASK_CLR : 32; /*!< [31..0] Set the appropriate bit
2887                                                to enable DMA requests for the
2888                                                      channel corresponding to
2889                                                dma_req[] and dma_sreq[] */
2890     } CHNL_REQ_MASK_CLR_b;
2891   };
2892 
2893   union {
2894     __IOM unsigned int CHNL_ENABLE_SET; /*!< (@ 0x00000028) UDMA Channel enable register */
2895 
2896     struct {
2897       __IOM unsigned int CHNL_ENABLE_SET : 32; /*!< [31..0] This Bits are Used to Load the
2898                                    16bits of Source address           */
2899     } CHNL_ENABLE_SET_b;
2900   };
2901 
2902   union {
2903     __OM unsigned int CHNL_ENABLE_CLR; /*!< (@ 0x0000002C) UDMA Channel enable clear
2904                                       register                         */
2905 
2906     struct {
2907       __OM unsigned int CHNL_ENABLE_CLR : 32; /*!< [31..0] Set the appropriate bit to disable
2908                                    the corresponding DMA channel */
2909     } CHNL_ENABLE_CLR_b;
2910   };
2911 
2912   union {
2913     __IOM unsigned int CHNL_PRI_ALT_SET; /*!< (@ 0x00000030) UDMA Channel primary or
2914                                         alternate set                      */
2915 
2916     struct {
2917       __IOM unsigned int CHNL_PRI_ALT_SET : 32; /*!< [31..0] Returns the channel control data
2918                                     structure status or selects the  alternate
2919                                     data structure for the corresponding DMA
2920                                     channel */
2921     } CHNL_PRI_ALT_SET_b;
2922   };
2923 
2924   union {
2925     __OM unsigned int CHNL_PRI_ALT_CLR; /*!< (@ 0x00000034) UDMA Channel primary
2926                                        alternate clear                       */
2927 
2928     struct {
2929       __OM unsigned int CHNL_PRI_ALT_CLR : 32; /*!< [31..0] Set the appropriate bit to select
2930                                     the primary data structure for the
2931                                     corresponding DMA channel */
2932     } CHNL_PRI_ALT_CLR_b;
2933   };
2934 
2935   union {
2936     __IOM unsigned int CHNL_PRIORITY_SET; /*!< (@ 0x00000038) UDMA Channel Priority Set */
2937 
2938     struct {
2939       __IOM unsigned int CHNL_PRIORITY_SET : 32; /*!< [31..0] Set the appropriate bit to select
2940                                      the primary data structure for  the
2941                                      corresponding DMA channel */
2942     } CHNL_PRIORITY_SET_b;
2943   };
2944 
2945   union {
2946     __OM unsigned int CHNL_PRIORITY_CLR; /*!< (@ 0x0000003C) UDMA Channel Priority Clear */
2947 
2948     struct {
2949       __OM unsigned int CHNL_PRIORITY_CLR : 32; /*!< [31..0] Set the appropriate bit to select
2950                                      the default priority level for the
2951                                      specified DMA channel */
2952     } CHNL_PRIORITY_CLR_b;
2953   };
2954   __IM unsigned int RESERVED[3];
2955 
2956   union {
2957     __IOM unsigned int ERR_CLR; /*!< (@ 0x0000004C) UDMA Bus Error Clear Register */
2958 
2959     struct {
2960       __IOM unsigned int ERR_CLR : 1;    /*!< [0..0] Returns the status of dma_err */
2961       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */
2962     } ERR_CLR_b;
2963   };
2964 
2965   union {
2966     __IOM unsigned int UDMA_SKIP_DESC_FETCH_REG; /*!< (@ 0x00000050) UDMA skip
2967                                                 descriptor fetch Register */
2968 
2969     struct {
2970       __IOM unsigned int SKIP_DESC_FETCH : 32; /*!< [31..0] improving the
2971                                               performance of transfer and saves
2972                                               bus cycles. This features has to
2973                                               be enabled always. */
2974     } UDMA_SKIP_DESC_FETCH_REG_b;
2975   };
2976   __IM unsigned int RESERVED1[491];
2977 
2978   union {
2979     __IOM unsigned int UDMA_DONE_STATUS_REG; /*!< (@ 0x00000800) UDMA Done status Register */
2980 
2981     struct {
2982       __IOM unsigned int DONE_STATUS_CHANNEL_0 : 1;  /*!< [0..0] UDMA done Status of
2983                                                     the channel 0  */
2984       __IOM unsigned int DONE_STATUS_CHANNEL_1 : 1;  /*!< [1..1] UDMA done Status of
2985                                                     the channel 1  */
2986       __IOM unsigned int DONE_STATUS_CHANNEL_2 : 1;  /*!< [2..2] UDMA done Status of
2987                                                     the channel 2  */
2988       __IOM unsigned int DONE_STATUS_CHANNEL_3 : 1;  /*!< [3..3] UDMA done Status of
2989                                                     the channel 3  */
2990       __IOM unsigned int DONE_STATUS_CHANNEL_4 : 1;  /*!< [4..4] UDMA done Status of
2991                                                     the channel 4  */
2992       __IOM unsigned int DONE_STATUS_CHANNEL_5 : 1;  /*!< [5..5] UDMA done Status of
2993                                                     the channel 5  */
2994       __IOM unsigned int DONE_STATUS_CHANNEL_6 : 1;  /*!< [6..6] UDMA done Status of
2995                                                     the channel 6  */
2996       __IOM unsigned int DONE_STATUS_CHANNEL_7 : 1;  /*!< [7..7] UDMA done Status of
2997                                                     the channel 7  */
2998       __IOM unsigned int DONE_STATUS_CHANNEL_8 : 1;  /*!< [8..8] UDMA done Status of
2999                                                     the channel 8  */
3000       __IOM unsigned int DONE_STATUS_CHANNEL_9 : 1;  /*!< [9..9] UDMA done Status of
3001                                                     the channel 9  */
3002       __IOM unsigned int DONE_STATUS_CHANNEL_10 : 1; /*!< [10..10] UDMA done Status
3003                                                     of the channel 10 */
3004       __IOM unsigned int DONE_STATUS_CHANNEL_11 : 1; /*!< [11..11] UDMA done Status
3005                                                     of the channel 3 */
3006       __IOM unsigned int DONE_STATUS_CHANNEL_12 : 1; /*!< [12..12] UDMA done Status
3007                                                     of the channel 12 */
3008       __IOM unsigned int DONE_STATUS_CHANNEL_13 : 1; /*!< [13..13] UDMA done Status
3009                                                     of the channel 13 */
3010       __IOM unsigned int DONE_STATUS_CHANNEL_14 : 1; /*!< [14..14] UDMA done Status
3011                                                     of the channel 14 */
3012       __IOM unsigned int DONE_STATUS_CHANNEL_15 : 1; /*!< [15..15] UDMA done Status
3013                                                     of the channel 15 */
3014       __IOM unsigned int DONE_STATUS_CHANNEL_16 : 1; /*!< [16..16] UDMA done Status
3015                                                     of the channel 16 */
3016       __IOM unsigned int DONE_STATUS_CHANNEL_17 : 1; /*!< [17..17] UDMA done Status
3017                                                     of the channel 17 */
3018       __IOM unsigned int DONE_STATUS_CHANNEL_18 : 1; /*!< [18..18] UDMA done Status
3019                                                     of the channel 18 */
3020       __IOM unsigned int DONE_STATUS_CHANNEL_19 : 1; /*!< [19..19] UDMA done Status
3021                                                     of the channel 19 */
3022       __IOM unsigned int DONE_STATUS_CHANNEL_20 : 1; /*!< [20..20] UDMA done Status
3023                                                     of the channel 3 */
3024       __IOM unsigned int DONE_STATUS_CHANNEL_21 : 1; /*!< [21..21] UDMA done Status
3025                                                     of the channel 21 */
3026       __IOM unsigned int DONE_STATUS_CHANNEL_22 : 1; /*!< [22..22] UDMA done Status
3027                                                     of the channel 22 */
3028       __IOM unsigned int DONE_STATUS_CHANNEL_23 : 1; /*!< [23..23] UDMA done Status
3029                                                     of the channel 23 */
3030       __IOM unsigned int DONE_STATUS_CHANNEL_24 : 1; /*!< [24..24] UDMA done Status
3031                                                     of the channel 24 */
3032       __IOM unsigned int DONE_STATUS_CHANNEL_25 : 1; /*!< [25..25] UDMA done Status
3033                                                     of the channel 25 */
3034       __IOM unsigned int DONE_STATUS_CHANNEL_26 : 1; /*!< [26..26] UDMA done Status
3035                                                     of the channel 26 */
3036       __IOM unsigned int DONE_STATUS_CHANNEL_27 : 1; /*!< [27..27] UDMA done Status
3037                                                     of the channel 27 */
3038       __IOM unsigned int DONE_STATUS_CHANNEL_28 : 1; /*!< [28..28] UDMA done Status
3039                                                     of the channel 28 */
3040       __IOM unsigned int DONE_STATUS_CHANNEL_29 : 1; /*!< [29..29] UDMA done Status
3041                                                     of the channel 29 */
3042       __IOM unsigned int DONE_STATUS_CHANNEL_30 : 1; /*!< [30..30] UDMA done Status
3043                                                     of the channel 30 */
3044       __IOM unsigned int DONE_STATUS_CHANNEL_31 : 1; /*!< [31..31] UDMA done Status
3045                                                     of the channel 31 */
3046     } UDMA_DONE_STATUS_REG_b;
3047   };
3048 
3049   union {
3050     __IM unsigned int CHANNEL_STATUS_REG; /*!< (@ 0x00000804) Channel status Register */
3051 
3052     struct {
3053       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_0 : 1;  /*!< [0..0] Reading 1 indicates
3054                                                  that the channel 0 is busy */
3055       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_1 : 1;  /*!< [1..1] Reading 1 indicates
3056                                                  that the channel 1 is busy */
3057       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_2 : 1;  /*!< [2..2] Reading 1 indicates
3058                                                  that the channel 2 is busy */
3059       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_3 : 1;  /*!< [3..3] Reading 1 indicates
3060                                                  that the channel 3 is busy */
3061       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_4 : 1;  /*!< [4..4] Reading 1 indicates
3062                                                  that the channel 4 is busy */
3063       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_5 : 1;  /*!< [5..5] Reading 1 indicates
3064                                                  that the channel 5 is busy */
3065       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_6 : 1;  /*!< [6..6] Reading 1 indicates
3066                                                  that the channel 6 is busy */
3067       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_7 : 1;  /*!< [7..7] Reading 1 indicates
3068                                                  that the channel 7 is busy */
3069       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_8 : 1;  /*!< [8..8] Reading 1 indicates
3070                                                  that the channel 8 is busy */
3071       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_9 : 1;  /*!< [9..9] Reading 1 indicates
3072                                                  that the channel 9 is busy */
3073       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_10 : 1; /*!< [10..10] Reading 1
3074                                                             indicates that the
3075                                                             channel 10 is busy
3076                                                           */
3077       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_11 : 1; /*!< [11..11] Reading 1
3078                                                             indicates that the
3079                                                             channel 11 is busy
3080                                                           */
3081       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_12 : 1; /*!< [12..12] Reading 1
3082                                                             indicates that the
3083                                                             channel 12 is busy
3084                                                           */
3085       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_13 : 1; /*!< [13..13] Reading 1
3086                                                             indicates that the
3087                                                             channel 13 is busy
3088                                                           */
3089       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_14 : 1; /*!< [14..14] Reading 1
3090                                                             indicates that the
3091                                                             channel 14 is busy
3092                                                           */
3093       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_15 : 1; /*!< [15..15] Reading 1
3094                                                             indicates that the
3095                                                             channel 15 is busy
3096                                                           */
3097       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_16 : 1; /*!< [16..16] Reading 1
3098                                                             indicates that the
3099                                                             channel 16 is busy
3100                                                           */
3101       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_17 : 1; /*!< [17..17] Reading 1
3102                                                             indicates that the
3103                                                             channel 17 is busy
3104                                                           */
3105       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_18 : 1; /*!< [18..18] Reading 1
3106                                                             indicates that the
3107                                                             channel 18 is busy
3108                                                           */
3109       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_19 : 1; /*!< [19..19] Reading 1
3110                                                             indicates that the
3111                                                             channel 19 is busy
3112                                                           */
3113       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_20 : 1; /*!< [20..20] Reading 1
3114                                                             indicates that the
3115                                                             channel 20 is busy
3116                                                           */
3117       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_21 : 1; /*!< [21..21] Reading 1
3118                                                             indicates that the
3119                                                             channel 21 is busy
3120                                                           */
3121       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_22 : 1; /*!< [22..22] Reading 1
3122                                                             indicates that the
3123                                                             channel 22 is busy
3124                                                           */
3125       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_23 : 1; /*!< [23..23] Reading 1
3126                                                             indicates that the
3127                                                             channel 23 is busy
3128                                                           */
3129       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_24 : 1; /*!< [24..24] Reading 1
3130                                                             indicates that the
3131                                                             channel 24 is busy
3132                                                           */
3133       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_25 : 1; /*!< [25..25] Reading 1
3134                                                             indicates that the
3135                                                             channel 25 is busy
3136                                                           */
3137       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_26 : 1; /*!< [26..26] Reading 1
3138                                                             indicates that the
3139                                                             channel 26 is busy
3140                                                           */
3141       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_27 : 1; /*!< [27..27] Reading 1
3142                                                             indicates that the
3143                                                             channel 27 is busy
3144                                                           */
3145       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_28 : 1; /*!< [28..28] Reading 1
3146                                                             indicates that the
3147                                                             channel 28 is busy
3148                                                           */
3149       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_29 : 1; /*!< [29..29] Reading 1
3150                                                             indicates that the
3151                                                             channel 29 is busy
3152                                                           */
3153       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_30 : 1; /*!< [30..30] Reading 1
3154                                                             indicates that the
3155                                                             channel 30 is busy
3156                                                           */
3157       __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_31 : 1; /*!< [31..31] Reading 1
3158                                                             indicates that the
3159                                                             channel 31 is busy
3160                                                           */
3161     } CHANNEL_STATUS_REG_b;
3162   };
3163   __IM unsigned int RESERVED2[8];
3164 
3165   union {
3166     __IOM unsigned int UDMA_CONFIG_CTRL_REG; /*!< (@ 0x00000828) DMA Controller
3167                                             Transfer Length Register */
3168 
3169     struct {
3170       __IOM unsigned int SINGLE_REQUEST_ENABLE : 1; /*!< [0..0] Enabled signal for
3171                                                    single request */
3172       __IOM unsigned int RESERVED1 : 31;            /*!< [31..1] Reserved for future use. */
3173     } UDMA_CONFIG_CTRL_REG_b;
3174   };
3175 
3176   union {
3177     __IOM unsigned int UDMA_INTR_MASK_REG; /*!< (@ 0x0000082C) Mask the uDMA
3178                                           interrupt register */
3179 
3180     struct {
3181       __IOM unsigned int UDMA_INTR_MASK : 12; /*!< [11..0] Mask the uDMA interrupt
3182                                              register */
3183       __IM unsigned int RESERVED1 : 20;       /*!< [31..12] RESERVED1       */
3184     } UDMA_INTR_MASK_REG_b;
3185   };
3186 } UDMA0_Type; /*!< Size = 2096 (0x830) */
3187 
3188 /* ===========================================================================================================================
3189  */
3190 /* ================                                          GPDMA_G
3191  * ================ */
3192 /* ===========================================================================================================================
3193  */
3194 
3195 /**
3196  * @brief GPDMA is an AMBA complaint peripheral unit supports 8-channels
3197  * (GPDMA_G)
3198  */
3199 
3200 typedef struct { /*!< (@ 0x21080000) GPDMA_G Structure */
3201   __IM unsigned int RESERVED[1057];
3202   __IOM GPDMA_G_GLOBAL_Type GLOBAL; /*!< (@ 0x00001084) GLOBAL */
3203 } GPDMA_G_Type;                     /*!< Size = 4252 (0x109c)                     */
3204 
3205 /* ===========================================================================================================================
3206  */
3207 /* ================                                          GPDMA_C
3208  * ================ */
3209 /* ===========================================================================================================================
3210  */
3211 
3212 /**
3213  * @brief GPDMAC (dma controller) is an AMBA complaint peripheral unit supports
3214  * 8-channels (GPDMA_C)
3215  */
3216 
3217 typedef struct {                                       /*!< (@ 0x21081004) GPDMA_C Structure */
3218   __IOM GPDMA_C_CHANNEL_CONFIG_Type CHANNEL_CONFIG[8]; /*!< (@ 0x00000000) [0..7] */
3219 } GPDMA_C_Type;                                        /*!< Size = 2048 (0x800)          */
3220 
3221 /* ===========================================================================================================================
3222  */
3223 /* ================                                           HWRNG
3224  * ================ */
3225 /* ===========================================================================================================================
3226  */
3227 
3228 /**
3229   * @brief Random numbers generated are 16-bit random numbers and are generated
3230   using either the True random number generator or the Pseudo random number
3231   generator. (HWRNG)
3232   */
3233 
3234 typedef struct { /*!< (@ 0x45090000) HWRNG Structure */
3235 
3236   union {
3237     __IOM unsigned int HWRNG_CTRL_REG; /*!< (@ 0x00000000) Random Number Generator
3238                                       Control Register                   */
3239 
3240     struct {
3241       __IOM unsigned int HWRNG_RNG_ST : 1;           /*!< [0..0] This bit is used to start the
3242                                           true number generation. */
3243       __IOM unsigned int HWRNG_PRBS_ST : 1;          /*!< [1..1] This bit is used to start the pseudo
3244                                 random number generation      */
3245       __IOM unsigned int SOFT_RESET : 1;             /*!< [2..2] This bit is used to start the
3246                                         pseudo random number generation      */
3247       __IOM unsigned int TAP_LFSR_INPUT : 1;         /*!< [3..3] This bit is used to Enable bit for
3248                                         Tapping LFSR input data which is coming from RING Oscillator      */
3249       __IM unsigned int LFSR_32_BIT_INPUT_VALID : 1; /*!< [4..4] This bit is used to
3250                                   Indicates when a valid 32 bit LFSR input data is latched
3251                                   After setting this bit, Firmware has to read LFSR_INPUT_LATCH_REG      */
3252       __IM unsigned int RESERVED1 : 27;              /*!< [31..5] RESERVED1  */
3253 
3254     } HWRNG_CTRL_REG_b;
3255   };
3256 
3257   union {
3258     __IM unsigned int HWRNG_RAND_NUM_REG; /*!< (@ 0x00000004) Hardware Random Number
3259                                          Register                            */
3260 
3261     struct {
3262       __IM unsigned int HWRNG_RAND_NUM : 32; /*!< [31..0] Generated random number
3263                                             can be read from this register. */
3264     } HWRNG_RAND_NUM_REG_b;
3265     struct {
3266       __IM unsigned int HWRNG_LFSR_INPUT_LATCH_REG : 32; /*!< [31..0] LFSR Input Latch Register. */
3267     } HWRNG_LFSR_INPUT_LATCH_REG_REG_b;
3268   };
3269 } HWRNG_Type; /*!< Size = 8 (0x8) */
3270 
3271 /* ===========================================================================================================================
3272  */
3273 /* ================                                          TIMERS
3274  * ================ */
3275 /* ===========================================================================================================================
3276  */
3277 
3278 /**
3279  * @brief TIMER can be used to generate various timing events for the software
3280  * (TIMERS)
3281  */
3282 
3283 typedef struct {                              /*!< (@ 0x24042000) TIMERS Structure */
3284   __IOM TIMERS_MATCH_CTRL_Type MATCH_CTRL[4]; /*!< (@ 0x00000000) [0..3] */
3285   __IM unsigned int RESERVED[24];
3286 
3287   union {
3288     __IOM unsigned int MCUULP_TMR_INTR_STAT; /*!< (@ 0x00000080) Timer Status Register */
3289 
3290     struct {
3291       __IOM unsigned int TMR0_INTR_STATUS : 1; /*!< [0..0] This bit indicates status of the
3292                                    interrupt generated by timer 0 */
3293       __IOM unsigned int TMR1_INTR_STATUS : 1; /*!< [1..1] This bit indicates status of the
3294                                    interrupt generated by timer 1 */
3295       __IOM unsigned int TMR2_INTR_STATUS : 1; /*!< [2..2] This bit indicates status of the
3296                                    interrupt generated by timer 2 */
3297       __IOM unsigned int TMR3_INTR_STATUS : 1; /*!< [3..3] This bit indicates status of the
3298                                        interrupt generated     by timer 3     */
3299       __IM unsigned int RESERVED1 : 28;        /*!< [31..4] reserved1 */
3300     } MCUULP_TMR_INTR_STAT_b;
3301   };
3302 
3303   union {
3304     __IOM unsigned int MCUULP_TMR_US_PERIOD_INT; /*!< (@ 0x00000084) Timer micro second period
3305                                      Integral Part Register           */
3306 
3307     struct {
3308       __IOM unsigned int TMR_US_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the
3309                                      integer part of number
3310                                           of clock cycles per microseconds of
3311                                      the system clock used                 */
3312       __IM unsigned int RESERVED1 : 16;          /*!< [31..16] reserved1 */
3313     } MCUULP_TMR_US_PERIOD_INT_b;
3314   };
3315 
3316   union {
3317     __IOM unsigned int MCUULP_TMR_US_PERIOD_FRAC; /*!< (@ 0x00000088) Timer microsecond period
3318                                       Fractional Part Register          */
3319 
3320     struct {
3321       __IOM unsigned int TMR_US_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the
3322                                      fractional part of number of clock cycles
3323                                      per microseconds of the system clock used
3324                                    */
3325       __IM unsigned int RESERVED1 : 24;          /*!< [31..8] reserved1 */
3326     } MCUULP_TMR_US_PERIOD_FRAC_b;
3327   };
3328 
3329   union {
3330     __IOM unsigned int MCUULP_TMR_MS_PERIOD_INT; /*!< (@ 0x0000008C) Timer 256 microsecond
3331                                      period Integral Part Register        */
3332 
3333     struct {
3334       __IOM unsigned int TMR_MS_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the
3335                                      integer part of number of clock cycles per
3336                                      256 microseconds of the system clock used
3337                                    */
3338       __IM unsigned int RESERVED1 : 16;          /*!< [31..16] reserved1 */
3339     } MCUULP_TMR_MS_PERIOD_INT_b;
3340   };
3341 
3342   union {
3343     __IOM unsigned int MCUULP_TMR_MS_PERIOD_FRAC; /*!< (@ 0x00000090) Timer 256 microsecond
3344                                       period Fractional Part Register */
3345 
3346     struct {
3347       __IOM unsigned int TMR_MS_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the
3348                                      fractional part of number of clock cycles
3349                                      per 256 microseconds of the system clock
3350                                      used */
3351       __IM unsigned int RESERVED1 : 24;          /*!< [31..8] reserved1 */
3352     } MCUULP_TMR_MS_PERIOD_FRAC_b;
3353   };
3354   __IM unsigned int RESERVED1[2];
3355 
3356   union {
3357     __IM unsigned int MCUULP_TMR_ACTIVE_STATUS; /*!< (@ 0x0000009C) Timer Active
3358                                                Status Register */
3359 
3360     struct {
3361       __IM unsigned int TIMER_ACTIVE : 4; /*!< [3..0] Timer active status for each
3362                                          timer. LSB bit specifies
3363                                                      the status for 0th timer
3364                                          and so on. */
3365       __IM unsigned int RESERVED1 : 28;   /*!< [31..4] reserved1   */
3366     } MCUULP_TMR_ACTIVE_STATUS_b;
3367   };
3368 } TIMERS_Type; /*!< Size = 160 (0xa0) */
3369 
3370 /* ===========================================================================================================================
3371  */
3372 /* ================                                            QEI
3373  * ================ */
3374 /* ===========================================================================================================================
3375  */
3376 
3377 /**
3378   * @brief The Quadrature Encoder Interface (QEI) module provides the interface
3379   to incremental encoders for obtaining mechanical position data (QEI)
3380   */
3381 
3382 typedef struct { /*!< (@ 0x47060000) QEI Structure */
3383 
3384   union {
3385     __IM unsigned int QEI_STATUS_REG; /*!< (@ 0x00000000) Quadrature Encoder status
3386                                      register                         */
3387 
3388     struct {
3389       __IM unsigned int QEI_INDEX : 1;               /*!< [0..0] This is a direct value from the
3390                                       position signal generator          */
3391       __IM unsigned int QEI_POSITION_B : 1;          /*!< [1..1] This is a direct value from the
3392                                  position signal generator.Value refers to the
3393                                  signal Position_B from the generator. */
3394       __IM unsigned int QEI_POSITION_A : 1;          /*!< [2..2] This is a direct value from the
3395                                  position signal generator.Value refers to the
3396                                  signal Position_A from the generator. */
3397       __IM unsigned int POSITION_CNTR_ERR : 1;       /*!< [3..3] Count Error Status Flag bit */
3398       __IM unsigned int POSITION_CNTR_DIRECTION : 1; /*!< [4..4] Position Counter
3399                                                     Direction Status bit */
3400       __IM unsigned int RESERVED1 : 27;              /*!< [31..5] Reserved1              */
3401     } QEI_STATUS_REG_b;
3402   };
3403 
3404   union {
3405     __IOM unsigned int QEI_CTRL_REG_SET; /*!< (@ 0x00000004) Quadrature Encoder
3406                                         control set register */
3407 
3408     struct {
3409       __IM unsigned int QEI_SFT_RST : 1;                /*!< [0..0] Quadrature encoder soft reset.
3410                                         It is self reset signal.            */
3411       __IOM unsigned int QEI_SWAP_PHASE_AB : 1;         /*!< [1..1] Phase A and Phase B
3412                                                Input Swap Select bit */
3413       __IOM unsigned int POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input
3414                                             Swap Select bit */
3415       __IOM unsigned int RESERVED1 : 1;                 /*!< [3..3] Reserved1      */
3416       __IOM unsigned int POS_CNT_DIRECTION_CTRL : 1;    /*!< [4..4] NONE */
3417       __IOM unsigned int POS_CNT_DIR_FRM_REG : 1;       /*!< [5..5] Position Counter Direction
3418                                        indication from user                    */
3419       __IOM unsigned int RESERVED2 : 1;                 /*!< [6..6] Reserved2 */
3420       __IOM unsigned int RESERVED3 : 1;                 /*!< [7..7] Reserved3 */
3421       __IOM unsigned int INDEX_CNT_RST_EN : 1;          /*!< [8..8] Index count reset enable */
3422       __IOM unsigned int DIGITAL_FILTER_BYPASS : 1;     /*!< [9..9] NONE */
3423       __IOM unsigned int TIMER_MODE : 1;                /*!< [10..10] NONE            */
3424       __IOM unsigned int START_VELOCITY_CNTR : 1;       /*!< [11..11] Starting the velocity counter.
3425                                       It is self reset bit.             */
3426       __IOM unsigned int QEI_STOP_IN_IDLE : 1;          /*!< [12..12] NONE */
3427       __IOM unsigned int QEI_POS_CNT_16_BIT_MODE : 1;   /*!< [13..13] Qei position counter 16 bit
3428                                           mode enable                         */
3429       __IOM unsigned int POS_CNT_RST : 1;               /*!< [14..14] 1=position counter is going
3430                                           to reset                             */
3431       __IOM unsigned int INDEX_CNT_RST : 1;             /*!< [15..15] 1= index counter is going
3432                                            to reset. */
3433       __IOM unsigned int RESERVED4 : 16;                /*!< [31..16] Reserved4    */
3434     } QEI_CTRL_REG_SET_b;
3435   };
3436 
3437   union {
3438     __IOM unsigned int QEI_CTRL_REG_RESET; /*!< (@ 0x00000008) Quadrature Encoder
3439                                           control reset register */
3440 
3441     struct {
3442       __IM unsigned int QEI_SFT_RST : 1;                /*!< [0..0] Quadrature encoder soft reset.
3443                                         It is self reset signal             */
3444       __IOM unsigned int QEI_SWAP_PHASE_AB : 1;         /*!< [1..1] Phase A and Phase B
3445                                                Input Swap Select bit */
3446       __IOM unsigned int POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input
3447                                             Swap Select bit */
3448       __IOM unsigned int RESERVED1 : 1;                 /*!< [3..3] Reserved1      */
3449       __IOM unsigned int POS_CNT_DIRECTION_CTRL : 1;    /*!< [4..4] NONE */
3450       __IOM unsigned int POS_CNT_DIR_FRM_REG : 1;       /*!< [5..5] Position Counter Direction
3451                                        indication from user                    */
3452       __IOM unsigned int RESERVED2 : 1;                 /*!< [6..6] Reserved2 */
3453       __IOM unsigned int RESERVED3 : 1;                 /*!< [7..7] Reserved3 */
3454       __IOM unsigned int INDEX_CNT_RST_EN : 1;          /*!< [8..8] NONE      */
3455       __IOM unsigned int DIGITAL_FILTER_BYPASS : 1;     /*!< [9..9] NONE */
3456       __IOM unsigned int TIMER_MODE : 1;                /*!< [10..10] NONE            */
3457       __IOM unsigned int START_VELOCITY_CNTR : 1;       /*!< [11..11] Starting the velocity counter.
3458                                       It is self reset bit.             */
3459       __IOM unsigned int QEI_STOP_IN_IDLE : 1;          /*!< [12..12] NONE */
3460       __IOM unsigned int QEI_POS_CNT_16_BIT_MODE : 1;   /*!< [13..13] Qei position counter 16 bit
3461                                           mode enable                         */
3462       __IOM unsigned int POS_CNT_RST : 1;               /*!< [14..14] 1=position counter is going
3463                                           to reset                             */
3464       __IOM unsigned int INDEX_CNT_RST : 1;             /*!< [15..15] 1= index counter is going
3465                                            to reset. */
3466       __IOM unsigned int RESERVED4 : 16;                /*!< [31..16] Reserved4    */
3467     } QEI_CTRL_REG_RESET_b;
3468   };
3469 
3470   union {
3471     __IOM unsigned int QEI_CNTLR_INIT_REG; /*!< (@ 0x0000000C) Quadrature Encoder
3472                                           initialization register */
3473 
3474     struct {
3475       __IOM unsigned int QEI_ENCODING_MODE : 2;       /*!< [1..0] NONE */
3476       __IOM unsigned int RESERVED1 : 2;               /*!< [3..2] Reserved1         */
3477       __IOM unsigned int INDEX_MATCH_VALUE : 2;       /*!< [5..4] These bits allow user to specify
3478                                     the state of position A and B during index
3479                                     pulse generation. */
3480       __IOM unsigned int DF_CLK_DIVIDE_SLT : 4;       /*!< [9..6] Digital Filter Clock
3481                                                Divide Select bits */
3482       __IOM unsigned int UNIDIRECTIONAL_VELOCITY : 1; /*!< [10..10] Uni directional
3483                                                      velocity enable. */
3484       __IOM unsigned int UNIDIRECTIONAL_INDEX : 1;    /*!< [11..11] Uni directional
3485                                                      index enable.    */
3486       __IOM unsigned int INDEX_CNT_INIT : 1;          /*!< [12..12] Index counter initial value in
3487                                  unidirectional index enable mode. */
3488       __IOM unsigned int RESERVED2 : 19;              /*!< [31..13] Reserved2 */
3489     } QEI_CNTLR_INIT_REG_b;
3490   };
3491 
3492   union {
3493     __IOM unsigned int QEI_INDEX_CNT_REG; /*!< (@ 0x00000010) Quadrature Encoder
3494                                          index counter register */
3495 
3496     struct {
3497       __IOM unsigned int QEI_INDEX_CNT : 16;          /*!< [15..0] Index counter value.User
3498                                             can initialize/change the index
3499                                             counter using this register */
3500       __IOM unsigned int QEI_INDEX_CNT_WR_VALUE : 16; /*!< [31..16] User can initialize/change
3501                                           the index counter using
3502                                           this register. */
3503     } QEI_INDEX_CNT_REG_b;
3504   };
3505 
3506   union {
3507     __IOM unsigned int QEI_INDEX_MAX_CNT_REG; /*!< (@ 0x00000014) Quadrature Encoder maximum
3508                                   index counter value register */
3509 
3510     struct {
3511       __IOM unsigned int QEI_INDEX_MAX_CNT : 16; /*!< [15..0] This is a maximum count value
3512                                         that is allowed to increment    in the index
3513                                         counter. If index counter reaches this
3514                                         value,    will get reset to zero    */
3515       __IOM unsigned int RESERVED1 : 16;         /*!< [31..16] Reserved1 */
3516     } QEI_INDEX_MAX_CNT_REG_b;
3517   };
3518 
3519   union {
3520     __IOM unsigned int QEI_POSITION_CNT_REG; /*!< (@ 0x00000018) Quadrature Encoder maximum
3521                                  position counter value register */
3522 
3523     struct {
3524       __IOM unsigned int QEI_POSITION_CNT_WR_VALUE_L : 16; /*!< [15..0] This is a maximum count
3525                                                value that is allowed to
3526                                                increment in the position
3527                                                counter. */
3528       __IOM unsigned int QEI_POSITION_CNT_WR_VALUE_H : 16; /*!< [31..16] This is a maximum
3529                                                count value that is allowed to
3530                                                increment in the position
3531                                                counter. */
3532     } QEI_POSITION_CNT_REG_b;
3533   };
3534   __IM unsigned int RESERVED;
3535 
3536   union {
3537     __IOM unsigned int QEI_POSITION_MAX_CNT_LSW_REG; /*!< (@ 0x00000020) Quadrature
3538                                                     Encoder maximum position
3539                                                     counter value register */
3540 
3541     struct {
3542       __IOM unsigned int QEI_POSITION_MAX_CNT_L : 16; /*!< [15..0] This is a maximum
3543                                                      count value that is allowed
3544                                                      to increment in the
3545                                                      position counter. */
3546       __IOM unsigned int QEI_POSITION_MAX_CNT_H : 16; /*!< [31..16] This is a maximum count
3547                                           value that is allowed to increment
3548                                                        in the position counter.
3549                                         */
3550     } QEI_POSITION_MAX_CNT_LSW_REG_b;
3551   };
3552   __IM unsigned int RESERVED1;
3553 
3554   union {
3555     __IM unsigned int QEI_INTR_STS_REG; /*!< (@ 0x00000028) Quadrature Encoder
3556                                        interrupt status register */
3557 
3558     struct {
3559       __IM unsigned int QEI_POSITION_CNT_RESET_INTR_LEV : 1;        /*!< [0..0] This is raised when
3560                                                   the position counter reaches
3561                                                   it's extremes */
3562       __IM unsigned int QEI_INDEX_CNT_MATCH_INTR_LEV : 1;           /*!< [1..1] This is raised when
3563                                                index counter reaches max value
3564                                                loaded in to index_max_cnt
3565                                                register. */
3566       __IM unsigned int POSITION_CNTR_ERR_INTR_LEV : 1;             /*!< [2..2] Whenever number of
3567                                            possible positions are mismatched
3568                                            with actual positions are received
3569                                            between two index pulses this will
3570                                            raised */
3571       __IM unsigned int VELOCITY_LESS_THAN_INTR_LEV : 1;            /*!< [3..3] When velocity count is
3572                                               less than the value given in
3573                                               velocity_value_to_c mpare
3574                                               register, interrupt is raised */
3575       __IM unsigned int QEI_POSITION_CNT_MATCH_INTR_LEV : 1;        /*!< [4..4] This is raised when
3576                                                   the position counter reaches
3577                                                   position
3578                                                        match value, which is
3579                                                   programmable. */
3580       __IM unsigned int QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] When velocity
3581                                                        count is computed for
3582                                                        given delta time, than
3583                                                        interrupt is raised. */
3584       __IM unsigned int RESERVED1 : 26;                             /*!< [31..6] Reserved1                   */
3585     } QEI_INTR_STS_REG_b;
3586   };
3587 
3588   union {
3589     __IOM unsigned int QEI_INTR_ACK_REG; /*!< (@ 0x0000002C) Quadrature Encoder
3590                                         interrupt acknowledge register */
3591 
3592     struct {
3593       __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_LEV : 1;    /*!< [0..0]
3594                                                              Qei_position_cnt_reset_intr_ack
3595                                                            */
3596       __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_LEV : 1;       /*!< [1..1] NONE    */
3597       __IOM unsigned int POSITION_CNTR_ERR_INTR_LEV : 1;         /*!< [2..2] Position_cntr_err_intr_ack
3598                                            */
3599       __IOM unsigned int VELOCITY_LESS_THAN_INTR_LEV : 1;        /*!< [3..3]
3600                                                                 Velocity_less_than_intr_ack                   */
3601       __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_LEV : 1;    /*!< [4..4]
3602                                                                 Qei_position_cnt_match_intr_ack
3603                                                               */
3604       __IOM unsigned int VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5]
3605                                                                 Velocity_computation_over_intr_ack
3606                                                               */
3607       __IOM unsigned int RESERVED1 : 26;                         /*!< [31..6] Reserved1 */
3608     } QEI_INTR_ACK_REG_b;
3609   };
3610 
3611   union {
3612     __IOM unsigned int QEI_INTR_MASK_REG; /*!< (@ 0x00000030) Quadrature Encoder
3613                                          interrupt mask register */
3614 
3615     struct {
3616       __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_MASK : 1;    /*!< [0..0]
3617                                                               Qei_position_cnt_reset_intr_mask
3618                                                             */
3619       __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_MASK : 1;       /*!< [1..1]
3620                                                               Qei_index_cnt_match_intr_mask
3621                                                             */
3622       __IOM unsigned int POSITION_CNTR_ERR_INTR_MASK : 1;         /*!< [2..2]
3623                                               Position_cntr_err_intr_mask */
3624       __IOM unsigned int VELOCITY_LESS_THAN_INTR_MASK : 1;        /*!< [3..3]
3625                                                                  Velocity_less_than_intr_mask                   */
3626       __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_MASK : 1;    /*!< [4..4]
3627                                                                  Qei_position_cnt_match_intr_mask
3628                                                                */
3629       __IOM unsigned int VELOCITY_COMPUTATION_OVER_INTR_MASK : 1; /*!< [5..5]
3630                                                                  Velocity_computation_over_intr_mask
3631                                                                */
3632       __IOM unsigned int RESERVED1 : 26;                          /*!< [31..6] Reserved1 */
3633     } QEI_INTR_MASK_REG_b;
3634   };
3635 
3636   union {
3637     __IOM unsigned int QEI_INTR_UNMASK_REg; /*!< (@ 0x00000034) Quadrature Encoder
3638                                            interrupt unmask register */
3639 
3640     struct {
3641       __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_UNMASK : 1; /*!< [0..0]
3642                                                                 Qei_position_cnt_reset_intr_unmask
3643                                                               */
3644       __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_UNMASK : 1;    /*!< [1..1]
3645                                                                 Qei_index_cnt_match_intr_unmask
3646                                                               */
3647       __IOM unsigned int POSITION_CNTR_ERR_INTR_UNMASK : 1;      /*!< [2..2]
3648                                                                 Position_cntr_err_intr_unmask
3649                                                               */
3650       __IOM unsigned int VELOCITY_LESS_THAN_INTR_UNMASK : 1;     /*!< [3..3]
3651                                                                 Velocity_less_than_intr_unmask
3652                                                               */
3653       __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_UNMASK : 1; /*!< [4..4]
3654                                                                 Qei_position_cnt_match_intr_unmask
3655                                                               */
3656       __IOM unsigned int RESERVED1 : 27;                         /*!< [31..5] Reserved1 */
3657     } QEI_INTR_UNMASK_REg_b;
3658   };
3659 
3660   union {
3661     __IOM unsigned int QEI_CLK_FREQ_REG; /*!< (@ 0x00000038) Quadrature Encoder
3662                                         clock frequency register */
3663 
3664     struct {
3665       __IOM unsigned int QEI_CLK_FREQ : 9; /*!< [8..0] Indication of clock frequency on which
3666                                QEI controller is running. */
3667       __IOM unsigned int RESERVED1 : 23;   /*!< [31..9] Reserved1 */
3668     } QEI_CLK_FREQ_REG_b;
3669   };
3670 
3671   union {
3672     __IOM unsigned int QEI_DELTA_TIME_REG; /*!< (@ 0x0000003C) Quadrature Delta time
3673                                           register */
3674 
3675     struct {
3676       __IOM unsigned int DELTA_TIME_FOR_VELOCITY : 20; /*!< [19..0] Delta time LSW
3677                                                       to compute velocity */
3678       __IOM unsigned int RESERVED1 : 12;               /*!< [31..20] Reserved1               */
3679     } QEI_DELTA_TIME_REG_b;
3680   };
3681   __IM unsigned int RESERVED2;
3682 
3683   union {
3684     __IOM unsigned int QEI_VELOCITY_REG; /*!< (@ 0x00000044) Quadrature velocity register */
3685 
3686     struct {
3687       __IOM unsigned int VELOCITY_VALUE_TO_COMPARE_L : 16; /*!< [15..0] For read operation :It
3688                                                is the velocity count to compare
3689                                                        using NWP firmware For
3690                                                write operation :It is the
3691                                                velocity value to compare with
3692                                                velocity count */
3693       __IOM unsigned int VELOCITY_VALUE_TO_COMPARE_H : 16; /*!< [31..16] For read operation :It
3694                                                is the velocity count to compare
3695                                                        using NWP firmware For
3696                                                write operation :It is the
3697                                                velocity value to compare with
3698                                                velocity count */
3699     } QEI_VELOCITY_REG_b;
3700   };
3701   __IM unsigned int RESERVED3;
3702 
3703   union {
3704     __IOM unsigned int QEI_POSITION_MATCH_REG; /*!< (@ 0x0000004C) Quadrature
3705                                               position match register */
3706 
3707     struct {
3708       __IOM unsigned int POSTION_MATCH_VALUE_L : 16; /*!< [15..0] Position match value to
3709                                          compare the position counter. */
3710       __IOM unsigned int POSTION_MATCH_VALUE_H : 16; /*!< [31..16] Position match value to
3711                                          compare the position counter. */
3712     } QEI_POSITION_MATCH_REG_b;
3713   };
3714 } QEI_Type; /*!< Size = 80 (0x50) */
3715 
3716 /* ===========================================================================================================================
3717  */
3718 /* ================                                          USART0
3719  * ================ */
3720 /* ===========================================================================================================================
3721  */
3722 
3723 /**
3724   * @brief Universal Asynchronous Receiver/Transmitter is for serial
3725   communication with peripherals, modems and datasets (USART0)
3726   */
3727 
3728 typedef struct { /*!< (@ 0x44000100) USART0 Structure */
3729 
3730   union {
3731     union {
3732       __IOM unsigned int DLL; /*!< (@ 0x00000000) Divisor Latch Low */
3733 
3734       struct {
3735         __IOM unsigned int DLL : 8;       /*!< [7..0] Lower 8-bits of a 16-bit, read/write, Divisor
3736                         Latch register that contains the baud rate divisor for
3737                         the UART.                         */
3738         __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3739       } DLL_b;
3740     };
3741 
3742     union {
3743       __OM unsigned int THR; /*!< (@ 0x00000000) Transmit Holding Register */
3744 
3745       struct {
3746         __OM unsigned int THR : 8;        /*!< [7..0] Data to be transmitted on serial
3747                                   output port                       */
3748         __OM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3749       } THR_b;
3750     };
3751 
3752     union {
3753       __IM unsigned int RBR; /*!< (@ 0x00000000) Receive Buffer Register */
3754 
3755       struct {
3756         __IM unsigned int RBR : 8;        /*!< [7..0] Receive Buffer Field        */
3757         __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3758       } RBR_b;
3759     };
3760   };
3761 
3762   union {
3763     union {
3764       __IOM unsigned int IER; /*!< (@ 0x00000004) Interrupt Enable Register */
3765 
3766       struct {
3767         __IOM unsigned int ERBFI : 1;     /*!< [0..0] Enable Received Data Available Interrupt */
3768         __IOM unsigned int ETBEI : 1;     /*!< [1..1] Enable Transmit Holding Register
3769                                      Empty Interrupt                   */
3770         __IOM unsigned int ELSI : 1;      /*!< [2..2] Enable Receiver Line Status Interrupt */
3771         __IOM unsigned int EDSSI : 1;     /*!< [3..3] Enable Modem Status Interrupt */
3772         __IM unsigned int RESERVED1 : 3;  /*!< [6..4] reserved1 */
3773         __IOM unsigned int PTIME : 1;     /*!< [7..7] Programmable THRE Interrupt Mode Enable */
3774         __IM unsigned int RESERVED2 : 24; /*!< [31..8] reserved2 */
3775       } IER_b;
3776     };
3777 
3778     union {
3779       __IOM unsigned int DLH; /*!< (@ 0x00000004) Divisor Latch High */
3780 
3781       struct {
3782         __IOM unsigned int DLH : 8;       /*!< [7..0] Upper 8-bits of a 16-bit, read/write, Divisor
3783                         Latch register that contains the baud rate divisor for
3784                         the UART                          */
3785         __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3786       } DLH_b;
3787     };
3788   };
3789 
3790   union {
3791     union {
3792       __OM unsigned int FCR; /*!< (@ 0x00000008) FIFO Control Register */
3793 
3794       struct {
3795         __OM unsigned int FIFOE : 1;      /*!< [0..0] This enables/disables the transmit
3796                                      (XMIT) and receive  (RCVR) FIFOs  */
3797         __OM unsigned int RFIFOR : 1;     /*!< [1..1] RCVR FIFO Reset */
3798         __OM unsigned int XFIFOR : 1;     /*!< [2..2] XMIT FIFO Reset */
3799         __OM unsigned int DMAM : 1;       /*!< [3..3] DMA signalling mode   */
3800         __OM unsigned int TET : 2;        /*!< [5..4] TX Empty Trigger    */
3801         __OM unsigned int RT : 2;         /*!< [7..6] This is used to select the trigger level in the
3802                        receiver FIFO at which the Received Data Available
3803                        Interrupt is generated */
3804         __OM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3805       } FCR_b;
3806     };
3807 
3808     union {
3809       __IM unsigned int IIR; /*!< (@ 0x00000008) Interrupt Identity Register */
3810 
3811       struct {
3812         __IM unsigned int IID : 4;        /*!< [3..0] Interrupt ID       */
3813         __IM unsigned int RESERVED1 : 2;  /*!< [5..4] reserved1 */
3814         __IM unsigned int FIFOSE : 2;     /*!< [7..6] This is used to indicate whether
3815                                      the FIFOs are enabled or disabled. */
3816         __IM unsigned int RESERVED2 : 24; /*!< [31..8] reserved2 */
3817       } IIR_b;
3818     };
3819   };
3820 
3821   union {
3822     __IOM unsigned int LCR; /*!< (@ 0x0000000C) Line Control Register */
3823 
3824     struct {
3825       __IOM unsigned int DLS : 2;          /*!< [1..0] Data Length Select,This is used to
3826                                   select the number  of data bits per character
3827                                   that the peripheral transmits  and receives  */
3828       __IOM unsigned int STOP : 1;         /*!< [2..2] This is used to select the number of
3829                                   stop bits per character that the peripheral
3830                                   transmits and receives */
3831       __IOM unsigned int PEN : 1;          /*!< [3..3] This bit is used to enable and disable parity
3832                       generation and detection in transmitted and received
3833                       serial character                */
3834       __IOM unsigned int EPS : 1;          /*!< [4..4] This is used to select between even
3835                                  and odd parity                 */
3836       __IOM unsigned int STICK_PARITY : 1; /*!< [5..5] This bit is used to force
3837                                           parity value */
3838       __IOM unsigned int BC : 1;           /*!< [6..6] This is used to cause a break condition
3839                                 to be transmitted to the receiving device */
3840       __IOM unsigned int DLAB : 1;         /*!< [7..7] This bit is used to enable reading
3841                                   and writing of the Divisor Latch register to
3842                                   set the baud rate of the UART */
3843       __IOM unsigned int RESERVED1 : 24;   /*!< [31..8] reserved1 */
3844     } LCR_b;
3845   };
3846 
3847   union {
3848     __IOM unsigned int MCR; /*!< (@ 0x00000010) Modem Control Register */
3849 
3850     struct {
3851       __IOM unsigned int DTR : 1;       /*!< [0..0] This is used to directly control the
3852                                   Data Terminal Ready  (dtr_n) output  */
3853       __IOM unsigned int RTS : 1;       /*!< [1..1] This is used to directly control the
3854                                   Request to Send  (rts_n) output  */
3855       __IOM unsigned int OUT1 : 1;      /*!< [2..2] This is used to directly control the
3856                                   user-designated Output1 (out1_n) output */
3857       __IOM unsigned int OUT2 : 1;      /*!< [3..3] This is used to directly control the
3858                                   user-designated Output2 (out2_n) output */
3859       __IOM unsigned int LB : 1;        /*!< [4..4] This is used to put the UART into a
3860                                   diagnostic mode for   test purposes   */
3861       __IOM unsigned int AFCE : 1;      /*!< [5..5] This is used to directly control the
3862                                   user-designated Output2 (out2_n) output */
3863       __IOM unsigned int SIRE : 1;      /*!< [6..6] This is used to enable/disable the
3864                                   IrDA SIR Mode features          */
3865       __IM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */
3866     } MCR_b;
3867   };
3868 
3869   union {
3870     __IM unsigned int LSR; /*!< (@ 0x00000014) Line Status Register */
3871 
3872     struct {
3873       __IM unsigned int DR : 1;         /*!< [0..0] This is used to indicate that the
3874                                receiver contains at least one character in the
3875                                RBR or the receiver FIFO                       */
3876       __IM unsigned int OE : 1;         /*!< [1..1] This is used to indicate the occurrence
3877                                of an overrun error */
3878       __IM unsigned int PE : 1;         /*!< [2..2] This is used to indicate the occurrence
3879                                of a parity error in the receiver  if the Parity
3880                                Enable (PEN) bit (LCR[3]) is set */
3881       __IM unsigned int FE : 1;         /*!< [3..3] This is used to indicate the occurrence
3882                                of a framing error in the receiver */
3883       __IM unsigned int BI : 1;         /*!< [4..4] his is used to indicate the detection of
3884                                a break sequence on the serial input data */
3885       __IM unsigned int THRE : 1;       /*!< [5..5] Transmit Holding Register Empty bit           */
3886       __IM unsigned int TEMT : 1;       /*!< [6..6] Transmitter Empty bit */
3887       __IM unsigned int RFE : 1;        /*!< [7..7] This is used to indicate if there is at
3888                                 least one parity error,framing error, or break
3889                                 indication in the FIFO                      */
3890       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3891     } LSR_b;
3892   };
3893 
3894   union {
3895     __IM unsigned int MSR; /*!< (@ 0x00000018) Modem Status Register */
3896 
3897     struct {
3898       __IM unsigned int DCTS : 1;       /*!< [0..0] This is used to indicate that the modem control
3899                        line cts_n has changed since the last time the MSR was
3900                        read                    */
3901       __IM unsigned int DDSR : 1;       /*!< [1..1] This is used to indicate that the modem control
3902                        line dsr_n has changed since the last time the MSR was
3903                        read                    */
3904       __IM unsigned int TERI : 1;       /*!< [2..2] This is used to indicate that a change on the
3905                        input ri_n(from an active-low to an inactive-high state)
3906                        has occurred since the last time the MSR was read */
3907       __IM unsigned int DDCD : 1;       /*!< [3..3] This is used to indicate that the modem control
3908                        line dcd_n has  changed since the last time the MSR was
3909                        read                   */
3910       __IM unsigned int CTS : 1;        /*!< [4..4] This is used to indicate the current
3911                                 state of the modem control line cts_n */
3912       __IM unsigned int DSR : 1;        /*!< [5..5] This is used to indicate the current
3913                                 state of the modem control line dsr_n */
3914       __IM unsigned int RI : 1;         /*!< [6..6] This is used to indicate the current
3915                                 state of the modem  control line ri_n  */
3916       __IM unsigned int DCD : 1;        /*!< [7..7] This is used to indicate the current
3917                                 state of the modem control line dcd_n */
3918       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
3919     } MSR_b;
3920   };
3921 
3922   union {
3923     __IOM unsigned int SCR; /*!< (@ 0x0000001C) Scratch pad Register */
3924 
3925     struct {
3926       __IOM unsigned int SCRATCH_PAD : 8; /*!< [7..0] This register is for programmers to use
3927                               as a temporary storage space. It has no defined
3928                               purpose                                  */
3929       __IM unsigned int RESERVED1 : 24;   /*!< [31..8] reserved1 */
3930     } SCR_b;
3931   };
3932 
3933   union {
3934     __IOM unsigned int LPDLL; /*!< (@ 0x00000020) Low Power Divisor Latch Low Register */
3935 
3936     struct {
3937       __IOM unsigned int LOW_POWER_DLL : 8; /*!< [7..0] This register makes up the lower 8-bits
3938                                 of a 16-bit, read/write, Low Power Divisor Latch
3939                                 register that contains the baud rate divisor for
3940                                 the UART, which must give a baud
3941                                           rate of 115.2K */
3942       __IOM unsigned int RESERVED1 : 24;    /*!< [31..8] reserved1 */
3943     } LPDLL_b;
3944   };
3945 
3946   union {
3947     __IOM unsigned int LPDLH; /*!< (@ 0x00000024) Low Power Divisor Latch High Register */
3948 
3949     struct {
3950       __IOM unsigned int LOW_POWER_DLH : 8; /*!< [7..0] This register makes up the upper 8-bits
3951                                 of a 16-bit, read/write, Low Power Divisor Latch
3952                                 register that contains the baud rate divisor for
3953                                 the UART, which must give a baud
3954                                           rate of 115200 */
3955       __IOM unsigned int RESERVED1 : 24;    /*!< [31..8] reserved1 */
3956     } LPDLH_b;
3957   };
3958   __IM unsigned int RESERVED[6];
3959 
3960   union {
3961     __IOM unsigned int HDEN; /*!< (@ 0x00000040) none */
3962 
3963     struct {
3964       __IOM unsigned int FULL_DUPLEX_MODE : 1; /*!< [0..0] none */
3965       __IOM unsigned int TX_MODE_RX_MODE : 1;  /*!< [1..1] This signal is valid when
3966                                               full_duplex_mode is disabled  */
3967       __IM unsigned int RESERVED1 : 30;        /*!< [31..2] reserved1        */
3968     } HDEN_b;
3969   };
3970   __IM unsigned int RESERVED1[5];
3971 
3972   union {
3973     __IOM unsigned int SMCR; /*!< (@ 0x00000058) none */
3974 
3975     struct {
3976       __IOM unsigned int SYNC_MODE : 1;      /*!< [0..0] none      */
3977       __IOM unsigned int MST_MODE : 1;       /*!< [1..1] none       */
3978       __IOM unsigned int RESERVED1 : 2;      /*!< [3..2] reserved1      */
3979       __IOM unsigned int CONTI_CLK_MODE : 1; /*!< [4..4] none */
3980       __IOM unsigned int START_STOP_EN : 1;  /*!< [5..5] none  */
3981       __IOM unsigned int RESERVED2 : 26;     /*!< [31..6] reserved2     */
3982     } SMCR_b;
3983   };
3984   __IM unsigned int RESERVED2[5];
3985 
3986   union {
3987     __IOM unsigned int FAR; /*!< (@ 0x00000070) none */
3988 
3989     struct {
3990       __IOM unsigned int SYNC_MODE : 1; /*!< [0..0] none */
3991       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
3992     } FAR_b;
3993   };
3994 
3995   union {
3996     __IM unsigned int TFR; /*!< (@ 0x00000074) none */
3997 
3998     struct {
3999       __IM unsigned int TX_FIFO_RD : 8; /*!< [7..0] Transmit FIFO Read */
4000       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
4001     } TFR_b;
4002   };
4003 
4004   union {
4005     __IOM unsigned int RFW; /*!< (@ 0x00000078) none */
4006 
4007     struct {
4008       __IOM unsigned int RFWD : 8;      /*!< [7..0] Receive FIFO Write Data      */
4009       __IOM unsigned int RFPE : 1;      /*!< [8..8] Receive FIFO Parity Error      */
4010       __IOM unsigned int RFFE : 1;      /*!< [9..9] Receive FIFO Framing Error      */
4011       __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */
4012     } RFW_b;
4013   };
4014 
4015   union {
4016     __IM unsigned int USR; /*!< (@ 0x0000007C) UART Status Register */
4017 
4018     struct {
4019       __IM unsigned int BUSY : 1;       /*!< [0..0] Indicates that a serial transfer is in
4020                                  progress                    */
4021       __IM unsigned int TFNF : 1;       /*!< [1..1] To Indicate that the transmit FIFO is
4022                                  not full                     */
4023       __IM unsigned int TFE : 1;        /*!< [2..2] To Indicate that the transmit FIFO is
4024                                  completely empty             */
4025       __IM unsigned int RFNE : 1;       /*!< [3..3] To Indicate that the receive FIFO
4026                                  contains one or more entries */
4027       __IM unsigned int RFE : 1;        /*!< [4..4] To Indicate that the receive FIFO is
4028                                  completely full               */
4029       __IM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */
4030     } USR_b;
4031   };
4032 
4033   union {
4034     __IM unsigned int TFL; /*!< (@ 0x00000080) Transmit FIFO Level */
4035 
4036     struct {
4037       __IM unsigned int FIFO_ADDR_WIDTH : 30; /*!< [29..0] Transmit FIFO Level. This
4038                                              is indicates the number of data
4039                                              entries in the transmit FIFO. */
4040       __IM unsigned int RESERVED1 : 2;        /*!< [31..30] reserved1        */
4041     } TFL_b;
4042   };
4043 
4044   union {
4045     __IM unsigned int RFL; /*!< (@ 0x00000084) Receive FIFO Level */
4046 
4047     struct {
4048       __IM unsigned int FIFO_ADDR_WIDTH : 30; /*!< [29..0] Receive FIFO Level. This
4049                                              is indicates the number of data
4050                                              entries in the receive FIFO. */
4051       __IM unsigned int RESERVED1 : 2;        /*!< [31..30] reserved1        */
4052     } RFL_b;
4053   };
4054 
4055   union {
4056     __OM unsigned int SRR; /*!< (@ 0x00000088) Software Reset Register */
4057 
4058     struct {
4059       __OM unsigned int UR : 1;         /*!< [0..0] UART Reset         */
4060       __OM unsigned int RFR : 1;        /*!< [1..1] RCVR FIFO Reset        */
4061       __OM unsigned int XFR : 1;        /*!< [2..2] XMIT FIFO Reset        */
4062       __OM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */
4063     } SRR_b;
4064   };
4065 
4066   union {
4067     __IOM unsigned int SRTS; /*!< (@ 0x0000008C) Shadow Request to Send */
4068 
4069     struct {
4070       __IOM unsigned int SRTS : 1;      /*!< [0..0] Shadow Request to Send.      */
4071       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4072     } SRTS_b;
4073   };
4074 
4075   union {
4076     __IOM unsigned int SBCR; /*!< (@ 0x00000090) Shadow Break Control Register */
4077 
4078     struct {
4079       __IOM unsigned int SBCR : 1;      /*!< [0..0] Shadow Break Control Bit      */
4080       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4081     } SBCR_b;
4082   };
4083 
4084   union {
4085     __IOM unsigned int SDMAM; /*!< (@ 0x00000094) Shadow DMA Mode */
4086 
4087     struct {
4088       __IOM unsigned int SDMAM : 1;     /*!< [0..0] Shadow DMA Mode     */
4089       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4090     } SDMAM_b;
4091   };
4092 
4093   union {
4094     __IOM unsigned int SFE; /*!< (@ 0x00000098) Shadow FIFO Enable */
4095 
4096     struct {
4097       __IOM unsigned int SFE : 1;       /*!< [0..0] Shadow FIFO Enable       */
4098       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4099     } SFE_b;
4100   };
4101 
4102   union {
4103     __IOM unsigned int SRT; /*!< (@ 0x0000009C) Shadow RCVR Trigger */
4104 
4105     struct {
4106       __IOM unsigned int SRT : 2;       /*!< [1..0] Shadow RCVR Trigger       */
4107       __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */
4108     } SRT_b;
4109   };
4110 
4111   union {
4112     __IOM unsigned int STET; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */
4113 
4114     struct {
4115       __IOM unsigned int STET : 2;      /*!< [1..0] Shadow TX Empty Trigger      */
4116       __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */
4117     } STET_b;
4118   };
4119 
4120   union {
4121     __IOM unsigned int HTX; /*!< (@ 0x000000A4) Halt Transmit */
4122 
4123     struct {
4124       __IOM unsigned int HALT_TX : 1;   /*!< [0..0] This register is use to halt
4125                                        transmissions for testing             */
4126       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4127     } HTX_b;
4128   };
4129 
4130   union {
4131     __IOM unsigned int DMASA; /*!< (@ 0x000000A8) DMA Software Acknowledge */
4132 
4133     struct {
4134       __OM unsigned int DMA_SOFTWARE_ACK : 1; /*!< [0..0] This register is use to perform a
4135                                    DMA software acknowledge
4136                                            if a transfer needs to be terminated
4137                                    due to an error condition            */
4138       __IM unsigned int RESERVED1 : 31;       /*!< [31..1] reserved1 */
4139     } DMASA_b;
4140   };
4141 
4142   union {
4143     __IOM unsigned int TCR; /*!< (@ 0x000000AC) Transceiver Control Register. */
4144 
4145     struct {
4146       __IOM unsigned int RS485_EN : 1;  /*!< [0..0] RS485 Transfer Enable.  */
4147       __IOM unsigned int RE_POL : 1;    /*!< [1..1] Receiver Enable Polarity.    */
4148       __IOM unsigned int DE_POL : 1;    /*!< [2..2] Driver Enable Polarity.    */
4149       __IOM unsigned int XFER_MODE : 2; /*!< [4..3] Transfer Mode. */
4150       __IM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */
4151     } TCR_b;
4152   };
4153 
4154   union {
4155     __IOM unsigned int DE_EN; /*!< (@ 0x000000B0) Driver Output Enable Register. */
4156 
4157     struct {
4158       __IOM unsigned int DE_EN : 1;     /*!< [0..0] DE Enable control.     */
4159       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4160     } DE_EN_b;
4161   };
4162 
4163   union {
4164     __IOM unsigned int RE_EN; /*!< (@ 0x000000B4) Receiver Output Enable Register. */
4165 
4166     struct {
4167       __IOM unsigned int RE_EN : 1;     /*!< [0..0] RE Enable control.     */
4168       __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */
4169     } RE_EN_b;
4170   };
4171 
4172   union {
4173     __IOM unsigned int DET; /*!< (@ 0x000000B8) Driver Output Enable Timing Register. */
4174 
4175     struct {
4176       __IOM unsigned int DE_ASSERT_TIME : 8;    /*!< [7..0] Driver enable assertion time. */
4177       __IOM unsigned int RES : 8;               /*!< [15..8] reserved. */
4178       __IOM unsigned int DE_DE_ASSERT_TIME : 8; /*!< [23..16] Driver enable
4179                                                de-assertion time. */
4180       __IM unsigned int RESERVED1 : 8;          /*!< [31..24] reserved1          */
4181     } DET_b;
4182   };
4183 
4184   union {
4185     __IOM unsigned int TAT; /*!< (@ 0x000000BC) TurnAround Timing Register */
4186 
4187     struct {
4188       __IOM unsigned int DE_RE : 16; /*!< [15..0] Driver Enable to Receiver Enable
4189                                     TurnAround time.                 */
4190       __IOM unsigned int RE_DE : 16; /*!< [31..16] Receiver Enable to Driver Enable
4191                                     TurnAround time.                */
4192     } TAT_b;
4193   };
4194 
4195   union {
4196     __IOM unsigned int DLF; /*!< (@ 0x000000C0) Divisor Latch Fraction Register. */
4197 
4198     struct {
4199       __IOM unsigned int DLF : 6; /*!< [5..0] Fractional part of divisor. */
4200       __IM unsigned int : 1;
4201       __IM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */
4202     } DLF_b;
4203   };
4204 
4205   union {
4206     __IOM unsigned int RAR; /*!< (@ 0x000000C4) Receive Address Register. */
4207 
4208     struct {
4209       __IOM unsigned int RAR : 8;       /*!< [7..0] This is an address matching register
4210                                  during receive mode.          */
4211       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
4212     } RAR_b;
4213   };
4214 
4215   union {
4216     __IOM unsigned int TAR; /*!< (@ 0x000000C8) Transmit Address Register. */
4217 
4218     struct {
4219       __IOM unsigned int TAR : 8;       /*!< [7..0] This is an address matching register
4220                                  during transmit mode. */
4221       __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */
4222     } TAR_b;
4223   };
4224 
4225   union {
4226     __IOM unsigned int LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */
4227 
4228     struct {
4229       __IOM unsigned int DLS_E : 1;         /*!< [0..0] Extension for DLS.      */
4230       __IOM unsigned int ADDR_MATCH : 1;    /*!< [1..1] Address Match Mode. */
4231       __IOM unsigned int SEND_ADDR : 1;     /*!< [2..2] Send address control bit.  */
4232       __IOM unsigned int TRANSMIT_MODE : 1; /*!< [3..3] Transmit mode control bit.        */
4233       __IM unsigned int RESERVED1 : 28;     /*!< [31..4] reserved1 */
4234     } LCR_EXT_b;
4235   };
4236   __IM unsigned int RESERVED3[9];
4237 
4238   union {
4239     __IM unsigned int CPR; /*!< (@ 0x000000F4) Component Parameter Register */
4240 
4241     struct {
4242       __IM unsigned int APB_DATA_WIDTH : 2;          /*!< [1..0] APB data width register.            */
4243       __IM unsigned int RESERVED1 : 2;               /*!< [3..2] reserved1       */
4244       __IM unsigned int AFCE_MODE : 1;               /*!< [4..4] none       */
4245       __IM unsigned int THRE_MODE : 1;               /*!< [5..5] none       */
4246       __IM unsigned int SIR_MODE : 1;                /*!< [6..6] none        */
4247       __IM unsigned int SIR_LP_MODE : 1;             /*!< [7..7] none     */
4248       __IM unsigned int ADDITIONAL_FEAT : 1;         /*!< [8..8] none */
4249       __IM unsigned int FIFO_ACCESS : 1;             /*!< [9..9] none     */
4250       __IM unsigned int FIFO_STAT : 1;               /*!< [10..10] none       */
4251       __IM unsigned int SHADOW : 1;                  /*!< [11..11] none          */
4252       __IM unsigned int UART_ADD_ENCODED_PARAMS : 1; /*!< [12..12] none */
4253       __IM unsigned int DMA_EXTRA : 1;               /*!< [13..13] none               */
4254       __IM unsigned int RESERVED2 : 2;               /*!< [15..14] reserved2               */
4255       __IM unsigned int FIFO_MODE : 8;               /*!< [23..16] none               */
4256       __IM unsigned int RESERVED3 : 8;               /*!< [31..24] reserved3               */
4257     } CPR_b;
4258   };
4259 
4260   union {
4261     __IM unsigned int UCV; /*!< (@ 0x000000F8) UART Component Version */
4262 
4263     struct {
4264       __IM unsigned int UART_COMP_VER : 32; /*!< [31..0] ASCII value for each number
4265                                            in the version, followed by * */
4266     } UCV_b;
4267   };
4268 
4269   union {
4270     __IM unsigned int CTR; /*!< (@ 0x000000FC) Component Type Register */
4271 
4272     struct {
4273       __IM unsigned int UART_COMP_VER : 32; /*!< [31..0] This register contains the
4274                                            peripherals identification code. */
4275     } CTR_b;
4276   };
4277 } USART0_Type; /*!< Size = 256 (0x100) */
4278 
4279 /* ===========================================================================================================================
4280  */
4281 /* ================                                           GSPI0
4282  * ================ */
4283 /* ===========================================================================================================================
4284  */
4285 
4286 /**
4287  * @brief GSPI, or Generic SPI, is a module which has been derived from QSPI.
4288  * GSPI can act only as a master (GSPI0)
4289  */
4290 
4291 typedef struct { /*!< (@ 0x45030000) GSPI0 Structure */
4292 
4293   union {
4294     __IOM unsigned int GSPI_CLK_CONFIG; /*!< (@ 0x00000000) GSPI Clock Configuration
4295                                        Register                          */
4296 
4297     struct {
4298       __IOM unsigned int GSPI_CLK_SYNC : 1; /*!< [0..0] If the clock frequency to FLASH
4299                                 (spi_clk) and SOC clk is same. */
4300       __IOM unsigned int GSPI_CLK_EN : 1;   /*!< [1..1] GSPI clock enable */
4301       __IOM unsigned int RESERVED1 : 30;    /*!< [31..2] reserved for future use  */
4302     } GSPI_CLK_CONFIG_b;
4303   };
4304 
4305   union {
4306     __IOM unsigned int GSPI_BUS_MODE; /*!< (@ 0x00000004) GSPI Bus Mode Register */
4307 
4308     struct {
4309       __IOM unsigned int GSPI_DATA_SAMPLE_EDGE : 1;   /*!< [0..0] Samples MISO data on
4310                                                    clock edges. This should be
4311                                                    ZERO for mode3 clock */
4312       __IOM unsigned int GSPI_CLK_MODE_CSN0 : 1;      /*!< [1..1] NONE    */
4313       __IOM unsigned int GSPI_CLK_MODE_CSN1 : 1;      /*!< [2..2] NONE    */
4314       __IOM unsigned int GSPI_CLK_MODE_CSN2 : 1;      /*!< [3..3] NONE    */
4315       __IOM unsigned int GSPI_CLK_MODE_CSN3 : 1;      /*!< [4..4] NONE    */
4316       __IOM unsigned int GSPI_GPIO_MODE_ENABLES : 6;  /*!< [10..5] These bits are used to map
4317                                          GSPI on GPIO pins */
4318       __IOM unsigned int SPI_HIGH_PERFORMANCE_EN : 1; /*!< [11..11] High performance
4319                                                      features are enabled when
4320                                                      this bit is set to one */
4321       __IOM unsigned int RESERVED1 : 20;              /*!< [31..12] reserved for future use */
4322     } GSPI_BUS_MODE_b;
4323   };
4324   __IM unsigned int RESERVED[2];
4325 
4326   union {
4327     __IOM unsigned int GSPI_CONFIG1; /*!< (@ 0x00000010) GSPI Configuration 1 Register */
4328 
4329     struct {
4330       __IOM unsigned int GSPI_MANUAL_CSN : 1;        /*!< [0..0] SPI CS in manual mode */
4331       __IOM unsigned int GSPI_MANUAL_WR : 1;         /*!< [1..1] Write enable for manual
4332                                              mode when CS is low.  */
4333       __IOM unsigned int GSPI_MANUAL_RD : 1;         /*!< [2..2] Read enable for manual mode
4334                                             when CS is low */
4335       __IOM unsigned int GSPI_MANUAL_RD_CNT : 10;    /*!< [12..3] Indicates total
4336                                                  number of bytes to be read */
4337       __IOM unsigned int GSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which CSn is
4338                                          valid. Can be programmable in manual
4339                                          mode */
4340       __IOM unsigned int SPI_FULL_DUPLEX_EN : 1;     /*!< [15..15] Full duplex mode enable    */
4341       __IOM unsigned int RESERVED1 : 16;             /*!< [31..16] reserved for future use */
4342     } GSPI_CONFIG1_b;
4343   };
4344 
4345   union {
4346     __IOM unsigned int GSPI_CONFIG2; /*!< (@ 0x00000014) GSPI Manual Configuration 2
4347                                     Register                       */
4348 
4349     struct {
4350       __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN0 : 1;       /*!< [0..0] Swap the write data inside
4351                                              the GSPI controller it-self. */
4352       __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN1 : 1;       /*!< [1..1] Swap the write data inside
4353                                              the GSPI controller it-self. */
4354       __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN2 : 1;       /*!< [2..2] Swap the write data inside
4355                                              the GSPI controller it-self. */
4356       __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN3 : 1;       /*!< [3..3] Swap the write data inside
4357                                              the GSPI controller it-self. */
4358       __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN0 : 1;       /*!< [4..4] Swap the read data inside
4359                                              the GSPI controller it-self. */
4360       __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN1 : 1;       /*!< [5..5] Swap the read data inside
4361                                              the GSPI controller it-self. */
4362       __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN2 : 1;       /*!< [6..6] Swap the read data inside
4363                                              the GSPI controller it-self. */
4364       __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN3 : 1;       /*!< [7..7] Swap the read data inside
4365                                              the GSPI controller it-self. */
4366       __IOM unsigned int GSPI_MANUAL_SIZE_FRM_REG : 1;         /*!< [8..8] Manual reads and
4367                                                       manual writes */
4368       __IOM unsigned int RESERVED1 : 1;                        /*!< [9..9] reserved for future use */
4369       __IOM unsigned int TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [10..10] NONE */
4370       __IOM unsigned int MANUAL_GSPI_MODE : 1;                 /*!< [11..11] Internally the priority
4371                                               is given to manual mode */
4372       __IOM unsigned int RESERVED2 : 20;                       /*!< [31..12] reserved for future use */
4373     } GSPI_CONFIG2_b;
4374   };
4375 
4376   union {
4377     __IOM unsigned int GSPI_WRITE_DATA2; /*!< (@ 0x00000018) GSPI Write Data 2 Register */
4378 
4379     struct {
4380       __IOM unsigned int GSPI_MANUAL_WRITE_DATA2 : 4; /*!< [3..0] Number of bits to be written
4381                                           in write mode */
4382       __IOM unsigned int RESERVED1 : 3;               /*!< [6..4] reserved for future use    */
4383       __IOM unsigned int USE_PREV_LENGTH : 1;         /*!< [7..7] Use previous length */
4384       __IOM unsigned int RESERVED2 : 24;              /*!< [31..8] reserved for future use */
4385     } GSPI_WRITE_DATA2_b;
4386   };
4387 
4388   union {
4389     __IOM unsigned int GSPI_FIFO_THRLD; /*!< (@ 0x0000001C) GSPI FIFO Threshold Register */
4390 
4391     struct {
4392       __IOM unsigned int FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */
4393       __IOM unsigned int FIFO_AFULL_THRLD : 4;  /*!< [7..4] FIFO almost full threshold       */
4394       __IOM unsigned int WFIFO_RESET : 1;       /*!< [8..8] Write FIFO reset */
4395       __IOM unsigned int RFIFO_RESET : 1;       /*!< [9..9] read FIFO reset */
4396       __IOM unsigned int RESERVED1 : 22;        /*!< [31..10] reserved for future use  */
4397     } GSPI_FIFO_THRLD_b;
4398   };
4399 
4400   union {
4401     __IM unsigned int GSPI_STATUS; /*!< (@ 0x00000020) GSPI Status Register */
4402 
4403     struct {
4404       __IM unsigned int GSPI_BUSY : 1;           /*!< [0..0] State of Manual mode         */
4405       __IM unsigned int FIFO_FULL_WFIFO_S : 1;   /*!< [1..1] Full status indication
4406                                               for Wfifo in manual mode */
4407       __IM unsigned int FIFO_AFULL_WFIFO_S : 1;  /*!< [2..2] Almost full status indication for
4408                                      Wfifo in manual mode             */
4409       __IM unsigned int FIFO_EMPTY_WFIFO : 1;    /*!< [3..3] Empty status indication
4410                                              for Wfifo in manual mode */
4411       __IM unsigned int RESERVED1 : 1;           /*!< [4..4] reserved for future use        */
4412       __IM unsigned int FIFO_FULL_RFIFO : 1;     /*!< [5..5] Full status indication for
4413                                              Rfifo in manual mode  */
4414       __IM unsigned int RESERVED2 : 1;           /*!< [6..6] reserved for future use        */
4415       __IM unsigned int FIFO_EMPTY_RFIFO_S : 1;  /*!< [7..7] Empty status indication
4416                                                for Rfifo in manual mode */
4417       __IM unsigned int FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Aempty status indication for
4418                                       Rfifo in manual mode                  */
4419       __IM unsigned int GSPI_MANUAL_RD_CNT : 1;  /*!< [9..9] This is a result of 10
4420                                                bits ORing counter */
4421       __IM unsigned int GSPI_MANUAL_CSN : 1;     /*!< [10..10] Provide the status of
4422                                                chip select signal    */
4423       __IM unsigned int RESERVED3 : 21;          /*!< [31..11] reserved for future use */
4424     } GSPI_STATUS_b;
4425   };
4426 
4427   union {
4428     __IOM unsigned int GSPI_INTR_MASK; /*!< (@ 0x00000024) GSPI Interrupt Mask Register */
4429 
4430     struct {
4431       __IOM unsigned int GSPI_INTR_MASK : 1;         /*!< [0..0] GSPI Interrupt mask bit */
4432       __IOM unsigned int FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */
4433       __IOM unsigned int FIFO_AFULL_RFIFO_MASK : 1;  /*!< [2..2] NONE  */
4434       __IOM unsigned int FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */
4435       __IOM unsigned int FIFO_AFULL_WFIFO_MASK : 1;  /*!< [4..4] NONE  */
4436       __IOM unsigned int FIFO_FULL_WFIFO_MASK : 1;   /*!< [5..5] NONE   */
4437       __IOM unsigned int FIFO_EMPTY_RFIFO_MASK : 1;  /*!< [6..6] NONE  */
4438       __IOM unsigned int RESERVED1 : 25;             /*!< [31..7] reserved for future use */
4439     } GSPI_INTR_MASK_b;
4440   };
4441 
4442   union {
4443     __IOM unsigned int GSPI_INTR_UNMASK; /*!< (@ 0x00000028) GSPI Interrupt Unmask
4444                                         Register                             */
4445 
4446     struct {
4447       __IOM unsigned int GSPI_INTR_UNMASK : 1;         /*!< [0..0] GSPI Interrupt unmask bit */
4448       __IOM unsigned int FIFO_AEMPTY_RFIFO_UNMASK : 1; /*!< [1..1] NONE */
4449       __IOM unsigned int FIFO_AFULL_RFIFO_UNMASK : 1;  /*!< [2..2] NONE  */
4450       __IOM unsigned int FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */
4451       __IOM unsigned int FIFO_AFULL_WFIFO_UNMASK : 1;  /*!< [4..4] NONE  */
4452       __IOM unsigned int FIFO_FULL_WFIFO_UNMASK : 1;   /*!< [5..5] NONE   */
4453       __IOM unsigned int FIFO_EMPTY_RFIFO_UNMASK : 1;  /*!< [6..6] NONE  */
4454       __IOM unsigned int RESERVED1 : 25;               /*!< [31..7] reserved for future use */
4455     } GSPI_INTR_UNMASK_b;
4456   };
4457 
4458   union {
4459     __IM unsigned int GSPI_INTR_STS; /*!< (@ 0x0000002C) GSPI Interrupt Status Register */
4460 
4461     struct {
4462       __IM unsigned int GSPI_INTR_LVL : 1;         /*!< [0..0] GSPI Interrupt status bit */
4463       __IM unsigned int FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */
4464       __IM unsigned int FIFO_AFULL_RFIFO_LVL : 1;  /*!< [2..2] NONE  */
4465       __IM unsigned int FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */
4466       __IM unsigned int FIFO_AFULL_WFIFO_LVL : 1;  /*!< [4..4] NONE  */
4467       __IM unsigned int FIFO_FULL_WFIFO_LVL : 1;   /*!< [5..5] NONE   */
4468       __IM unsigned int FIFO_EMPTY_RFIFO_LVL : 1;  /*!< [6..6] NONE  */
4469       __IM unsigned int RESERVED2 : 25;            /*!< [31..7] reserved for future use */
4470     } GSPI_INTR_STS_b;
4471   };
4472 
4473   union {
4474     __OM unsigned int GSPI_INTR_ACK; /*!< (@ 0x00000030) GSPI Interrupt Acknowledge
4475                                     Register                        */
4476 
4477     struct {
4478       __OM unsigned int GSPI_INTR_ACK : 1;         /*!< [0..0] GSPI Interrupt status bit */
4479       __OM unsigned int FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */
4480       __OM unsigned int FIFO_AFULL_RFIFO_ACK : 1;  /*!< [2..2] NONE  */
4481       __OM unsigned int FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */
4482       __OM unsigned int FIFO_AFULL_WFIFO_ACK : 1;  /*!< [4..4] NONE  */
4483       __OM unsigned int FIFO_FULL_WFIFO_ACK : 1;   /*!< [5..5] NONE   */
4484       __OM unsigned int FIFO_EMPTY_RFIFO_ACK : 1;  /*!< [6..6] NONE  */
4485       __OM unsigned int RESERVED2 : 25;            /*!< [31..7] reserved1            */
4486     } GSPI_INTR_ACK_b;
4487   };
4488 
4489   union {
4490     __IM unsigned int GSPI_STS_MC; /*!< (@ 0x00000034) GSPI State Machine Monitor
4491                                   Register                        */
4492 
4493     struct {
4494       __IM unsigned int BUS_CTRL_PSTATE : 3; /*!< [2..0] Provides SPI bus controller
4495                                             present state */
4496       __IM unsigned int SPI_RD_CNT : 13;     /*!< [15..3] number of pending bytes to be
4497                                         read by device                      */
4498       __IM unsigned int RESERVED1 : 16;      /*!< [31..16] reserved1  */
4499     } GSPI_STS_MC_b;
4500   };
4501 
4502   union {
4503     __IOM unsigned int GSPI_CLK_DIV; /*!< (@ 0x00000038) GSPI Clock Division Factor
4504                                     Register                        */
4505 
4506     struct {
4507       __IOM unsigned int GSPI_CLK_DIV_FACTOR : 8; /*!< [7..0] Provides GSPI clock division
4508                                        factor to the clock divider,  which takes
4509                                        SOC clock as input clock and generates
4510                                        required  clock according to division
4511                                        factor  */
4512       __IM unsigned int RESERVED1 : 24;           /*!< [31..8] reserved1 */
4513     } GSPI_CLK_DIV_b;
4514   };
4515 
4516   union {
4517     __IOM unsigned int GSPI_CONFIG3; /*!< (@ 0x0000003C) GSPI Configuration 3 Register */
4518 
4519     struct {
4520       __IOM unsigned int SPI_MANUAL_RD_LNTH_TO_BC : 15; /*!< [14..0] Bits are used to indicate
4521                                           the total number of bytes
4522                                           to read from flash during read
4523                                           operation */
4524       __IOM unsigned int RESERVED1 : 17;                /*!< [31..15] reserved1     */
4525     } GSPI_CONFIG3_b;
4526   };
4527   __IM unsigned int RESERVED1[16];
4528 
4529   union {
4530     union {
4531       __OM unsigned int GSPI_WRITE_FIFO[16]; /*!< (@ 0x00000080) GSPI fifo */
4532 
4533       struct {
4534         __OM unsigned int WRITE_FIFO : 32; /*!< [31..0] FIFO data is write to this
4535                                           address space */
4536       } GSPI_WRITE_FIFO_b[16];
4537     };
4538 
4539     union {
4540       __IM unsigned int GSPI_READ_FIFO[16]; /*!< (@ 0x00000080) GSPI READ FIFO */
4541 
4542       struct {
4543         __IM unsigned int READ_FIFO : 32; /*!< [31..0] FIFO data is read from this
4544                                          address space */
4545       } GSPI_READ_FIFO_b[16];
4546     };
4547   };
4548 } GSPI0_Type; /*!< Size = 192 (0xc0) */
4549 
4550 /* ===========================================================================================================================
4551  */
4552 /* ================                                           SSI0
4553  * ================ */
4554 /* ===========================================================================================================================
4555  */
4556 
4557 /**
4558  * @brief Synchronous Serial Interface(SSI) (SSI0)
4559  */
4560 
4561 typedef struct { /*!< (@ 0x44020000) SSI0 Structure */
4562 
4563   union {
4564     __IOM unsigned int CTRLR0; /*!< (@ 0x00000000) Control Register 0 */
4565 
4566     struct {
4567       __IOM unsigned int DFS : 4;       /*!< [3..0] Select the data frame length (4-bit to
4568                                  16-bit serial data transfers) */
4569       __IOM unsigned int FRF : 2;       /*!< [5..4] Frame Format, Selects which serial
4570                                  protocol transfers the data */
4571       __IOM unsigned int SCPH : 1;      /*!< [6..6] Serial Clock Phase. Valid when the
4572                                   frame format (FRF) is set to Motorola SPI */
4573       __IOM unsigned int SCPOL : 1;     /*!< [7..7] Serial Clock Polarity. Valid when the frame
4574                         format (FRF) is set to Motorola SPI */
4575       __IOM unsigned int TMOD : 2;      /*!< [9..8] Selects the mode of transfer for
4576                                     serial communication              */
4577       __IOM unsigned int SLV_OE : 1;    /*!< [10..10] DW_apb_ssi is configured as a
4578                                     serial-slave device                */
4579       __IOM unsigned int SRL : 1;       /*!< [11..11] Shift Register Loop Used for testing
4580                                  purposes only               */
4581       __IOM unsigned int CFS : 4;       /*!< [15..12] Control Frame Size Selects the length of the
4582                       control word for the Micro wire frame format */
4583       __IOM unsigned int DFS_32 : 5;    /*!< [20..16] Selects the data frame length             */
4584       __IOM unsigned int SPI_FRF : 2;   /*!< [22..21] Selects data frame format for
4585                                      transmitting or receiving data */
4586       __IOM unsigned int RESERVED1 : 9; /*!< [31..23] Reserved for future use */
4587     } CTRLR0_b;
4588   };
4589 
4590   union {
4591     __IOM unsigned int CTRLR1; /*!< (@ 0x00000004) Control Register 1 */
4592 
4593     struct {
4594       __IOM unsigned int NDF : 16;       /*!< [15..0] Number of Data Frames.When TMOD = 10 or TMOD =
4595                        11, this register field sets the number of data frames to
4596                        be continuously received by the ssi_master */
4597       __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use. */
4598     } CTRLR1_b;
4599   };
4600 
4601   union {
4602     __IOM unsigned int SSIENR; /*!< (@ 0x00000008) SSI Enable Register */
4603 
4604     struct {
4605       __IOM unsigned int SSI_EN : 1;     /*!< [0..0] Enables and disables all ssi operations */
4606       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
4607     } SSIENR_b;
4608   };
4609 
4610   union {
4611     __IOM unsigned int MWCR; /*!< (@ 0x0000000C) Micro wire Control Register */
4612 
4613     struct {
4614       __IOM unsigned int MWMOD : 1;      /*!< [0..0] The Micro wire transfer is
4615                                    sequential or non-sequential            */
4616       __IOM unsigned int MDD : 1;        /*!< [1..1] The direction of the data word when
4617                                    the Micro wire serial   protocol is used   */
4618       __IOM unsigned int MHS : 1;        /*!< [2..2] Microwire Handshaking. Used to enable
4619                                  and disable the busy/ready handshaking
4620                                  interface for the Microwire protocol */
4621       __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */
4622     } MWCR_b;
4623   };
4624 
4625   union {
4626     __IOM unsigned int SER; /*!< (@ 0x00000010) SLAVE ENABLE REGISTER */
4627 
4628     struct {
4629       __IOM unsigned int SER : 4;        /*!< [3..0] Each bit in this register corresponds to a slave
4630                       select line (ss_x_n) from the SSI master. */
4631       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
4632     } SER_b;
4633   };
4634 
4635   union {
4636     __IOM unsigned int BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */
4637 
4638     struct {
4639       __IOM unsigned int SCKDV : 16;     /*!< [15..0] SSI Clock Divider.The LSB for this
4640                                     field is always set to 0 and is unaffected
4641                                     by a write operation, which ensures
4642                                                  an even value is held in this
4643                                     register */
4644       __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */
4645     } BAUDR_b;
4646   };
4647 
4648   union {
4649     __IOM unsigned int TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */
4650 
4651     struct {
4652       __IOM unsigned int TFT : 4;        /*!< [3..0] Controls the level of entries (or below) at which
4653                       the transmit  FIFO controller triggers an interrupt */
4654       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
4655     } TXFTLR_b;
4656   };
4657 
4658   union {
4659     __IOM unsigned int RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level */
4660 
4661     struct {
4662       __IOM unsigned int RFT : 4;        /*!< [3..0] Controls the level of entries (or above) at which
4663                       the receive FIFO controller triggers an interrupt */
4664       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
4665     } RXFTLR_b;
4666   };
4667 
4668   union {
4669     __IM unsigned int TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */
4670 
4671     struct {
4672       __IM unsigned int TXTFL : 5;      /*!< [4..0] Contains the number of valid data
4673                                   entries in the transmit FIFO */
4674       __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */
4675     } TXFLR_b;
4676   };
4677 
4678   union {
4679     __IM unsigned int RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */
4680 
4681     struct {
4682       __IM unsigned int RXTFL : 5;      /*!< [4..0] Contains the number of valid data
4683                                   entries in the receive FIFO */
4684       __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */
4685     } RXFLR_b;
4686   };
4687 
4688   union {
4689     __IM unsigned int SR; /*!< (@ 0x00000028) Status Register */
4690 
4691     struct {
4692       __IM unsigned int BUSY : 1;       /*!< [0..0] indicates that a serial transfer is in
4693                                  progress                    */
4694       __IM unsigned int TFNF : 1;       /*!< [1..1] Set when the transmit FIFO contains one or more
4695                        empty locations and is cleared when the FIFO is full */
4696       __IM unsigned int TFE : 1;        /*!< [2..2] When the transmit FIFO is completely
4697                                  empty this bit is  set  */
4698       __IM unsigned int RFNE : 1;       /*!< [3..3] Set when the receive FIFO contains one
4699                                  or more entries and is  cleared when the
4700                                  receive FIFO is empty */
4701       __IM unsigned int RFF : 1;        /*!< [4..4] When the receive FIFO is completely
4702                                  full this bit is  set  */
4703       __IM unsigned int TXE : 1;        /*!< [5..5] This bit is cleared when read  */
4704       __IM unsigned int DCOL : 1;       /*!< [6..6] This bit is set if the ss_in_n input
4705                                  is asserted by another master, while the ssi
4706                                  master is in the middle of the transfer */
4707       __IM unsigned int RESERVED1 : 25; /*!< [31..7] Reserved for future use */
4708     } SR_b;
4709   };
4710 
4711   union {
4712     __IOM unsigned int IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */
4713 
4714     struct {
4715       __IOM unsigned int TXEIM : 1;     /*!< [0..0] Transmit FIFO Empty Interrupt Mask */
4716       __IOM unsigned int TXOIM : 1;     /*!< [1..1] Transmit FIFO Overflow Interrupt Mask */
4717       __IOM unsigned int RXUIM : 1;     /*!< [2..2] Receive FIFO Underflow Interrupt Mask */
4718       __IOM unsigned int RXOIM : 1;     /*!< [3..3] Receive FIFO Overflow Interrupt Mask */
4719       __IOM unsigned int RXFIM : 1;     /*!< [4..4] Receive FIFO Full Interrupt Mask */
4720       __IOM unsigned int MSTIM : 1;     /*!< [5..5] Multi-Master Contention Interrupt Mask */
4721       __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */
4722     } IMR_b;
4723   };
4724 
4725   union {
4726     __IM unsigned int ISR; /*!< (@ 0x00000030) Interrupt Status Register */
4727 
4728     struct {
4729       __IM unsigned int TXEIS : 1;      /*!< [0..0] Transmit FIFO Empty Interrupt Status */
4730       __IM unsigned int TXOIS : 1;      /*!< [1..1] Transmit FIFO Overflow Interrupt Status */
4731       __IM unsigned int RXUIS : 1;      /*!< [2..2] Receive FIFO Underflow Interrupt Status */
4732       __IM unsigned int RXOIS : 1;      /*!< [3..3] Receive FIFO Overflow Interrupt Status */
4733       __IM unsigned int RXFIS : 1;      /*!< [4..4] Receive FIFO Full Interrupt Status */
4734       __IM unsigned int MSTIS : 1;      /*!< [5..5] Multi-Master Contention Interrupt Status */
4735       __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */
4736     } ISR_b;
4737   };
4738 
4739   union {
4740     __IM unsigned int RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */
4741 
4742     struct {
4743       __IM unsigned int TXEIR : 1;      /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */
4744       __IM unsigned int TXOIR : 1;      /*!< [1..1] Transmit FIFO Overflow Raw Interrupt
4745                                   Status                        */
4746       __IM unsigned int RXUIR : 1;      /*!< [2..2] Receive FIFO Underflow Raw Interrupt
4747                                   Status                        */
4748       __IM unsigned int RXOIR : 1;      /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */
4749       __IM unsigned int RXFIR : 1;      /*!< [4..4] Receive FIFO Full Raw Interrupt Status */
4750       __IM unsigned int MSTIR : 1;      /*!< [5..5] Multi-Master Contention Raw Interrupt
4751                                   Status                       */
4752       __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */
4753     } RISR_b;
4754   };
4755 
4756   union {
4757     __IM unsigned int TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt
4758                              Clear Register            */
4759 
4760     struct {
4761       __IM unsigned int TXOICR : 1;     /*!< [0..0] Clear Transmit FIFO Overflow Interrupt This
4762                          register reflects the status of the interrupt */
4763       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
4764     } TXOICR_b;
4765   };
4766 
4767   union {
4768     __IM unsigned int RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt
4769                              Clear Register             */
4770 
4771     struct {
4772       __IM unsigned int RXOICR : 1;     /*!< [0..0] This register reflects the status of
4773                                    the interrupt A read from this  register
4774                                    clears the ssi_rxo_intr interrupt */
4775       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
4776     } RXOICR_b;
4777   };
4778 
4779   union {
4780     __IM unsigned int RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt
4781                              Clear Register            */
4782 
4783     struct {
4784       __IM unsigned int RXUICR : 1;     /*!< [0..0] This register reflects the status of
4785                                    the interrupt A read from this  register
4786                                    clears the ssi_rxu_intr interrupt */
4787       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
4788     } RXUICR_b;
4789   };
4790 
4791   union {
4792     __IM unsigned int MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */
4793 
4794     struct {
4795       __IM unsigned int MSTICR : 1;     /*!< [0..0] This register reflects the status of
4796                                    the interrupt A read from this  register
4797                                    clears the ssi_mst_intr interrupt */
4798       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
4799     } MSTICR_b;
4800   };
4801 
4802   union {
4803     __IM unsigned int ICR; /*!< (@ 0x00000048) Interrupt Clear Register */
4804 
4805     struct {
4806       __IM unsigned int ICR : 1;        /*!< [0..0] This register is set if any of the
4807                                 interrupts below are active A read clears the
4808                                 ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and
4809                                 the ssi_mst_intr interrupts */
4810       __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
4811     } ICR_b;
4812   };
4813 
4814   union {
4815     __IOM unsigned int DMACR; /*!< (@ 0x0000004C) DMA Control Register */
4816 
4817     struct {
4818       __IOM unsigned int RDMAE : 1;     /*!< [0..0] This bit enables/disables the
4819                                        receive FIFO DMA channel             */
4820       __IOM unsigned int TDMAE : 1;     /*!< [1..1] This bit enables/disables the
4821                                        transmit FIFO DMA channel            */
4822       __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved for future use */
4823     } DMACR_b;
4824   };
4825 
4826   union {
4827     __IOM unsigned int DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level */
4828 
4829     struct {
4830       __IOM unsigned int DMATDL : 4;    /*!< [3..0] This bit field controls the level at which a
4831                          DMA request is made by the transmit logic */
4832       __IM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
4833     } DMATDLR_b;
4834   };
4835 
4836   union {
4837     __IOM unsigned int DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */
4838 
4839     struct {
4840       __IOM unsigned int DMARDL : 4;     /*!< [3..0] This bit field controls the level at which a
4841                          DMA request is made by the receive logic */
4842       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */
4843     } DMARDLR_b;
4844   };
4845 
4846   union {
4847     __IM unsigned int IDR; /*!< (@ 0x00000058) Identification Register */
4848 
4849     struct {
4850       __IM unsigned int IDCODE : 32; /*!< [31..0] This register contains the
4851                                     peripherals identification code */
4852     } IDR_b;
4853   };
4854 
4855   union {
4856     __IM unsigned int SSI_COMP_VERSION; /*!< (@ 0x0000005C) coreKit version ID register */
4857 
4858     struct {
4859       __IM unsigned int SSI_COMP_VERSION : 32; /*!< [31..0] Contains the hex representation of
4860                                     the Synopsys component version */
4861     } SSI_COMP_VERSION_b;
4862   };
4863 
4864   union {
4865     __IOM unsigned int DR; /*!< (@ 0x00000060) Data Register */
4866 
4867     struct {
4868       __IOM unsigned int DR : 32; /*!< [31..0] When writing to this register must
4869                                  right-justify the data */
4870     } DR_b;
4871   };
4872   __IM unsigned int RESERVED[35];
4873 
4874   union {
4875     __IOM unsigned int RX_SAMPLE_DLY; /*!< (@ 0x000000F0) Rx Sample Delay Register */
4876 
4877     struct {
4878       __IOM unsigned int RSD : 8;        /*!< [7..0] Receive Data (rxd) Sample Delay. This register is
4879                       used to delay the sample of the rxd input signal. */
4880       __IOM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved for future use */
4881     } RX_SAMPLE_DLY_b;
4882   };
4883 
4884   union {
4885     __IOM unsigned int SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control Register */
4886 
4887     struct {
4888       __IOM unsigned int TRANS_TYPE : 2;  /*!< [1..0] Address and instruction
4889                                         transfer format */
4890       __IOM unsigned int ADDR_L : 4;      /*!< [5..2] This bit defines length of address to be
4891                          transmitted, The transfer begins only after these many
4892                          bits are programmed into the FIFO */
4893       __IM unsigned int RESERVED1 : 2;    /*!< [7..6] Reserved for future use */
4894       __IOM unsigned int INST_L : 2;      /*!< [9..8] DUAL/QUAD length in bits   */
4895       __IM unsigned int RESERVED2 : 1;    /*!< [10..10] Reserved for future use */
4896       __IOM unsigned int WAIT_CYCLES : 4; /*!< [14..11] This bit defines the wait cycles in
4897                               dual/quad mode between control frames transmit and
4898                               data reception, Specified as number of SPI clock
4899                               cycles */
4900       __IM unsigned int RESERVED3 : 17;   /*!< [31..15] Reserved for future use */
4901     } SPI_CTRLR0_b;
4902   };
4903 } SSI0_Type; /*!< Size = 248 (0xf8) */
4904 
4905 /* ===========================================================================================================================
4906  */
4907 /* ================                                            SIO
4908  * ================ */
4909 /* ===========================================================================================================================
4910  */
4911 
4912 /**
4913  * @brief SERIAL GENERAL PERPOSE INPUT/OUTPUT (SIO)
4914  */
4915 
4916 typedef struct { /*!< (@ 0x47000000) SIO Structure */
4917 
4918   union {
4919     __IOM unsigned int SIO_ENABLE_REG; /*!< (@ 0x00000000) ENABLE REGISTER */
4920 
4921     struct {
4922       __IOM unsigned int SIO_OPERATION_ENABLE : 16; /*!< [15..0] Contains the
4923                                                    Enables for all SIO */
4924       __IM unsigned int RESERVED3 : 16;             /*!< [31..16] Reserved for future use */
4925     } SIO_ENABLE_REG_b;
4926   };
4927 
4928   union {
4929     __IOM unsigned int SIO_PAUSE_REG; /*!< (@ 0x00000004) PAUSE REGISTER */
4930 
4931     struct {
4932       __IOM unsigned int SIO_POSITION_COUNTER_DISABLE : 16; /*!< [15..0] Contains
4933                                                            sio position counter
4934                                                            disable for all SIOs
4935                                                          */
4936       __IM unsigned int RESERVED3 : 16;                     /*!< [31..16] Reserved for future use */
4937     } SIO_PAUSE_REG_b;
4938   };
4939 
4940   union {
4941     __IM unsigned int SIO_GPIO_IN_REG; /*!< (@ 0x00000008) GPIO Input Register */
4942 
4943     struct {
4944       __IM unsigned int IN_VALUE : 32; /*!< [31..0] GPIO input pin status */
4945     } SIO_GPIO_IN_REG_b;
4946   };
4947 
4948   union {
4949     __IOM unsigned int SIO_GPIO_OUT_REG; /*!< (@ 0x0000000C) GPIO Output Register */
4950 
4951     struct {
4952       __IOM unsigned int OUT_VALUE : 32; /*!< [31..0] Value to be loaded on GPIO out pins */
4953     } SIO_GPIO_OUT_REG_b;
4954   };
4955 
4956   union {
4957     __IOM unsigned int SIO_GPIO_OEN_REG; /*!< (@ 0x00000010) GPIO Output enable Register */
4958 
4959     struct {
4960       __IOM unsigned int OEN_VALUE : 32; /*!< [31..0] OEN for the GPIO pins */
4961     } SIO_GPIO_OEN_REG_b;
4962   };
4963 
4964   union {
4965     __IOM unsigned int SIO_GPIO_INTR_EN_SET_REG; /*!< (@ 0x00000014) GPIO Interrupt
4966                                                 Enable Set Register */
4967 
4968     struct {
4969       __OM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] gpio interrupt enable set
4970                                              register for all SIOs */
4971       __IM unsigned int RESERVED1 : 16;       /*!< [31..16] Reserved for future use */
4972     } SIO_GPIO_INTR_EN_SET_REG_b;
4973   };
4974 
4975   union {
4976     __OM unsigned int SIO_GPIO_INTR_EN_CLEAR_REG; /*!< (@ 0x00000018) GPIO Interrupt
4977                                                  Enable Clear Register */
4978 
4979     struct {
4980       __OM unsigned int INTR_ENABLE_CLEAR : 16; /*!< [15..0] gpio interrupt enable
4981                                                Clear register for all SIOs */
4982       __OM unsigned int RESERVED1 : 16;         /*!< [31..16] Reserved for future use */
4983     } SIO_GPIO_INTR_EN_CLEAR_REG_b;
4984   };
4985 
4986   union {
4987     __IOM unsigned int SIO_GPIO_INTR_MASK_SET_REG; /*!< (@ 0x0000001C) GPIO Interrupt Enable
4988                                        Clear Register                       */
4989 
4990     struct {
4991       __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt mask
4992                                             set register for all SIOs */
4993       __IM unsigned int RESERVED1 : 16;      /*!< [31..16] Reserved for future use */
4994     } SIO_GPIO_INTR_MASK_SET_REG_b;
4995   };
4996 
4997   union {
4998     __OM unsigned int SIO_GPIO_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000020) GPIO Interrupt Enable
4999                                          Clear Register                       */
5000 
5001     struct {
5002       __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] gpio interrupt mask clear
5003                                              register for all SIOs */
5004       __OM unsigned int RESERVED1 : 16;       /*!< [31..16] Reserved for future use */
5005     } SIO_GPIO_INTR_MASK_CLEAR_REG_b;
5006   };
5007 
5008   union {
5009     __IOM unsigned int SIO_GPIO_INTR_STATUS_REG; /*!< (@ 0x00000024) GPIO Interrupt
5010                                                 Status Register */
5011 
5012     struct {
5013       __OM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt
5014                                            status register for all SIOs */
5015       __IM unsigned int RESERVED1 : 16;     /*!< [31..16] Reserved for future use     */
5016     } SIO_GPIO_INTR_STATUS_REG_b;
5017   };
5018 
5019   union {
5020     __IM unsigned int SIO_SHIFT_COUNTER[16]; /*!< (@ 0x00000028) Shift counter register */
5021 
5022     struct {
5023       __IM unsigned int SHIFT_COUNTER : 14; /*!< [13..0] shift counter current value       */
5024       __IM unsigned int RESERVED1 : 18;     /*!< [31..14] Reserved for future use */
5025     } SIO_SHIFT_COUNTER_b[16];
5026   };
5027 
5028   union {
5029     __IOM unsigned int SIO_BUFFER_REG[16]; /*!< (@ 0x00000068) Buffer Register */
5030 
5031     struct {
5032       __IOM unsigned int DATA : 32; /*!< [31..0] Data to load into the shift register */
5033     } SIO_BUFFER_REG_b[16];
5034   };
5035 
5036   union {
5037     __IOM unsigned int SIO_SHIFT_COUNT_PRELOAD_REG[16]; /*!< (@ 0x000000A8) Shift counter
5038                                             Reload Register */
5039 
5040     struct {
5041       __IOM unsigned int RELOAD_VALUE : 14; /*!< [13..0] division factor required to
5042                                            generate shift clock */
5043       __IM unsigned int RESERVED1 : 1;      /*!< [14..14] Reserved for future use      */
5044       __IOM unsigned int REVERSE_LOAD : 1;  /*!< [15..15] When set, the data on APB is loaded to
5045                                buffer is reverse order */
5046       __IM unsigned int RESERVED2 : 16;     /*!< [31..16] Reserved for future use */
5047     } SIO_SHIFT_COUNT_PRELOAD_REG_b[16];
5048   };
5049 
5050   union {
5051     __IOM unsigned int SIO_DATA_POS_COUNT_REG[16]; /*!< (@ 0x000000E8) Data Position
5052                                                   Counter Register */
5053 
5054     struct {
5055       __IOM unsigned int RELOAD_VALUE : 8;     /*!< [7..0] No. of shifts to happen before reloading
5056                                the shift register with data/ pausing the
5057                                operation */
5058       __IOM unsigned int POSITION_COUNTER : 8; /*!< [15..8] The position counter can
5059                                               be loaded via AHB */
5060       __IM unsigned int RESERVED3 : 16;        /*!< [31..16] Reserved for future use */
5061     } SIO_DATA_POS_COUNT_REG_b[16];
5062   };
5063 
5064   union {
5065     __IOM unsigned int SIO_CONFIG_REG[16]; /*!< (@ 0x00000128) Configuration Register */
5066 
5067     struct {
5068       __IOM unsigned int FULL_ENABLE : 1;                  /*!< [0..0] When set, fifo full indication would be
5069                               asserted when internal buffer is full */
5070       __IOM unsigned int EMPTY_ENABLE : 1;                 /*!< [1..1] When set, fifo full indication would be
5071                                asserted when internal buffer is empty */
5072       __IOM unsigned int EDGE_SEL : 1;                     /*!< [2..2] edge selection */
5073       __IOM unsigned int CLK_SEL : 1;                      /*!< [3..3] clock selection  */
5074       __IOM unsigned int IGNORE_FIRST_SHIFT_CONDITION : 1; /*!< [4..4] data shift
5075                                                           condition */
5076       __IOM unsigned int FLOW_CONTROL_ENABLED : 1;         /*!< [5..5] flow control */
5077       __IOM unsigned int PATTERN_MATCH_ENABLE : 1;         /*!< [6..6] pattern match */
5078       __IOM unsigned int QUALIFIER_MODE : 1;               /*!< [7..7] qualifier mode       */
5079       __IOM unsigned int QUALIFY_CLOCK : 1;                /*!< [8..8] qualify clock        */
5080       __IOM unsigned int INVERT_CLOCK : 1;                 /*!< [9..9] invert clock         */
5081       __IOM unsigned int PARALLEL_MODE : 2;                /*!< [11..10] No. of bits to
5082                                                   shift/capture at valid clk edge        */
5083       __IOM unsigned int PIN_DETECTION_MODE : 2;           /*!< [13..12] Pin mode to be considered for
5084                                      gpio interrupt                     */
5085       __IOM unsigned int SET_CLK_OUT : 1;                  /*!< [14..14] When high sets the sio clock_out port.
5086                               This is used only when sio is not enabled */
5087       __IOM unsigned int RESET_CLK_OUT : 1;                /*!< [15..15] When high resets the sio
5088                                            clock_out port. This is used only
5089                                            when sio is not enabled */
5090       __IOM unsigned int LOAD_DATA_POS_CNTR_VIA_APB : 1;   /*!< [16..16] When set, data position
5091                                              counter can be loaded via APB */
5092       __IM unsigned int RESERVED1 : 15;                    /*!< [31..17] Reserved for future use */
5093     } SIO_CONFIG_REG_b[16];
5094   };
5095 
5096   union {
5097     __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_0; /*!< (@ 0x00000168) Pattern Match
5098                                                Mask Register 0 */
5099 
5100     struct {
5101       __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower
5102                                                       16 bits */
5103     } SIO_PATTERN_MATCH_MASK_REG_SLICE_0_b;
5104   };
5105 
5106   union {
5107     __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_1; /*!< (@ 0x0000016C) Pattern Match
5108                                                Mask Register Slice 1 */
5109 
5110     struct {
5111       __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower
5112                                                       16 bits */
5113     } SIO_PATTERN_MATCH_MASK_REG_SLICE_1_b;
5114   };
5115 
5116   union {
5117     __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_2; /*!< (@ 0x00000170) Pattern Match
5118                                                Mask Register Slice 2 */
5119 
5120     struct {
5121       __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower
5122                                                       16 bits */
5123     } SIO_PATTERN_MATCH_MASK_REG_SLICE_2_b;
5124   };
5125   __IM unsigned int RESERVED[5];
5126 
5127   union {
5128     __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_8; /*!< (@ 0x00000188) Pattern Match
5129                                                Mask Register Slice 8 */
5130 
5131     struct {
5132       __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower
5133                                                       16 bits */
5134     } SIO_PATTERN_MATCH_MASK_REG_SLICE_8_b;
5135   };
5136 
5137   union {
5138     __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_9; /*!< (@ 0x0000018C) Pattern Match
5139                                                Mask Register Slice 9 */
5140 
5141     struct {
5142       __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower
5143                                                       16 bits */
5144     } SIO_PATTERN_MATCH_MASK_REG_SLICE_9_b;
5145   };
5146 
5147   union {
5148     __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_10; /*!< (@ 0x00000190) Pattern Match
5149                                                 Mask Register Slice 10 */
5150 
5151     struct {
5152       __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower
5153                                                       16 bits */
5154     } SIO_PATTERN_MATCH_MASK_REG_SLICE_10_b;
5155   };
5156   __IM unsigned int RESERVED1[5];
5157 
5158   union {
5159     __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_0; /*!< (@ 0x000001A8) Pattern Match Mask
5160                                           Register Slice 0 */
5161 
5162     struct {
5163       __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern
5164                                               to be detected */
5165     } SIO_PATTERN_MATCH_REG_SLICE_0_b;
5166   };
5167 
5168   union {
5169     __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_1; /*!< (@ 0x000001AC) Pattern Match Mask
5170                                           Register Slice 1 */
5171 
5172     struct {
5173       __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern
5174                                               to be detected */
5175     } SIO_PATTERN_MATCH_REG_SLICE_1_b;
5176   };
5177 
5178   union {
5179     __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_2; /*!< (@ 0x000001B0) Pattern Match Mask
5180                                           Register Slice 2 */
5181 
5182     struct {
5183       __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern
5184                                               to be detected */
5185     } SIO_PATTERN_MATCH_REG_SLICE_2_b;
5186   };
5187   __IM unsigned int RESERVED2[5];
5188 
5189   union {
5190     __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_8; /*!< (@ 0x000001C8) Pattern Match Mask
5191                                           Register Slice 8 */
5192 
5193     struct {
5194       __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern
5195                                               to be detected */
5196     } SIO_PATTERN_MATCH_REG_SLICE_8_b;
5197   };
5198 
5199   union {
5200     __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_9; /*!< (@ 0x000001CC) Pattern Match Mask
5201                                           Register Slice 9 */
5202 
5203     struct {
5204       __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern
5205                                               to be detected */
5206     } SIO_PATTERN_MATCH_REG_SLICE_9_b;
5207   };
5208 
5209   union {
5210     __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_10; /*!< (@ 0x000001D0) Pattern Match Mask
5211                                            Register Slice 10 */
5212 
5213     struct {
5214       __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern
5215                                               to be detected */
5216     } SIO_PATTERN_MATCH_REG_SLICE_10_b;
5217   };
5218   __IM unsigned int RESERVED3[7];
5219 
5220   union {
5221     __IOM unsigned int SIO_SHIFT_INTR_EN_SET_REG; /*!< (@ 0x000001F0) Shift Interrupt Enable
5222                                       Set Register                        */
5223 
5224     struct {
5225       __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt enable set
5226                                    register for all SIOs           */
5227       __IM unsigned int RESERVED3 : 16;        /*!< [31..16] Reserved for future use */
5228     } SIO_SHIFT_INTR_EN_SET_REG_b;
5229   };
5230 
5231   union {
5232     __OM unsigned int SIO_SHIFT_INTR_EN_CLEAR_REG; /*!< (@ 0x000001F4) Shift Interrupt Enable
5233                                         Clear Register                      */
5234 
5235     struct {
5236       __OM unsigned int INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common shift interrupt enable
5237                                        Clear register for all   SIOs   */
5238       __OM unsigned int RESERVED3 : 16;         /*!< [31..16] Reserved for future use */
5239     } SIO_SHIFT_INTR_EN_CLEAR_REG_b;
5240   };
5241 
5242   union {
5243     __IOM unsigned int SIO_SHIFT_INTR_MASK_SET_REG; /*!< (@ 0x000001F8) Shift Interrupt Mask
5244                                         Set Register                          */
5245 
5246     struct {
5247       __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common shift interrupt enable Set
5248                                  register for all SIOs           */
5249       __IM unsigned int RESERVED1 : 16;      /*!< [31..16] Reserved for future use */
5250     } SIO_SHIFT_INTR_MASK_SET_REG_b;
5251   };
5252 
5253   union {
5254     __OM unsigned int SIO_SHIFT_INTR_MASK_CLEAR_REG; /*!< (@ 0x000001FC) Shift Interrupt Mask
5255                                           Clear Register */
5256 
5257     struct {
5258       __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common shift interrupt mask clear
5259                                    register for all SIOs           */
5260       __OM unsigned int RESERVED1 : 16;       /*!< [31..16] Reserved for future use */
5261     } SIO_SHIFT_INTR_MASK_CLEAR_REG_b;
5262   };
5263 
5264   union {
5265     __IOM unsigned int SIO_SHIFT_INTR_STATUS_REG; /*!< (@ 0x00000200) Shift
5266                                                  Interrupt Status Register */
5267 
5268     struct {
5269       __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt mask clear
5270                                    register for all SIOs           */
5271       __IM unsigned int RESERVED1 : 16;        /*!< [31..16] Reserved for future use */
5272     } SIO_SHIFT_INTR_STATUS_REG_b;
5273   };
5274 
5275   union {
5276     __IOM unsigned int SIO_SWAP_INTR_EN_SET_REG; /*!< (@ 0x00000204) Swap Interrupt
5277                                                 Enable Set Register */
5278 
5279     struct {
5280       __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Swap interrupt enable
5281                                               set register for all SIOs */
5282       __IM unsigned int RESERVED1 : 16;        /*!< [31..16] Reserved for future use */
5283     } SIO_SWAP_INTR_EN_SET_REG_b;
5284   };
5285 
5286   union {
5287     __OM unsigned int SIO_SWAP_INTR_EN_CLEAR_REG; /*!< (@ 0x00000208) Swap Interrupt
5288                                                  Enable Clear Register */
5289 
5290     struct {
5291       __OM unsigned int INTR_ENABLE_CLEAR : 16; /*!< [15..0] Swap interrupt enable
5292                                                Clear register for all SIOs */
5293       __OM unsigned int RESERVED1 : 16;         /*!< [31..16] Reserved for future use */
5294     } SIO_SWAP_INTR_EN_CLEAR_REG_b;
5295   };
5296 
5297   union {
5298     __IOM unsigned int SIO_SWAP_INTR_MASK_SET_REG; /*!< (@ 0x0000020C) Swap Interrupt Mask Set
5299                                        Register                           */
5300 
5301     struct {
5302       __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common swap interrupt mask
5303                                             set register for all SIOs */
5304       __IM unsigned int RESERVED1 : 16;      /*!< [31..16] Reserved for future use */
5305     } SIO_SWAP_INTR_MASK_SET_REG_b;
5306   };
5307 
5308   union {
5309     __OM unsigned int SIO_SWAP_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000210) Swap Interrupt Mask
5310                                          Clear Register */
5311 
5312     struct {
5313       __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common swap interrupt mask Clear
5314                                    register for all SIOs            */
5315       __OM unsigned int RESERVED1 : 16;       /*!< [31..16] Reserved for future use */
5316     } SIO_SWAP_INTR_MASK_CLEAR_REG_b;
5317   };
5318 
5319   union {
5320     __IOM unsigned int SIO_SWAP_INTR_STATUS_REG; /*!< (@ 0x00000214) Swap Interrupt
5321                                                 Statusr Register */
5322 
5323     struct {
5324       __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common swap interrupt
5325                                               status register for all SIOs */
5326       __IM unsigned int RESERVED1 : 16;        /*!< [31..16] Reserved for future use */
5327     } SIO_SWAP_INTR_STATUS_REG_b;
5328   };
5329 
5330   union {
5331     __IOM unsigned int SIO_PATTERN_MATCH_INTR_EN_SET_REG; /*!< (@ 0x00000218) Pattern Match
5332                                               Interrupt Enable Set Register */
5333 
5334     struct {
5335       __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common pattern or buffer under run
5336                                    interrupt enable set register for all SIOs.
5337                                    Each bit corresponds to one SIO */
5338       __IM unsigned int RESERVED1 : 16;        /*!< [31..16] Reserved for future use */
5339     } SIO_PATTERN_MATCH_INTR_EN_SET_REG_b;
5340   };
5341 
5342   union {
5343     __OM unsigned int SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG; /*!< (@ 0x0000021C) Pattern Match
5344                                                 Interrupt Enable Clear Register
5345                                               */
5346 
5347     struct {
5348       __OM unsigned int INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common pattern or buffer under
5349                                        run interrupt enable
5350                                              clear register for all SIOs   */
5351       __OM unsigned int RESERVED1 : 16;         /*!< [31..16] Reserved for future use */
5352     } SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG_b;
5353   };
5354 
5355   union {
5356     __IOM unsigned int SIO_PATTERN_MATCH_INTR_MASK_SET_REG; /*!< (@ 0x00000220) Pattern Match
5357                                                 Interrupt Mask Set Register */
5358 
5359     struct {
5360       __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common pattern or buffer under run
5361                                  interrupt mask set register for all SIOs */
5362       __IM unsigned int RESERVED1 : 16;      /*!< [31..16] Reserved for future use */
5363     } SIO_PATTERN_MATCH_INTR_MASK_SET_REG_b;
5364   };
5365 
5366   union {
5367     __OM unsigned int SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000224) Pattern Match
5368                                                   Interrupt Mask Clear Register
5369                                                 */
5370 
5371     struct {
5372       __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common pattern or buffer
5373                                              under run interrupt mask clear
5374                                                      register for all SIOs */
5375       __OM unsigned int RESERVED1 : 16;       /*!< [31..16] Reserved for future use */
5376     } SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG_b;
5377   };
5378 
5379   union {
5380     __IOM unsigned int SIO_PATTERN_MATCH_INTR_STATUS_REG; /*!< (@ 0x00000228) Pattern Match
5381                                               Interrupt Status Register */
5382 
5383     struct {
5384       __IOM unsigned int INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt
5385                                           status register for all SIOs */
5386       __IM unsigned int RESERVED3 : 16;    /*!< [31..16] Reserved for future use    */
5387     } SIO_PATTERN_MATCH_INTR_STATUS_REG_b;
5388   };
5389 
5390   union {
5391     __IOM unsigned int SIO_BUFFER_INTR_STATUS_REG; /*!< (@ 0x0000022C) Buffer
5392                                                   Interrupt Status Register */
5393 
5394     struct {
5395       __IOM unsigned int INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt
5396                                           status register for all SIOs */
5397       __IM unsigned int RESERVED1 : 16;    /*!< [31..16] Reserved for future use    */
5398     } SIO_BUFFER_INTR_STATUS_REG_b;
5399   };
5400 
5401   union {
5402     __IOM unsigned int SIO_OUT_MUX_REG[16]; /*!< (@ 0x00000230) Output muxing Register */
5403 
5404     struct {
5405       __IOM unsigned int DOUT_OEN_SEL : 3; /*!< [2..0] OEN select for GPIO pin 0 */
5406       __IOM unsigned int DOUT_SEL : 3;     /*!< [5..3] Output mux select for GPIO pin 0 */
5407       __IM unsigned int RESERVED1 : 26;    /*!< [31..6] Reserved for future use */
5408     } SIO_OUT_MUX_REG_b[16];
5409   };
5410 
5411   union {
5412     __IOM unsigned int SIO_INPUT_MUX_REG[16]; /*!< (@ 0x00000270) Input muxing Register */
5413 
5414     struct {
5415       __IOM unsigned int CLK_SEL : 3;          /*!< [2..0] Input clock select for SIO 0 */
5416       __IOM unsigned int QUALIFIER_SELECT : 2; /*!< [4..3] qualifier select */
5417       __IOM unsigned int QUALIFIER_MODE : 2;   /*!< [6..5] qualifier mode   */
5418       __IOM unsigned int DIN_SEL : 3;          /*!< [9..7] Data in mux select          */
5419       __IM unsigned int RESERVED1 : 22;        /*!< [31..10] Reserved for future use */
5420     } SIO_INPUT_MUX_REG_b[16];
5421   };
5422 
5423   union {
5424     __IOM unsigned int SIO_FIFO_WR_RD_REG; /*!< (@ 0x000002B0) FIFO READ/WRITE Register */
5425 
5426     struct {
5427       __IOM unsigned int FIFO_DATA_REGISTER : 32; /*!< [31..0] Writes and read into
5428                                                  this register will be written
5429                                                  into SIO buffer register */
5430     } SIO_FIFO_WR_RD_REG_b;
5431   };
5432 
5433   union {
5434     __IOM unsigned int SIO_FIFO_WR_OFFSET_START_REG; /*!< (@ 0x000002B4) Points to start slice
5435                                          number forming the FIFO              */
5436 
5437     struct {
5438       __IOM unsigned int SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number
5439                                           forming the FIFO,On write,
5440                                           FIFO_WR_OFFSET_CNT_REG  will also be
5441                                           reset to the value pointed written
5442                                           into this register */
5443     } SIO_FIFO_WR_OFFSET_START_REG_b;
5444   };
5445 
5446   union {
5447     __IOM unsigned int SIO_FIFO_WR_OFFSET_END_REG; /*!< (@ 0x000002B8) SIO last slice no
5448                                        indication Register */
5449 
5450     struct {
5451       __IOM unsigned int SIO_END_SLICE_NUMBER : 32; /*!< [31..0] points to last
5452                                                    slice no forming fifo */
5453     } SIO_FIFO_WR_OFFSET_END_REG_b;
5454   };
5455 
5456   union {
5457     __IOM unsigned int SIO_FIFO_WR_OFFSET_CNT_REG; /*!< (@ 0x000002BC) Points to current slice
5458                                        number forming the FIFO            */
5459 
5460     struct {
5461       __IOM unsigned int SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will
5462                                           happen to buffer in the slice
5463                                           pointed by this register */
5464     } SIO_FIFO_WR_OFFSET_CNT_REG_b;
5465   };
5466 
5467   union {
5468     __IOM unsigned int SIO_FIFO_RD_OFFSET_START_REG; /*!< (@ 0x000002C0) Points to start slice
5469                                          number forming the FIFO              */
5470 
5471     struct {
5472       __IOM unsigned int SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number
5473                                           forming the FIFO                    */
5474     } SIO_FIFO_RD_OFFSET_START_REG_b;
5475   };
5476 
5477   union {
5478     __IOM unsigned int SIO_FIFO_RD_OFFSET_END_REG; /*!< (@ 0x000002C4) Points to last slice
5479                                        number forming the FIFO               */
5480 
5481     struct {
5482       __IOM unsigned int SIO_END_SLICE_NUMBER : 32; /*!< [31..0] Points to last slice number
5483                                         forming the FIFO                      */
5484     } SIO_FIFO_RD_OFFSET_END_REG_b;
5485   };
5486 
5487   union {
5488     __IOM unsigned int SIO_FIFO_RD_OFFSET_CNT_REG; /*!< (@ 0x000002C8) Points to start current
5489                                        number forming the FIFO            */
5490 
5491     struct {
5492       __IOM unsigned int SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will
5493                                           happen to buffer in the slice pointed
5494                                           by this register This register has to
5495                                           be set to zero before starting fresh
5496                                           DMA operation */
5497     } SIO_FIFO_RD_OFFSET_CNT_REG_b;
5498   };
5499 } SIO_Type; /*!< Size = 716 (0x2cc) */
5500 
5501 /* ===========================================================================================================================
5502  */
5503 /* ================                                           QSPI
5504  * ================ */
5505 /* ===========================================================================================================================
5506  */
5507 
5508 /**
5509  * @brief The queued serial peripheral interface module provides a serial
5510  * peripheral interface with queued transfer capability (QSPI)
5511  */
5512 
5513 typedef struct { /*!< (@ 0x12000000) QSPI Structure */
5514 
5515   union {
5516     __IOM unsigned int QSPI_CLK_CONFIG; /*!< (@ 0x00000000) QSPI Clock Configuration
5517                                        Register                          */
5518 
5519     struct {
5520       __IOM unsigned int QSPI_AUTO_CSN_HIGH_CNT : 5;    /*!< [4..0] Minimum SOC clock cycles,
5521                                          during which QSPI auto csn should be
5522                                          high between consecutive CSN assertions
5523                                        */
5524       __IOM unsigned int QSPI_CLK_SYNC : 1;             /*!< [5..5] If the clock frequency to
5525                                          FLASH(spi_clk) and QSPI(hclk)          controller is
5526                                          same,  this bit can be set to one to by-pass
5527                                           the syncros results in time consumption          */
5528       __IOM unsigned int RESERVED1 : 2;                 /*!< [7..6] reserved1   */
5529       __IOM unsigned int QSPI_CLK_EN : 1;               /*!< [8..8] QSPI clock enable */
5530       __IOM unsigned int RESERVED2 : 3;                 /*!< [11..9] reserved2   */
5531       __IOM unsigned int SPI_CLK_DELAY_VAL : 6;         /*!< [17..12] Delay value programmed to RX QSPI
5532                                     DLL on read side. This delay is used to
5533                                     delay the pad clock/DQS according to the
5534                                     requirement */
5535       __IOM unsigned int OCTA_MODE_ENABLE_WITH_DQS : 1; /*!< [18..18] Enables SPI octa mode
5536                                             along with DQS in DDR mode */
5537       __IOM unsigned int QSPI_DLL_ENABLE : 1;           /*!< [19..19] Enable for RX QSPI DLL in read
5538                                   mode.This is used in M4SS QSPI DDR pads to
5539                                   delay the pad clock DQS input */
5540       __IOM unsigned int DDR_CLK_POLARITY_FROM_REG : 1; /*!< [20..20] Used this bit to sample
5541                                           the data at posedge negedge after
5542                                           interface FFs with internal qspi clock
5543                                           0-Sample at negedge 1-Sample at
5544                                           posedge */
5545       __IOM unsigned int QSPI_DLL_ENABLE_TX : 1;        /*!< [21..21] Enable for TX QSPI DLL in write
5546                                    path. This is used in M4SS QSPI DDR pads to
5547                                    delay the qspi clock output. 0–DLL is
5548                                    disabled bypassed 1–DLL is enabled */
5549       __IOM unsigned int SPI_CLK_DELAY_VAL_TX : 6;      /*!< [27..22] Delay value programmed to TX
5550                                      QSPI DLL in write path. This delay is used
5551                                      to delay the qspi clock output according
5552                                      to the requirement */
5553       __IOM unsigned int QSPI_RX_DQS_DLL_CALIB : 1;     /*!< [28..28] Delay value programmed to TX
5554                                       QSPI DLL in write path. This delay is used
5555                                       to delay the qspi clock output according
5556                                       to the requirement */
5557       __IOM unsigned int RESERVED3 : 3;                 /*!< [31..29] reserved3  */
5558     } QSPI_CLK_CONFIG_b;
5559   };
5560 
5561   union {
5562     __IOM unsigned int QSPI_BUS_MODE; /*!< (@ 0x00000004) QSPI Bus Mode Register */
5563 
5564     struct {
5565       __IOM unsigned int QSPI_9116_FEATURE_EN : 1;               /*!< [0..0] 9115 specific features are
5566                                        enabled with this enable */
5567       __IOM unsigned int QSPI_MAN_MODE_CONF_CSN0 : 2;            /*!< [2..1] Configures the QSPI flash for
5568                                           Single/Dual/Quad mode operation in
5569                                           manual mode */
5570       __IOM unsigned int AUTO_MODE_RESET : 1;                    /*!< [3..3] QSPI Auto controller reset. This is
5571                                   not a Self clearing bit */
5572       __IOM unsigned int QSPI_PREFETCH_EN : 1;                   /*!< [4..4] Pre-fetch of data from the model
5573                                    which is connected to QSPI, automatically
5574                                    with out reading on AHB and is supplied to
5575                                    AHB,  when address is matched with AHB read
5576                                    transaction address */
5577       __IOM unsigned int QSPI_WRAP_EN : 1;                       /*!< [5..5] Model wrap is considered with this bit
5578                                and uses wrap instruction to read from FLASH */
5579       __IOM unsigned int QSPI_AUTO_MODE_FRM_REG : 1;             /*!< [6..6] QSPI Mode of Operation */
5580       __IOM unsigned int PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN : 1; /*!< [7..7] Programmable auto
5581                                                      csn mode enable */
5582       __IOM unsigned int QSPI_D2_OEN_CSN0 : 1;                   /*!< [8..8] Direction Control for SPI_IO2 in
5583                                    case of dual/single mode for chip select0
5584                                    csn0. It is used both in Auto and
5585                                      Manual Mode */
5586       __IOM unsigned int QSPI_D3_OEN_CSN0 : 1;                   /*!< [9..9] Direction Control for SPI_IO3 in
5587                                    case of dual/single mode for chip select0
5588                                    csn0. It is used both in Auto and Manual
5589                                    Mode. */
5590       __IOM unsigned int QSPI_D2_DATA_CSN0 : 1;                  /*!< [10..10] Value of SPI_IO2 in case of
5591                                     dual/single mode for chip select0 csn0. It
5592                                     is used both in Auto and Manual Mode. */
5593       __IOM unsigned int QSPI_D3_DATA_CSN0 : 1;                  /*!< [11..11] Value of SPI_IO3 in case of
5594                                     dual/single mode for chip select0 csn0. It
5595                                     is used both in Auto and Manual Mode */
5596       __IOM unsigned int QSPI_D2_OEN_CSN1 : 1;                   /*!< [12..12] Direction Control for
5597                                                SPI_IO2 in case of dual/single
5598                                                  mode for chip select1 csn1  */
5599       __IOM unsigned int QSPI_D3_OEN_CSN1 : 1;                   /*!< [13..13] Direction Control for
5600                                                SPI_IO3 in case of dual/single
5601                                                  mode for chip select1 csn1  */
5602       __IOM unsigned int QSPI_D2_DATA_CSN1 : 1;                  /*!< [14..14] Direction Control for
5603                                                SPI_IO3 in case of dual/single
5604                                                  mode for chip select1 csn1 */
5605       __IOM unsigned int QSPI_D3_DATA_CSN1 : 1;                  /*!< [15..15] Value of SPI_IO3 in case of
5606                                     dual/single mode for chip select1 csn1 */
5607       __IOM unsigned int QSPI_DATA_SAMPLE_EDGE : 1;              /*!< [16..16] Samples MISO data
5608                                                    on clock edges */
5609       __IOM unsigned int QSPI_CLK_MODE_CSN0 : 1;                 /*!< [17..17] QSPI Clock Mode    */
5610       __IOM unsigned int QSPI_CLK_MODE_CSN1 : 1;                 /*!< [18..18] QSPI Clock Mode    */
5611       __IOM unsigned int QSPI_CLK_MODE_CSN2 : 1;                 /*!< [19..19] QSPI Clock Mode    */
5612       __IOM unsigned int QSPI_CLK_MODE_CSN3 : 1;                 /*!< [20..20] QSPI Clock Mode    */
5613       __IOM unsigned int FLASH_AW_FIFO_LS_EN : 1;                /*!< [21..21] Qspi flash auto write fifo
5614                                       light sleep enable                    */
5615       __IOM unsigned int FLASH_SEC_AES_LS_EN : 1;                /*!< [22..22] Qspi flash auto write fifo
5616                                        light sleep enable                    */
5617       __IOM unsigned int RESERVED1 : 1;                          /*!< [23..23] reserved1 */
5618       __IOM unsigned int QSPI_D2_OEN_CSN2 : 1;                   /*!< [24..24] Direction Control for SPI_IO2 in
5619                                    case of dual/single mode for chip select2
5620                                    csn2 */
5621       __IOM unsigned int QSPI_D3_OEN_CSN2 : 1;                   /*!< [25..25] Direction Control for SPI_IO3 in
5622                                    case of dual/single mode for chip select2
5623                                    csn2 */
5624       __IOM unsigned int QSPI_D2_DATA_CSN2 : 1;                  /*!< [26..26] Value of SPI_IO2 in case of
5625                                     dual/single mode for chip select2 csn2 */
5626       __IOM unsigned int QSPI_D3_DATA_CSN2 : 1;                  /*!< [27..27] Value of SPI_IO3 in case of
5627                                     dual/single mode for chip select2 csn2 */
5628       __IOM unsigned int QSPI_D2_OEN_CSN3 : 1;                   /*!< [28..28] Direction Control for SPI_IO2 in
5629                                    case of dual/single mode for chip select3
5630                                    csn3 */
5631       __IOM unsigned int QSPI_D3_OEN_CSN3 : 1;                   /*!< [29..29] Direction Control for SPI_IO3 in
5632                                    case of dual/single mode for chip select3
5633                                    csn3 */
5634       __IOM unsigned int QSPI_D2_DATA_CSN3 : 1;                  /*!< [30..30] Value of SPI_IO2 in case of
5635                                     dual/single mode for chip select3 csn3 */
5636       __IOM unsigned int QSPI_D3_DATA_CSN3 : 1;                  /*!< [31..31] Value of SPI_IO3 in case of
5637                                     dual/single mode for chip select3 csn3 */
5638     } QSPI_BUS_MODE_b;
5639   };
5640 
5641   union {
5642     __IOM unsigned int QSPI_AUTO_CONFIG_1; /*!< (@ 0x00000008) QSPI Auto Controller
5643                                           Configuration 1 Register */
5644 
5645     struct {
5646       __IOM unsigned int QSPI_EXT_BYTE_MODE_CSN0 : 2;    /*!< [1..0] Mode of operation of QSPI in
5647                                           the extra byte phase */
5648       __IOM unsigned int QSPI_DUMMY_MODE_CSN0 : 2;       /*!< [3..2] Mode of operation of
5649                                                   QSPI in instruction phase */
5650       __IOM unsigned int QSPI_ADDR_MODE_CSN0 : 2;        /*!< [5..4] Mode of operation of
5651                                                   QSPI in instruction phase  */
5652       __IOM unsigned int QSPI_CMD_MODE_CSN0 : 2;         /*!< [7..6] Mode of operation of
5653                                                   QSPI in instruction phase   */
5654       __IOM unsigned int QSPI_DATA_MODE_CSN0 : 2;        /*!< [9..8] Mode of operation of
5655                                                   QSPI in DATA phase  */
5656       __IOM unsigned int QSPI_EXTRA_BYTE_CSN0 : 8;       /*!< [17..10] Value of the extra byte to be
5657                                        transmitted, if the extra byte mode is
5658                                        enabled */
5659       __IOM unsigned int QSPI_EXTRA_BYTE_EN_CSN0 : 2;    /*!< [19..18] Value of the extra byte to
5660                                           be transmitted, if the extra
5661                                           byte mode is enabled */
5662       __IOM unsigned int QSPI_WRAP_SIZE : 2;             /*!< [21..20] Qspi auto wrap size    */
5663       __IOM unsigned int RESERVED1 : 1;                  /*!< [22..22] reserved1         */
5664       __IOM unsigned int QSPI_PG_JUMP_CSN0 : 1;          /*!< [23..23] NONE */
5665       __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [27..24] Specifies the number of
5666                                           dummy bytes 0 to 7 for the selected
5667                                           SPI mode */
5668       __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [31..28] Specifies the number of
5669                                           dummy bytes 0 to 7 for the selected
5670                                           SPI mode in case of wrap instruction
5671                                         */
5672     } QSPI_AUTO_CONFIG_1_b;
5673   };
5674 
5675   union {
5676     __IOM unsigned int QSPI_AUTO_CONFIG_2; /*!< (@ 0x0000000C) QSPI Auto Controller
5677                                           Configuration 2 Register */
5678 
5679     struct {
5680       __IOM unsigned int QSPI_RD_DATA_SWAP_AUTO_CSN0 : 1;         /*!< [0..0] NONE */
5681       __IOM unsigned int QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 : 1; /*!< [1..1] NONE */
5682       __IOM unsigned int QSPI_CONTI_RD_EN_CSN0 : 1;               /*!< [2..2] NONE    */
5683       __IOM unsigned int DUMMY_BYTES_WR_RD_CSN0 : 1;              /*!< [3..3] Dummy bytes to the model to be
5684                                          read or to be write                 */
5685       __IOM unsigned int QSPI_DUMMY_BYTES_JMP_CSN : 4;            /*!< [7..4] Dummy cycles to be selected
5686                                            in case of JUMP */
5687       __IOM unsigned int QSPI_RD_INST_CSN0 : 8;                   /*!< [15..8] Read instruction to be used for
5688                                     the selected SPI modes and when wrap */
5689       __IOM unsigned int QSPI_RD_WRAP_INT_CSN0 : 8;               /*!< [23..16] Read instruction
5690                                                    to be used, when wrap mode is
5691                                                    supported by QSPI flash */
5692       __IOM unsigned int QSPI_PG_JUMP_INST_CSN0 : 8;              /*!< [31..24] Read instruction to be used,
5693                                          when Page jump is to be used */
5694     } QSPI_AUTO_CONFIG_2_b;
5695   };
5696 
5697   union {
5698     __IOM unsigned int QSPI_MANUAL_CONFIG1; /*!< (@ 0x00000010) QSPI Manual
5699                                            Configuration 1 Register */
5700 
5701     struct {
5702       __IOM unsigned int QSPI_MANUAL_CSN : 1;                  /*!< [0..0] SPI CS in manual mode */
5703       __IOM unsigned int QSPI_MANUAL_WR : 1;                   /*!< [1..1] Write enable for manual
5704                                              mode when CS is low  */
5705       __IOM unsigned int QSPI_MANUAL_RD : 1;                   /*!< [2..2] Read enable for manual mode
5706                                             when CS is low */
5707       __IOM unsigned int QSPI_MANUAL_RD_CNT : 10;              /*!< [12..3] Indicates total number of bytes
5708                                       to be read along with 31:27 bits of this
5709                                       register. Maximum length supported is
5710                                           32k bytes */
5711       __IOM unsigned int QSPI_MANUAL_CSN_SELECT : 2;           /*!< [14..13] Indicates which
5712                                                     CSn is valid */
5713       __IOM unsigned int RESERVED1 : 4;                        /*!< [18..15] reserved1              */
5714       __IOM unsigned int QSPI_MANUAL_SIZE_FRM_REG : 2;         /*!< [20..19] Manual reads and manual
5715                                            writes follow this size */
5716       __IOM unsigned int TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [21..21] NONE */
5717       __IOM unsigned int QSPI_FULL_DUPLEX_EN : 1;              /*!< [22..22] Full duplex mode enable.  */
5718       __IOM unsigned int RESERVED2 : 2;                        /*!< [24..23] reserved2 */
5719       __IOM unsigned int HW_CTRLD_QSPI_MODE_CTRL : 1;          /*!< [25..25] Hardware controlled qspi
5720                                           mode in between AUTO and manual */
5721       __IOM unsigned int QSPI_MANUAL_QSPI_MODE : 1;            /*!< [26..26] Internally the priority is
5722                                         given to manual mode                  */
5723       __IOM unsigned int QSPI_MANUAL_RD_CNT1 : 5;              /*!< [31..27] Indicates total
5724                                                  number of bytes or bits */
5725     } QSPI_MANUAL_CONFIG1_b;
5726   };
5727 
5728   union {
5729     __IOM unsigned int QSPI_MANUAL_CONFIG2; /*!< (@ 0x00000014) QSPI Manual
5730                                            Configuration 2 Register */
5731 
5732     struct {
5733       __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN0 : 1;          /*!< [0..0] Swap the write data inside
5734                                              the QSPI controller it-self */
5735       __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN1 : 1;          /*!< [1..1] Swap the write data inside
5736                                              the QSPI controller it-self. */
5737       __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN2 : 1;          /*!< [2..2] Swap the write data inside
5738                                              the QSPI controller itself. */
5739       __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN3 : 1;          /*!< [3..3] Swap the write data inside
5740                                              the QSPI controller itself. */
5741       __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN0 : 1;          /*!< [4..4] Swap the read data inside
5742                                              the QSPIcontroller it self. */
5743       __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN1 : 1;          /*!< [5..5] Swap the read data inside
5744                                              the QSPIcontroller itself. */
5745       __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN2 : 1;          /*!< [6..6] Swap the read data inside
5746                                              the QSPIcontroller it-self */
5747       __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN3 : 1;          /*!< [7..7] Swap the read data inside
5748                                              the QSPIcontroller itself */
5749       __IOM unsigned int QSPI_MAN_MODE_CONF_CSN1 : 2;             /*!< [9..8] Configures the QSPI flash for
5750                                           Single/Dual/Quad mode operation in
5751                                           manual mode for chip select1 csn1 */
5752       __IOM unsigned int QSPI_MAN_MODE_CONF_CSN2 : 2;             /*!< [11..10] Configures the QSPI flash
5753                                           for Single or Dual or Quad mode
5754                                           operation in manual mode for chip
5755                                           select2 csn2                       */
5756       __IOM unsigned int QSPI_MAN_MODE_CONF_CSN3 : 2;             /*!< [13..12] Configures the QSPI flash
5757                                           for Single or Dual or Quad mode
5758                                           operation in manual mode for chip
5759                                           select3 csn3                       */
5760       __IOM unsigned int LOOP_BACK_EN : 1;                        /*!< [14..14] Internal loop back test mode. */
5761       __IOM unsigned int QSPI_MANUAL_DDR_PHASE : 1;               /*!< [15..15] DDR operations can be
5762                                              performed even in manual mode      */
5763       __IOM unsigned int QSPI_DDR_CLK_EN : 1;                     /*!< [16..16] DDR operations can be
5764                                              performed even in manual mode */
5765       __IOM unsigned int RESERVED1 : 1;                           /*!< [17..17] reserved1       */
5766       __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [18..18] Set this bit
5767                                                       for read data byte
5768                                                       swapping within the word.
5769                                                       It is valid only for octa
5770                                                       ddr mode. It is valid
5771                                                        for csn0. */
5772       __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [19..19] Set this bit
5773                                                       for read data byte
5774                                                       swapping within the word.
5775                                                       It is valid only for octa
5776                                                       ddr mode. It is valid
5777                                                        for csn1. */
5778       __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [20..20] Set this bit
5779                                                       for read data byte
5780                                                       swapping within the word.
5781                                                       It is valid only for octa
5782                                                       ddr mode. It is valid
5783                                                        for csn2. */
5784       __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [21..21] Set this bit
5785                                                       for write data byte
5786                                                       swapping within the word.
5787                                                       It is valid only for octa
5788                                                       ddr mode. It is valid
5789                                                        for csn0. */
5790       __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [22..22] Set this bit
5791                                                       for write data byte
5792                                                       swapping within the word.
5793                                                       It is valid only for octa
5794                                                       ddr mode. It is valid
5795                                                        for csn1. */
5796       __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [23..23] Set this bit
5797                                                       for write data byte
5798                                                       swapping within the word.
5799                                                       It is valid only for octa
5800                                                       ddr mode. It is valid
5801                                                        for csn2. */
5802       __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 : 1; /*!< [24..24] Set this bit
5803                                                       for write data byte
5804                                                       swapping within the word.
5805                                                       It is valid only for octa
5806                                                       ddr mode. It is valid
5807                                                        for csn3. */
5808       __IOM unsigned int QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE : 1;  /*!< [25..25] Indicates
5809                                                      qspi_manual_rd_cnt values
5810                                                      are dummy bytes
5811                                                        or bits in manual mode.
5812                                                    */
5813       __IOM unsigned int RESERVED2 : 6;                           /*!< [31..26] reserved2               */
5814     } QSPI_MANUAL_CONFIG2_b;
5815   };
5816   __IM unsigned int RESERVED;
5817 
5818   union {
5819     __IOM unsigned int QSPI_FIFO_THRLD; /*!< (@ 0x0000001C) QSPI FIFO Threshold Register */
5820 
5821     struct {
5822       __IOM unsigned int FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */
5823       __IOM unsigned int FIFO_AFULL_THRLD : 4;  /*!< [7..4] FIFO almost full threshold       */
5824       __IOM unsigned int WFIFO_RESET : 1;       /*!< [8..8] Write fifo reset */
5825       __IOM unsigned int RFIFO_RESET : 1;       /*!< [9..9] Read fifo reset */
5826       __IOM unsigned int RESERVED1 : 22;        /*!< [31..10] reserved1  */
5827     } QSPI_FIFO_THRLD_b;
5828   };
5829 
5830   union {
5831     __IM unsigned int QSPI_MANUAL_STATUS; /*!< (@ 0x00000020) QSPI Manual Status Register */
5832 
5833     struct {
5834       __IM unsigned int QSPI_BUSY : 1;                   /*!< [0..0] State of Manual mode.          */
5835       __IM unsigned int FIFO_FULL_WFIFO_S : 1;           /*!< [1..1] Status indication for
5836                                                Wfifo in manual mode  */
5837       __IM unsigned int FIFO_AFULL_WFIFO_S : 1;          /*!< [2..2] Status indication for
5838                                                Wfifo in manual mode */
5839       __IM unsigned int FIFO_EMPTY_WFIFO : 1;            /*!< [3..3] Status indication for
5840                                                Wfifo in manual mode   */
5841       __IM unsigned int FIFO_AEMPTY_WFIFO : 1;           /*!< [4..4] Status indication for
5842                                                Wfifo in manual mode  */
5843       __IM unsigned int FIFO_FULL_RFIFO : 1;             /*!< [5..5] Status indication for Rfifo
5844                                             in manual mode */
5845       __IM unsigned int FIFO_AFULL_RFIFO : 1;            /*!< [6..6] Status indication for
5846                                                 Rfifo in manual mode    */
5847       __IM unsigned int FIFO_EMPTY_RFIFO_S : 1;          /*!< [7..7] Status indication for
5848                                                 Rfifo in manual mode  */
5849       __IM unsigned int FIFO_AEMPTY_RFIFO_S : 1;         /*!< [8..8] Status indication for
5850                                                 Rfifo in manual mode */
5851       __IM unsigned int GSPI_MANUAL_RD_CNT : 1;          /*!< [9..9] This is a result of 10
5852                                                 bits ORing counter  */
5853       __IM unsigned int AUTO_MODE_FSM_IDLE_SCLK : 1;     /*!< [10..10] Auto mode idle signal to
5854                                           track auto controller is busy
5855                                            or idle. */
5856       __IM unsigned int QSPI_AUTO_MODE : 1;              /*!< [11..11] QSPI controller status. */
5857       __IM unsigned int QSPI_AUTO_MODE_FRM_REG_SCLK : 1; /*!< [12..12] QSPI auto mode status.
5858                                                Valid only when
5859                                                HW_CTRLD_QSPI_MODE_CTRL  is zero.
5860                                              */
5861       __IM unsigned int HW_CTRLD_MODE_SCLK : 1;          /*!< [13..13] QSPI mode status in
5862                                                HW_CTRLD_MODE */
5863       __IM unsigned int HW_CTRLD_MODE_CTRL_SCLK : 1;     /*!< [14..14] HW_CTRLD_MODE status */
5864       __IM unsigned int AW_CTRL_BUSY : 1;                /*!< [15..15] Auto write busy indication.         */
5865       __IM unsigned int RESERVED1 : 16;                  /*!< [31..16] reserved1 */
5866     } QSPI_MANUAL_STATUS_b;
5867   };
5868 
5869   union {
5870     __IOM unsigned int QSPI_INTR_MASK; /*!< (@ 0x00000024) QSPI Interrupt Mask Register */
5871 
5872     struct {
5873       __IOM unsigned int QSPI_INTR_MASK : 1;                    /*!< [0..0] Interrupt Status bit */
5874       __IOM unsigned int FIFO_AEMPTY_RFIFO_MASK : 1;            /*!< [1..1] NONE */
5875       __IOM unsigned int FIFO_AFULL_RFIFO_MASK : 1;             /*!< [2..2] NONE  */
5876       __IOM unsigned int FIFO_AEMPTY_WFIFO_MASK : 1;            /*!< [3..3] NONE */
5877       __IOM unsigned int FIFO_AFULL_WFIFO_MASK : 1;             /*!< [4..4] NONE  */
5878       __IOM unsigned int FIFO_FULL_WFIFO_MASK : 1;              /*!< [5..5] NONE   */
5879       __IOM unsigned int FIFO_EMPTY_RFIFO_MASK : 1;             /*!< [6..6] NONE  */
5880       __IOM unsigned int AHB_AUTO_WRITE_INTR_MASK : 1;          /*!< [7..7] Rising interrupt for any
5881                                           auto write operation on AHB
5882                                           bus. This bit is a mask for this
5883                                           interrupt */
5884       __IOM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK : 1; /*!< [8..8] Rising interrupt
5885                                                     when no csn is selected
5886                                                     using programmable
5887                                                        auto base address. This
5888                                                     bit is a mask for this
5889                                                     interrupt. */
5890       __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_MASK : 1;   /*!< [9..9] Rising interrupt when
5891                                                   M4 QSPI tries to do manual
5892                                                   mode transactions in Common
5893                                                   flash mode (3).  This bit is a
5894                                                   mask for this interrupt. */
5895       __IOM unsigned int M4_AUTO_READ_OUT_range_intr_mask : 1;  /*!< [10..10] Rising interrupt
5896                                                    when M4 QSPI tries to read NWP
5897                                                    locations in Common flash
5898                                                    mode (3).  This bit is a mask
5899                                                    for this interrupt. */
5900       __IOM unsigned int RESERVED1 : 21;                        /*!< [31..11] reserved1            */
5901     } QSPI_INTR_MASK_b;
5902   };
5903 
5904   union {
5905     __IOM unsigned int QSPI_INTR_UNMASK; /*!< (@ 0x00000028) QSPI Interrupt Unmask
5906                                         Register                             */
5907 
5908     struct {
5909       __IOM unsigned int QSPI_INTR_UNMASK : 1;                    /*!< [0..0] Interrupt Status bit */
5910       __IOM unsigned int FIFO_AEMPTY_RFIFO_UN : 1;                /*!< [1..1] NONE     */
5911       __IOM unsigned int FIFO_AFULL_RFIFO_UNMASK : 1;             /*!< [2..2] NONE  */
5912       __IOM unsigned int FIFO_AEMPTY_WFIFO_UNMASK : 1;            /*!< [3..3] NONE */
5913       __IOM unsigned int FIFO_AFULL_WFIFO_UNMASK : 1;             /*!< [4..4] NONE  */
5914       __IOM unsigned int FIFO_FULL_WFIFO_UNMASK : 1;              /*!< [5..5] NONE   */
5915       __IOM unsigned int FIFO_EMPTY_RFIFO_UNMASK : 1;             /*!< [6..6] NONE  */
5916       __IOM unsigned int AHB_AUTO_WRITE_INTR_UNMASK : 1;          /*!< [7..7] Rising interrupt for any
5917                                           auto write operation on AHB
5918                                           bus. This bit is a unmask for this
5919                                           interrupt. */
5920       __IOM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK : 1; /*!< [8..8] Rising interrupt
5921                                                       when M4 QSPI tries to do
5922                                                       manual mode transactions
5923                                                       in Common flash mode (3).
5924                                                       This bit is a unmask for
5925                                                       this interrupt. */
5926       __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_UNMASK : 1;   /*!< [9..9] Rising interrupt
5927                                                     when M4 QSPI tries to do
5928                                                     manual mode transactions in
5929                                                     Common flash mode (3).  This
5930                                                     bit is a unmask for this
5931                                                     interrupt. */
5932       __IOM unsigned int M4_AUTO_READ_OUT_RANGE_INTR_UNMASK : 1;  /*!< [10..10] Rising interrupt
5933                                                      when M4 QSPI tries to read
5934                                                      NWP locations in Common
5935                                                      flash mode (3).  This bit
5936                                                      is a unmask for this
5937                                                        interrupt. */
5938       __IOM unsigned int RESERVED1 : 21;                          /*!< [31..11] reserved1              */
5939     } QSPI_INTR_UNMASK_b;
5940   };
5941 
5942   union {
5943     __IM unsigned int QSPI_INTR_STS; /*!< (@ 0x0000002C) QSPI Interrupt Status Register */
5944 
5945     struct {
5946       __IM unsigned int QSPI_INTR_LVL : 1;                    /*!< [0..0] Interrupt Status bit */
5947       __IM unsigned int FIFO_AEMPTY_RFIFO_LVL : 1;            /*!< [1..1] NONE */
5948       __IM unsigned int FIFO_AFULL_RFIFO_LVL : 1;             /*!< [2..2] NONE  */
5949       __IM unsigned int FIFO_AEMPTY_WFIFO_LVL : 1;            /*!< [3..3] NONE */
5950       __IM unsigned int FIFO_AFULL_WFIFO_LVL : 1;             /*!< [4..4] NONE  */
5951       __IM unsigned int FIFO_FULL_WFIFO_LVL : 1;              /*!< [5..5] NONE   */
5952       __IM unsigned int FIFO_EMPTY_RFIFO_LVL : 1;             /*!< [6..6] NONE  */
5953       __IM unsigned int AHB_AUTO_WRITE_INTR_LEV : 1;          /*!< [7..7] rising interrupt for any auto
5954                                           write operation on AHB bus. */
5955       __IM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL : 1; /*!< [8..8] Rising interrupt
5956                                                    when no csn is selected using
5957                                                    programmable auto base
5958                                                    address. */
5959       __IM unsigned int M4QSPI_MANUAL_BLOCKED_LVL : 1;        /*!< [9..9] Rising interrupt when M4
5960                                            QSPI tries to do manual mode
5961                                            transactions in Common flash mode
5962                                            (3). */
5963       __IM unsigned int M4_AUTO_READ_OUT_RANGE_LVL : 1;       /*!< [10..10] Rising interrupt when M4
5964                                              QSPI tries to read NWP locations
5965                                                        in Common flash mode (3).
5966                                            */
5967       __IM unsigned int RESERVED1 : 21;                       /*!< [31..11] reserved1       */
5968     } QSPI_INTR_STS_b;
5969   };
5970 
5971   union {
5972     __IOM unsigned int QSPI_INTR_ACK; /*!< (@ 0x00000030) QSPI Interrupt Acknowledge
5973                                      Register                        */
5974 
5975     struct {
5976       __OM unsigned int QSPI_INTR_ACK : 1;                    /*!< [0..0] Interrupt Status bit */
5977       __OM unsigned int FIFO_AEMPTY_RFIFO_ACK : 1;            /*!< [1..1] NONE */
5978       __OM unsigned int FIFO_AFULL_RFIFO_ACK : 1;             /*!< [2..2] NONE  */
5979       __OM unsigned int FIFO_AEMPTY_WFIFO_ACK : 1;            /*!< [3..3] NONE */
5980       __OM unsigned int FIFO_AFULL_WFIFO_ACK : 1;             /*!< [4..4] NONE  */
5981       __OM unsigned int FIFO_FULL_WFIFO_ACK : 1;              /*!< [5..5] NONE   */
5982       __OM unsigned int FIFO_EMPTY_RFIFO_ACK : 1;             /*!< [6..6] NONE  */
5983       __OM unsigned int AHB_AUTO_WRITE_INTR_ACK : 1;          /*!< [7..7] Rising interrupt for any auto
5984                                           write operation on AHB bus. This bit
5985                                           is an ack for this interrupt. */
5986       __OM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK : 1; /*!< [8..8] Rising interrupt
5987                                                    when no csn is selected using
5988                                                    programmable auto base
5989                                                    address. This bit is an ack
5990                                                    for this interrupt. */
5991       __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_ACK : 1;  /*!< [9..9] Rising interrupt when
5992                                                  M4 QSPI tries to do manual mode
5993                                                        transactions in Common
5994                                                  flash mode (3).  This bit is an
5995                                                        ack for this interrupt.
5996                                                */
5997       __IOM unsigned int M4_AUTO_READ_OUT_RANGE_INTR_ACK : 1; /*!< [10..10] Rising interrupt
5998                                                   when M4 QSPI tries to read NWP
5999                                                   locations
6000                                                        in Common flash mode (3).
6001                                                   This bit is an ack for this
6002                                                   interrupt.          */
6003       __OM unsigned int RESERVED1 : 21;                       /*!< [31..11] reserved1            */
6004     } QSPI_INTR_ACK_b;
6005   };
6006 
6007   union {
6008     __IM unsigned int QSPI_STS_MC; /*!< (@ 0x00000034) QSPI State Machine Monitor
6009                                   Register                        */
6010 
6011     struct {
6012       __IM unsigned int BUS_CTRL_PSTATE : 4;     /*!< [3..0] Bus controller present state */
6013       __IM unsigned int AUTO_CTRL_PSTATE : 3;    /*!< [6..4] Auto controller present state */
6014       __IM unsigned int QSPI_MASTER_PSTATE : 3;  /*!< [9..7] Qspi master present state */
6015       __IM unsigned int QSPI_MANUAL_RD_CNT : 15; /*!< [24..10] Qspi manual read
6016                                                 counter value */
6017       __IM unsigned int RESERVED1 : 7;           /*!< [31..25] reserved1           */
6018     } QSPI_STS_MC_b;
6019   };
6020 
6021   union {
6022     __IOM unsigned int QSPI_AUTO_CONFIG_1_CSN1; /*!< (@ 0x00000038) QSPI Auto Controller
6023                                     Configuration 1 CSN1 Register         */
6024 
6025     struct {
6026       __IOM unsigned int QSPI_EXT_BYTE_MODE_CSN1 : 2;   /*!< [1..0] Mode of operation of QSPI in
6027                                           instruction phase. */
6028       __IOM unsigned int QSPI_DUMMY_MODE_CSN1 : 2;      /*!< [3..2] Mode of operation of
6029                                                   QSPI in instruction phase */
6030       __IOM unsigned int QSPI_ADDR_MODE_CSN1 : 2;       /*!< [5..4] Mode of operation of
6031                                                   QSPI in instruction phase.  */
6032       __IOM unsigned int QSPI_CMD_MODE_CSN1 : 2;        /*!< [7..6] Mode of operation of
6033                                                   QSPI in instruction phase.   */
6034       __IOM unsigned int QSPI_DATA_MODE_CSN1 : 2;       /*!< [9..8] Mode of operation of
6035                                                   QSPI in DATA phase.  */
6036       __IM unsigned int QSPI_EXTRA_BYTE_CSN1 : 8;       /*!< [17..10] Value of the extra byte to be
6037                                        transmitted, if the extra byte mode is
6038                                        enabled. */
6039       __IOM unsigned int QSPI_EXTRA_BYTE_EN_CSN1 : 2;   /*!< [19..18] Mode of operation of QSPI
6040                                             in DATA phase.   */
6041       __IOM unsigned int QSPI_WRAP_SIZE : 2;            /*!< [21..20] Qspi auto wrap size */
6042       __IOM unsigned int RESERVED1 : 1;                 /*!< [22..22] reserved1      */
6043       __OM unsigned int QSPI_PG_JUMP_CSN1 : 1;          /*!< [23..23] NONE */
6044       __IM unsigned int QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [27..24] Specifies the number of
6045                                            dummy bytes 0 to 7 for the selected
6046                                            SPI mode. */
6047       __IM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [31..28] Specifies the number of
6048                                            dummy bytes 0 to 7 for the selected
6049                                            SPI mode in case of wrap instruction.
6050                                          */
6051     } QSPI_AUTO_CONFIG_1_CSN1_b;
6052   };
6053 
6054   union {
6055     __IOM unsigned int QSPI_AUTO_CONFIG_2_CSN1_REG; /*!< (@ 0x0000003C) QSPI Auto Controller
6056                                         Configuration 2 CSN1 Register         */
6057 
6058     struct {
6059       __IOM unsigned int QSPI_RD_SWAP_AUTO_CSN1 : 1;             /*!< [0..0] Swap the read data from the
6060                                          flash in byte order for chip select1
6061                                          csn1 in auto mode. */
6062       __IOM unsigned int QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 : 1; /*!< [1..1] NONE */
6063       __IOM unsigned int QSPI_CONTI_RD_EN_CSN1 : 1;              /*!< [2..2] Continuous read
6064                                                      enable bit.   */
6065       __IOM unsigned int DUMMY_BYTES_WR_RD : 1;                  /*!< [3..3] Dummy bytes to the model
6066                                                to be read or to be write. */
6067       __IOM unsigned int QSPI_DUMMY_BYTES_JMP_CSN1 : 4;          /*!< [7..4] Dummy cycles to be selected
6068                                             in case of JUMP */
6069       __IOM unsigned int QSPI_RD_INST_CSN1 : 8;                  /*!< [15..8] Read instruction to be
6070                                                used for the selected SPI modes
6071                                                 and when wrap is not needed or
6072                                                supported */
6073       __IOM unsigned int QSPI_RD_WRAP_INST_CSN1 : 8;             /*!< [23..16] Read instruction to be used
6074                                          for the selected SPI modes and when
6075                                          wrap is not needed or supported */
6076       __IOM unsigned int QSPI_PG_JMP_INST_CSN1 : 8;              /*!< [31..24] Read instruction to be used,
6077                                         when Page jump is to be used. */
6078     } QSPI_AUTO_CONFIG_2_CSN1_REG_b;
6079   };
6080   __IOM unsigned int QSPI_MANUAL_RDWR_FIFO[16]; /*!< (@ 0x00000040) QSPI FIFOs */
6081 
6082   union {
6083     __IOM unsigned int QSPI_MANUAL_WRITE_DATA2; /*!< (@ 0x00000080) QSPI Manual
6084                                                Write Data 2 Register */
6085 
6086     struct {
6087       __IOM unsigned int QSPI_MANUAL_WRITE_DATA2 : 5; /*!< [4..0] Number of bits to be written
6088                                           in write mode */
6089       __IOM unsigned int RESERVED1 : 2;               /*!< [6..5] reserved1    */
6090       __IOM unsigned int USE_PREV_LENGTH : 1;         /*!< [7..7] Use previous length. */
6091       __IOM unsigned int QSPI_CLK_ENABLE_HCLK : 1;    /*!< [8..8] reserved2 */
6092       __IOM unsigned int RESERVED2 : 23;              /*!< [31..9] reserved2           */
6093     } QSPI_MANUAL_WRITE_DATA2_b;
6094   };
6095   __IM unsigned int RESERVED1[3];
6096 
6097   union {
6098     __IOM unsigned int QSPI_AUTO_CONFIG_3_CSN0_REG; /*!< (@ 0x00000090) QSPI Auto Controller
6099                                         Configuration 3 CSN0 Register         */
6100 
6101     struct {
6102       __IOM unsigned int QSPI_DUMMY_BYTE_OR_BIT_CSN0 : 1;          /*!< [0..0] Indicates all above
6103                                           mention values are dummy bytes or
6104                                           bits in auto mode. */
6105       __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN0 : 4;           /*!< [4..1] Specifies the number of
6106                                          dummy bytes for the selected
6107                                          SPI mode. It contains MS nibble for
6108                                          byte. */
6109       __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN0 : 4;           /*!< [8..5] Specifies the number of
6110                                          dummy bytes for the selected SPI mode
6111                                          in case of wrap instruction. It
6112                                          contains MS nibble for byte. */
6113       __IOM unsigned int RESERVED1 : 3;                            /*!< [11..9] reserved1       */
6114       __IOM unsigned int QSPI_DDR_CMD_MODE_CSN0 : 1;               /*!< [12..12] DDR Command mode */
6115       __IOM unsigned int QSPI_DDR_ADDR_MODE_CSN0 : 1;              /*!< [13..13] DDR Address mode */
6116       __IOM unsigned int QSPI_DDR_DUMMY_MODE_CSN0 : 1;             /*!< [14..14] DDR Address mode */
6117       __IOM unsigned int QSPI_DDR_EXTRA_MODE_CSN0 : 1;             /*!< [15..15] DDR Address mode */
6118       __IOM unsigned int QSPI_DDR_DATA_MODE_CSN0 : 1;              /*!< [16..16] DDR Address mode */
6119       __IOM unsigned int QSPI_AUTO_DDR_CMD_MODE_CSN0 : 1;          /*!< [17..17] DDR data mode. */
6120       __IOM unsigned int QSPI_CMD_SIZE_16BIT_CSN0 : 1;             /*!< [18..18] Enable for 16 read cmd
6121                                            size for csn0. */
6122       __IOM unsigned int QSPI_ADR_SIZE_32BIT_AUTO_MODE : 1;        /*!< [19..19] 32 bit addressing
6123                                                 support enable. */
6124       __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 : 1; /*!< [20..20] Rd data swap
6125                                                        at word level in auto
6126                                                        mode for csn0. It is
6127                                                        valid for octa mode. */
6128       __IOM unsigned int RESERVED3 : 3;                            /*!< [23..21] reserved3                 */
6129       __IOM unsigned int QSPI_RD_INST_CSN0_MSB : 8;                /*!< [31..24] Read instruction MS byte to
6130                                         be used the selected SPI
6131                                           modes and when wrap is not needed or
6132                                         supported.                           */
6133     } QSPI_AUTO_CONFIG_3_CSN0_REG_b;
6134   };
6135 
6136   union {
6137     __IOM unsigned int QSPI_AUTO_CONFIG_3_CSN1_REG; /*!< (@ 0x00000094) QSPI Auto Controller
6138                                         Configuration 3 CSN1 Register         */
6139 
6140     struct {
6141       __IOM unsigned int QSPI_DUMMY_BYTE_OR_BIT_CSN1 : 1;          /*!< [0..0] Indicates all above
6142                                           mention values are dummy bytes or
6143                                           bits in auto mode. */
6144       __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN1 : 4;           /*!< [4..1] Specifies the number of
6145                                          dummy bytes for the selected
6146                                          SPI mode. It contains MS nibble for
6147                                          byte. */
6148       __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN1 : 4;           /*!< [8..5] Specifies the number of
6149                                          dummy bytes for the selected SPI mode
6150                                          in case of wrap instruction. It
6151                                          contains MS nibble for byte. */
6152       __IOM unsigned int RESERVED1 : 3;                            /*!< [11..9] reserved1       */
6153       __IOM unsigned int QSPI_DDR_CMD_MODE_CSN1 : 1;               /*!< [12..12] DDR Command mode */
6154       __IOM unsigned int QSPI_DDR_ADDR_MODE_CSN1 : 1;              /*!< [13..13] DDR Address mode */
6155       __IOM unsigned int QSPI_DDR_DUMMY_MODE_CSN1 : 1;             /*!< [14..14] DDR Address mode */
6156       __IOM unsigned int QSPI_DDR_EXTRA_MODE_CSN1 : 1;             /*!< [15..15] DDR Address mode */
6157       __IOM unsigned int QSPI_DDR_DATA_MODE_CSN1 : 1;              /*!< [16..16] DDR Address mode */
6158       __IOM unsigned int QSPI_AUTO_DDR_CMD_MODE_CSN1 : 1;          /*!< [17..17] DDR data mode. */
6159       __IOM unsigned int QSPI_CMD_SIZE_16BIT_CSN1 : 1;             /*!< [18..18] Enable for 16 read cmd
6160                                            size for csn1. */
6161       __IOM unsigned int RESERVED3 : 1;                            /*!< [19..19] RESERVED3     */
6162       __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 : 1; /*!< [20..20] Rd data swap
6163                                                        at word level in auto
6164                                                        mode for csn1. It is
6165                                                        valid for octa mode. */
6166       __IOM unsigned int RESERVED4 : 3;                            /*!< [23..21] reserved4                 */
6167       __IOM unsigned int QSPI_RD_INST_CSN1_MSB : 8;                /*!< [31..24] Read instruction MS byte to
6168                                         be used the selected SPI
6169                                           modes and when wrap is not needed or
6170                                         supported.                           */
6171     } QSPI_AUTO_CONFIG_3_CSN1_REG_b;
6172   };
6173   __IM unsigned int RESERVED2[2];
6174 
6175   union {
6176     __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN0; /*!< (@ 0x000000A0) none */
6177 
6178     struct {
6179       __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN0 : 32; /*!< [31..0] Holds the 32 bit base
6180                                           address for select chip select0 in
6181                                           programmable auto csn mode.  It is
6182                                           valid only programmable
6183                                           auto csn mode is enabled. */
6184     } QSPI_AUTO_BASE_ADDR_CSN0_b;
6185   };
6186 
6187   union {
6188     __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN1; /*!< (@ 0x000000A4) none */
6189 
6190     struct {
6191       __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN1 : 32; /*!< [31..0] Holds the 32 bit base
6192                                           address for select chip select1 in
6193                                           programmable auto csn mode.  It is
6194                                           valid only programmable
6195                                           auto csn mode is enabled. */
6196     } QSPI_AUTO_BASE_ADDR_CSN1_b;
6197   };
6198   __IM unsigned int RESERVED3[2];
6199 
6200   union {
6201     __IOM unsigned int OCTASPI_BUS_CONTROLLER; /*!< (@ 0x000000B0) none */
6202 
6203     struct {
6204       __IOM unsigned int QSPI_D7TOD4_DATA_CSN0 : 4; /*!< [3..0] Value of SPI_IO7,6,5 and 4 in
6205                                         case of quad/dual/single mode for chip
6206                                         select1 (cs_n0). It is used both in Auto
6207                                           and Manual Mode. */
6208       __IOM unsigned int QSPI_D7TOD4_OEN_CSN0 : 4;  /*!< [7..4] Direction Control for SPI_IO
6209                                        7,6,5 and 4 in case of quad/dual/single
6210                                                        mode for chip select0
6211                                        (cs_n0).  It is used both in Auto and
6212                                        Manual Mode. */
6213       __IOM unsigned int QSPI_D7TOD4_DATA_CSN1 : 4; /*!< [11..8] Value of SPI_IO7,6,5 and 4 in
6214                                         case of quad/dual/single mode for chip
6215                                         select1 (cs_n1).  It is used both in
6216                                         Auto and Manual Mode. */
6217       __IOM unsigned int QSPI_D7TOD4_OEN_CSN1 : 4;  /*!< [15..12] Direction Control for SPI_IO
6218                                        7,6,5 and 4 in case of quad/dual/single
6219                                        mode for chip select1 (cs_n1).  It is
6220                                          used both in Auto and Manual Mode. */
6221       __IOM unsigned int QSPI_D7TOD4_DATA_CSN2 : 4; /*!< [19..16] Value of SPI_IO7,6,5 and 4 in
6222                                         case of quad/dual/single mode for chip
6223                                         select2 (cs_n2).  It is used both in
6224                                         Auto and Manual Mode. */
6225       __IOM unsigned int QSPI_D7TOD4_OEN_CSN2 : 4;  /*!< [23..20] Direction Control for SPI_IO
6226                                        7,6,5 and 4 in case of quad/dual/single
6227                                        mode for chip select2 (cs_n2).  It is
6228                                          used both in Auto and Manual Mode. */
6229       __IOM unsigned int QSPI_D7TOD4_DATA_CSN3 : 4; /*!< [27..24] Value of SPI_IO7,6,5 and 4 in
6230                                         case of quad/dual/single mode for chip
6231                                         select3 (cs_n3). It is used both in Auto
6232                                           and Manual Mode. */
6233       __IOM unsigned int QSPI_D7TOD4_OEN_CSN3 : 4;  /*!< [31..28] Direction Control for SPI_IO
6234                                        7,6,5 and 4 in case of quad/dual/single
6235                                        mode for chip select3 (cs_n3).  It is
6236                                          used both in Auto and Manual Mode. */
6237     } OCTASPI_BUS_CONTROLLER_b;
6238   };
6239 
6240   union {
6241     __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; /*!< (@ 0x000000B4) none */
6242 
6243     struct {
6244       __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 : 32; /*!< [31..0] Holds the 32 bit
6245                                                    base address unmask value for
6246                                                    select chip select0 in
6247                                                    programmable auto csn mode.
6248                                                    It is valid
6249                                                        only programmable auto
6250                                                    csn mode is enabled. */
6251     } QSPI_AUTO_BASE_ADDR_UNMASK_CSN0_b;
6252   };
6253 
6254   union {
6255     __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; /*!< (@ 0x000000B8) none */
6256 
6257     struct {
6258       __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 : 32; /*!< [31..0] Holds the 32 bit
6259                                                    base address unmask value for
6260                                                    select chip select1 in
6261                                                    programmable auto csn mode.
6262                                                    It is valid
6263                                                        only programmable auto
6264                                                    csn mode is enabled. */
6265     } QSPI_AUTO_BASE_ADDR_UNMASK_CSN1_b;
6266   };
6267   __IM unsigned int RESERVED4[2];
6268 
6269   union {
6270     __IOM unsigned int OCTASPI_BUS_CONTROLLER_2_REG; /*!< (@ 0x000000C4) none */
6271 
6272     struct {
6273       __IOM unsigned int SET_IP_MODE : 1;             /*!< [0..0] This bit enables the qspi
6274                                             interface pins into HiZ mode    */
6275       __IOM unsigned int AES_NONCE_INIT : 1;          /*!< [1..1] This bit enables the AES
6276                                             initialization with nonce */
6277       __IOM unsigned int AES_SEC_ENABLE : 1;          /*!< [2..2] This bit enables the AES
6278                                             security enable or not */
6279       __IOM unsigned int DUAL_MODE_EN : 1;            /*!< [3..3] Dual flash mode enable control. */
6280       __IOM unsigned int CSN0_2_CSN : 2;              /*!< [5..4] Map csn0 to the programmed csn. It is
6281                              valid for both manual and auto modes */
6282       __IOM unsigned int CSN1_2_CSN : 2;              /*!< [7..6] Map csn1 to the programmed csn. It is
6283                              valid for both manual and auto modes */
6284       __IOM unsigned int CSN2_2_CSN : 2;              /*!< [9..8] Map csn2 to the programmed csn. It is
6285                              valid for both manual and auto modes */
6286       __IOM unsigned int CSN3_2_CSN : 2;              /*!< [11..10] Map csn3 to the programmed csn. It is
6287                              valid for both manual and auto modes */
6288       __IOM unsigned int AES_SEC_ENABLE_SG1 : 1;      /*!< [12..12] This bit enables the AES
6289                                      security enable or not for segment 1 */
6290       __IOM unsigned int AES_SEC_ENABLE_SG2 : 1;      /*!< [13..13] This bit enables the AES
6291                                      security enable or not for segment 2 */
6292       __IOM unsigned int AES_SEC_ENABLE_SG3 : 1;      /*!< [14..14] This bit enables the AES
6293                                      security enable or not for segment 3 */
6294       __IOM unsigned int AES_SEC_ENABLE_SG4 : 1;      /*!< [15..15] This bit enables the AES
6295                                      security enable or not for segment 4 */
6296       __IOM unsigned int DUAL_MODE_SWAP_LINES : 1;    /*!< [16..16] This bit controls the 8 lines
6297                                        of qspi with 4 bit swap manner */
6298       __IOM unsigned int AUTO_MODE_IN_DEFAULT_EN : 1; /*!< [17..17] Qspi works in auto mode if
6299                                           set this is bit by default. */
6300       __IOM unsigned int OTP_KEY_LOAD : 1;            /*!< [18..18] Enable to load key from OTP/KH */
6301       __IOM unsigned int DUAL_STAGE_EN_MANUAL : 1;    /*!< [19..19] Dual stage en for
6302                                                   dual flash mode */
6303       __IOM unsigned int RESERVED2 : 12;              /*!< [31..20] reserved2           */
6304     } OCTASPI_BUS_CONTROLLER_2_REG_b;
6305   };
6306 
6307   union {
6308     __IOM unsigned int QSPI_AES_CONFIG; /*!< (@ 0x000000C8) QSPI AES CONFIG REG */
6309 
6310     struct {
6311       __IOM unsigned int QSPI_AES_MODE : 9;      /*!< [8..0] AES mode of decryption CTR/XTS */
6312       __IOM unsigned int QSPI_AES_DECKEYCAL : 1; /*!< [9..9] Enables pre-calculation of KEY
6313                                      before decryption operation         */
6314       __IOM unsigned int FLIP_KEY_FRM_REG : 1;   /*!< [10..10] writing 1 to this Flips the 32-bit
6315                                    endian key taken from kh */
6316       __IOM unsigned int FLIP_KEY_FRM_KH : 1;    /*!< [11..11] writing 1 to this Flips the 32-bit
6317                                   endian key taken from kh */
6318       __OM unsigned int QSPI_AES_SRST : 1;       /*!< [12..12] Synchronous soft reset for
6319                                           AES Module. Write only bit. Reading
6320                                           this bit gives alway 0 */
6321       __IOM unsigned int RESERVED1 : 19;         /*!< [31..13] reserved1   */
6322     } QSPI_AES_CONFIG_b;
6323   };
6324 
6325   union {
6326     __IOM unsigned int QSPI_AES_KEY_IV_VALID; /*!< (@ 0x000000CC) QSPI AES KEYS and
6327                                              IVS VALID */
6328 
6329     struct {
6330       __IOM unsigned int QSPI_AES_KEY1_VALID : 4; /*!< [3..0] Write enables for AES KEY 1.
6331                                        Denotes which bytes of key1  is valid  */
6332       __IOM unsigned int RESERVED1 : 4;           /*!< [7..4] reserved1 */
6333       __IOM unsigned int QSPI_AES_KEY2_VALID : 4; /*!< [11..8] Write enables for AES KEY 2.
6334                                        Denotes which bytes of  key2 is valid  */
6335       __IOM unsigned int RESERVED2 : 4;           /*!< [15..12] reserved2 */
6336       __IOM unsigned int QSPI_AES_IV1_VALID : 4;  /*!< [19..16] Write enables for AES IV 1.
6337                                         Denotes which bytes of    IV1 is valid    */
6338       __IOM unsigned int RESERVED3 : 12;          /*!< [31..20] reserved3 */
6339     } QSPI_AES_KEY_IV_VALID_b;
6340   };
6341 
6342   union {
6343     __IM unsigned int QSPI_CMNFLASH_STS; /*!< (@ 0x000000D0) QSPI Common Flash Status */
6344 
6345     struct {
6346       __IM unsigned int QSPI_MANUAL_BLOCKED : 1; /*!< [0..0] 1 - Manual read/write transaction
6347                                       initiated is blocked.0- No manual
6348                                       transactions */
6349       __IM unsigned int AUTO_READ_OUT_RANGE : 1; /*!< [1..1] 1- Auto read transaction is out
6350                                       of M4 Address range 0- Auto read
6351                                       transaction is in Address range */
6352       __IM unsigned int QSPI_AUTO_RD_BUSY : 1;   /*!< [2..2] 1 - Auto read transactions in
6353                                        progress.0 - No Auto read    transactions    */
6354       __IM unsigned int RESERVED1 : 29;          /*!< [31..3] reserved1 */
6355     } QSPI_CMNFLASH_STS_b;
6356   };
6357   __IM unsigned int RESERVED5[4];
6358 
6359   union {
6360     __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_1; /*!< (@ 0x000000E4)
6361                                        QSPI_AES_SEC_SEG_LS_ADDR_1 */
6362 
6363     struct {
6364       __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_1 : 32; /*!< [31..0] This register specifies
6365                                               the lower boundary address of
6366                                                        1st segment */
6367     } QSPI_AES_SEC_SEG_LS_ADDR_1_b;
6368   };
6369 
6370   union {
6371     __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_1; /*!< (@ 0x000000E8)
6372                                        QSPI_AES_SEC_SEG_MS_ADDR_1 */
6373 
6374     struct {
6375       __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_1 : 32; /*!< [31..0] This register specifies
6376                                               the upper boundary address of
6377                                                        1st segment */
6378     } QSPI_AES_SEC_SEG_MS_ADDR_1_b;
6379   };
6380 
6381   union {
6382     __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_2; /*!< (@ 0x000000EC)
6383                                        QSPI_AES_SEC_SEG_LS_ADDR_2 */
6384 
6385     struct {
6386       __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_2 : 32; /*!< [31..0] This register specifies
6387                                               the lower boundary address of
6388                                                        2nd segment */
6389     } QSPI_AES_SEC_SEG_LS_ADDR_2_b;
6390   };
6391 
6392   union {
6393     __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_2; /*!< (@ 0x000000F0)
6394                                        QSPI_AES_SEC_SEG_MS_ADDR_2 */
6395 
6396     struct {
6397       __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_2 : 32; /*!< [31..0] This register specifies
6398                                               the upper boundary address of
6399                                                        2nd segment */
6400     } QSPI_AES_SEC_SEG_MS_ADDR_2_b;
6401   };
6402 
6403   union {
6404     __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_3; /*!< (@ 0x000000F4)
6405                                        QSPI_AES_SEC_SEG_LS_ADDR_3 */
6406 
6407     struct {
6408       __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_3 : 32; /*!< [31..0] This register specifies
6409                                               the lower boundary address of
6410                                                        3rd segment */
6411     } QSPI_AES_SEC_SEG_LS_ADDR_3_b;
6412   };
6413 
6414   union {
6415     __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_3; /*!< (@ 0x000000F8)
6416                                        QSPI_AES_SEC_SEG_MS_ADDR_3 */
6417 
6418     struct {
6419       __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_3 : 32; /*!< [31..0] This register specifies
6420                                               the upper boundary address of
6421                                                        3rd segment */
6422     } QSPI_AES_SEC_SEG_MS_ADDR_3_b;
6423   };
6424 
6425   union {
6426     __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_4; /*!< (@ 0x000000FC)
6427                                        QSPI_AES_SEC_SEG_LS_ADDR_4 */
6428 
6429     struct {
6430       __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_4 : 32; /*!< [31..0] This register specifies
6431                                               the lower boundary address of
6432                                                        4th segment */
6433     } QSPI_AES_SEC_SEG_LS_ADDR_4_b;
6434   };
6435 
6436   union {
6437     __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_4; /*!< (@ 0x00000100)
6438                                        QSPI_AES_SEC_SEG_MS_ADDR_4 */
6439 
6440     struct {
6441       __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_4 : 32; /*!< [31..0] This register specifies
6442                                               the upper boundary address of
6443                                                        4th segment */
6444     } QSPI_AES_SEC_SEG_MS_ADDR_4_b;
6445   };
6446 
6447   union {
6448     __IOM unsigned int QSPI_SRAM_CTRL_CSN_REG[4]; /*!< (@ 0x00000104) QSPI SRAM CTRL CSN */
6449 
6450     struct {
6451       __IOM unsigned int BIT_8_MODE : 1;      /*!< [0..0] Flash 8bit (1 byte) boundary mode */
6452       __IOM unsigned int BYTE_32_MODE : 1;    /*!< [1..1] Flash 32 byte boundary mode */
6453       __IOM unsigned int ADDR_16BIT_MODE : 1; /*!< [2..2] Send only lower 16bits of
6454                                              Address enable. */
6455       __IOM unsigned int RESERVED1 : 5;       /*!< [7..3] reserved1       */
6456       __IOM unsigned int CMD_MODE : 2;        /*!< [9..8] writing cmd mode        */
6457       __IOM unsigned int ADDR_MODE : 2;       /*!< [11..10] writing address mode       */
6458       __IOM unsigned int DATA_MODE : 2;       /*!< [13..12] writing address mode       */
6459       __IOM unsigned int RESERVED2 : 2;       /*!< [15..14] reserved2       */
6460       __IOM unsigned int WR_CMD : 8;          /*!< [23..16] Command to be used for writing */
6461       __IOM unsigned int RESERVED3 : 8;       /*!< [31..24] reserved3 */
6462     } QSPI_SRAM_CTRL_CSN_REG_b[4];
6463   };
6464   __IM unsigned int RESERVED6[2];
6465   __IOM
6466   unsigned int SEMI_AUTO_MODE_ADDR_REG; /*!< (@ 0x0000011C) Byte address to read
6467                                            the data from flash in semi auto
6468                                            mode.  It is valid only semi auto
6469                                            mode enable bit is asserted */
6470 
6471   union {
6472     __IOM unsigned int SEMI_AUTO_MODE_CONFIG_REG; /*!< (@ 0x00000120) none */
6473 
6474     struct {
6475       __IOM unsigned int QSPI_SEMI_AUTO_BSIZE : 8; /*!< [7..0] This is burst size to read data
6476                                        from flash in semi auto mode */
6477       __IOM unsigned int QSPI_SEMI_AUTO_HSIZE : 2; /*!< [9..8] Indicates number of bytes valid
6478                                         in each transaction                */
6479       __IOM unsigned int RESERVED1 : 22;           /*!< [31..10] reserved1 */
6480     } SEMI_AUTO_MODE_CONFIG_REG_b;
6481   };
6482 
6483   union {
6484     __IOM unsigned int SEMI_AUTO_MODE_CONFIG2_REG; /*!< (@ 0x00000124) none */
6485 
6486     struct {
6487       __IOM unsigned int QSPI_SEMI_AUTO_RD_CNT : 12; /*!< [11..0] Total number of bytes to be
6488                                          read flash continuously from the
6489                                          address given by
6490                                          SEMI_AUTO_MODE_ADDR_REG */
6491       __IOM unsigned int QSPI_SEMI_AUTO_MODE_EN : 1; /*!< [12..12] Enable for semi auto mode
6492                                          read operation. Make sure manual mode
6493                                          read/write operation is completed
6494                                          before asserting this bit */
6495       __IOM unsigned int QSPI_SEMI_AUTO_RD_BUSY : 1; /*!< [13..13] Indicates status of semi
6496                                          auto mode read status. If it is high,
6497                                          semi auto mode read operation is
6498                                          progressing                  */
6499       __IOM unsigned int RESERVED1 : 18;             /*!< [31..14] reserved1  */
6500     } SEMI_AUTO_MODE_CONFIG2_REG_b;
6501   };
6502 
6503   union {
6504     __IOM unsigned int QSPI_BUS_MODE2_REG; /*!< (@ 0x00000128) none */
6505 
6506     struct {
6507       __IOM unsigned int PREFETCH_ENBLD_MSTR_ID : 4;      /*!< [3..0] Holds the programmable
6508                                          prefetch enabled AHB master ID. This is
6509                                          commonly used for enabling prefetch for
6510                                          icache master. */
6511       __IOM unsigned int PREFETCH_EN_FOR_ICACHE_MSTR : 1; /*!< [4..4] Prefetch enable for
6512                                               icache AHB master. */
6513       __IOM unsigned int RESERVED1 : 3;                   /*!< [7..5] Reserved for future use */
6514       __IOM
6515       unsigned int QSPI_PREFETCH_ENBLD_TRANS_BYTES : 8; /*!< [15..8] Programmable
6516                                                       prefetch enabled AHB
6517                                                       master transfer bytes.
6518                                                            Assume this is used
6519                                                       for icache and dma ahb
6520                                                       master access in auto
6521                                                       mode. */
6522       __IOM unsigned int RESERVED2 : 16;                /*!< [31..16] Reserved for future use */
6523     } QSPI_BUS_MODE2_REG_b;
6524   };
6525 
6526   union {
6527     __IOM unsigned int QSPI_AES_SEC_KEY_FRM_KH_REG; /*!< (@ 0x0000012C) none */
6528 
6529     struct {
6530       __OM unsigned int START_LOADING_SEC_KEY_FRM_KH : 1; /*!< [0..0] Start Security key
6531                                                loading from KH. */
6532       __IM unsigned int LOADING_SEC_KEY_FRM_KH : 1;       /*!< [1..1] Indicates security key loading
6533                                          status from KH.                     */
6534       __IOM unsigned int SEC_KEY_READING_INTERVAL : 4;    /*!< [5..2] Security key
6535                                                       reading interval */
6536       __IOM unsigned int RESERVED1 : 26;                  /*!< [31..6] Reserved for future use */
6537     } QSPI_AES_SEC_KEY_FRM_KH_REG_b;
6538   };
6539 
6540   union {
6541     __IOM unsigned int QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; /*!< (@ 0x00000130) none */
6542 
6543     struct {
6544       __IOM unsigned int CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG : 12; /*!< [11..0] Maximum
6545                                                        Continue fetch wait time
6546                                                        between two qspi auto
6547                                                        reads. */
6548       __IOM unsigned int CONTINUE_FETCH_EN : 1;                          /*!< [12..12] Continue fetch feature
6549                                                enable. */
6550       __IOM unsigned int RESERVED1 : 19;                                 /*!< [31..13] Reserved for future use */
6551     } QSPI_AUTO_CONITNUE_FETCH_CTRL_REG_b;
6552   };
6553 
6554   union {
6555     __IOM unsigned int QSPI_AES_KEY1_0_3; /*!< (@ 0x00000134) QSPI_AES_KEY1_0_3 */
6556 
6557     struct {
6558       __IOM unsigned int QSPI_AES_KEY1_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes
6559                                      key1 as 0 referred as lsb in the key */
6560     } QSPI_AES_KEY1_0_3_b;
6561   };
6562 
6563   union {
6564     __IOM unsigned int QSPI_AES_KEY1_4_7; /*!< (@ 0x00000138) QSPI_AES_KEY1_4_7 */
6565 
6566     struct {
6567       __IOM unsigned int QSPI_AES_KEY1_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes
6568                                      key1 as 0 referred as lsb */
6569     } QSPI_AES_KEY1_4_7_b;
6570   };
6571 
6572   union {
6573     __IOM unsigned int QSPI_AES_KEY1_8_B; /*!< (@ 0x0000013C) QSPI_AES_KEY1_8_B */
6574 
6575     struct {
6576       __IOM unsigned int QSPI_AES_KEY1_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes
6577                                      key1 as 0 referred as lsb */
6578     } QSPI_AES_KEY1_8_B_b;
6579   };
6580 
6581   union {
6582     __IOM unsigned int QSPI_AES_KEY1_C_F; /*!< (@ 0x00000140) QSPI_AES_KEY1_C_F */
6583 
6584     struct {
6585       __IOM unsigned int QSPI_AES_KEY1_C_F : 32; /*!< [31..0] To hold first 11-8 bytes of aes
6586                                      key1 as 0 referred as lsb */
6587     } QSPI_AES_KEY1_C_F_b;
6588   };
6589   __IM unsigned int RESERVED7[4];
6590 
6591   union {
6592     __IOM unsigned int QSPI_AES_KEY2_0_3; /*!< (@ 0x00000154) QSPI_AES_KEY2_0_3 */
6593 
6594     struct {
6595       __IOM unsigned int QSPI_AES_KEY2_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes
6596                                      key2 as 0 referred as lsb in the key */
6597     } QSPI_AES_KEY2_0_3_b;
6598   };
6599 
6600   union {
6601     __IOM unsigned int QSPI_AES_KEY2_4_7; /*!< (@ 0x00000158) QSPI_AES_KEY2_4_7 */
6602 
6603     struct {
6604       __IOM unsigned int QSPI_AES_KEY2_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes
6605                                      key2 as 0 referred as lsb */
6606     } QSPI_AES_KEY2_4_7_b;
6607   };
6608 
6609   union {
6610     __IOM unsigned int QSPI_AES_KEY2_8_B; /*!< (@ 0x0000015C) QSPI_AES_KEY2_8_B */
6611 
6612     struct {
6613       __IOM unsigned int QSPI_AES_KEY2_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes
6614                                      key2 as 0 referred as lsb */
6615     } QSPI_AES_KEY2_8_B_b;
6616   };
6617 
6618   union {
6619     __IOM unsigned int QSPI_AES_KEY2_C_F; /*!< (@ 0x00000160) QSPI_AES_KEY2_C_F */
6620 
6621     struct {
6622       __IOM unsigned int QSPI_AES_KEY2_C_F : 32; /*!< [31..0] To hold first 15-12 bytes of aes
6623                                      key2 as 0 referred as lsb */
6624     } QSPI_AES_KEY2_C_F_b;
6625   };
6626 } QSPI_Type; /*!< Size = 356 (0x164) */
6627 
6628 /* ===========================================================================================================================
6629  */
6630 /* ================                                            CRC
6631  * ================ */
6632 /* ===========================================================================================================================
6633  */
6634 
6635 /**
6636  * @brief CRC is used in all wireless communication as a first data integrity
6637  * check (CRC)
6638  */
6639 
6640 typedef struct { /*!< (@ 0x45080000) CRC Structure */
6641 
6642   union {
6643     __IOM unsigned int CRC_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set
6644                                             register */
6645 
6646     struct {
6647       __IOM unsigned int SOFT_RST : 1;   /*!< [0..0] Soft reset. This clears the FIFO and settles
6648                            all the state machines to their IDLE */
6649       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use. */
6650     } CRC_GEN_CTRL_SET_REG_b;
6651   };
6652 
6653   union {
6654     __IOM unsigned int CRC_GEN_CTRL_RESET; /*!< (@ 0x00000004) General control reset
6655                                           register */
6656 
6657     struct {
6658       __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved for future use. */
6659     } CRC_GEN_CTRL_RESET_b;
6660   };
6661 
6662   union {
6663     __IM unsigned int CRC_GEN_STS; /*!< (@ 0x00000008) General status register */
6664 
6665     struct {
6666       __IM unsigned int CALC_DONE : 1;          /*!< [0..0] When the computation of final CRC
6667                                       with the data out of fifo, this will get
6668                                       set to 1 otherwise 0 */
6669       __IM unsigned int DIN_NUM_BYTES_DONE : 1; /*!< [1..1] When number of bytes requested for
6670                                      computation of final CRC is read from fifo
6671                                      by internal FSM, this will get set to 1
6672                                      otherwise 0. */
6673       __IM unsigned int RESERVED1 : 30;         /*!< [31..2] Reserved for future use. */
6674     } CRC_GEN_STS_b;
6675   };
6676 
6677   union {
6678     __IOM unsigned int CRC_POLYNOMIAL; /*!< (@ 0x0000000C) This register holds the polynomial
6679                            with which the final CRC is computed. */
6680 
6681     struct {
6682       __IOM unsigned int POLYNOMIAL : 32; /*!< [31..0] Polynomial register. This register holds
6683                               the polynomial with which the final CRC is
6684                               computed.When write Polynomial will be
6685                               updated.When read read polynomial. */
6686     } CRC_POLYNOMIAL_b;
6687   };
6688 
6689   union {
6690     __IOM unsigned int CRC_POLYNOMIAL_CTRL_SET; /*!< (@ 0x00000010) Polynomial
6691                                                control set register */
6692 
6693     struct {
6694       __IOM unsigned int POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width set. Number of
6695                                         bits/width of the polynomial  has to be
6696                                         written here for the computation of final
6697                                         CRC.  If a new width has to be configured,
6698                                         clear the existing  length first by
6699                                         writing 0x1f in polynomial_ctrl_reset
6700                                         register.  When read, actual polynomial
6701                                         width is read.  */
6702       __IOM unsigned int RESERVED1 : 27;           /*!< [31..5] Reserved for future use. */
6703     } CRC_POLYNOMIAL_CTRL_SET_b;
6704   };
6705 
6706   union {
6707     __IOM unsigned int CRC_POLYNOMIAL_CTRL_RESET; /*!< (@ 0x00000014) Polynomial
6708                                                  control set register */
6709 
6710     struct {
6711       __IOM unsigned int POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width reset. If a new
6712                                        width has to be configured, clear the
6713                                        existing length first by writing 0x1f.
6714                                        When read, actual polynomial width is
6715                                        read. */
6716       __IOM unsigned int RESERVED1 : 27;           /*!< [31..5] Reserved for future use. */
6717     } CRC_POLYNOMIAL_CTRL_RESET_b;
6718   };
6719 
6720   union {
6721     __IOM unsigned int CRC_LFSR_INIT_VAL; /*!< (@ 0x00000018) LFSR initial value */
6722 
6723     struct {
6724       __IOM unsigned int LFSR_INIT : 32; /*!< [31..0] This holds LFSR initialization value.
6725                              When ever LFSR needs to be initialized, this has to
6726                              be updated with the init value and trigger
6727                              init_lfsr in LFSR_INIT_CTRL_SET register. For
6728                              example, in WiFi case, 0xffffffff is used as init
6729                              value of LFSR. */
6730     } CRC_LFSR_INIT_VAL_b;
6731   };
6732 
6733   union {
6734     __IOM unsigned int CRC_LFSR_INIT_CTRL_SET; /*!< (@ 0x0000001C) LFSR state initialization
6735                                    control set register             */
6736 
6737     struct {
6738       __IOM unsigned int CLEAR_LFSR : 1;           /*!< [0..0] Clear LFSR state. When this is
6739                                         set, LFSR state is cleared to 0 */
6740       __IOM unsigned int INIT_LFSR : 1;            /*!< [1..1] Initialize LFSR state. When this
6741                                        is set LFSR state will be initialized
6742                                        with LFSR_INIT_VAL/bit swapped
6743                                        LFSR_INIT_VAL in the next cycle */
6744       __IOM unsigned int USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If
6745                                         this is set bit swapped  version of LFSR
6746                                         init value will be loaded / initialized
6747                                            to LFSR state  */
6748       __IOM unsigned int RESERVED1 : 29;           /*!< [31..3] Reserved for future use. */
6749     } CRC_LFSR_INIT_CTRL_SET_b;
6750   };
6751 
6752   union {
6753     __IOM unsigned int CRC_LFSR_INIT_CTRL_RESET; /*!< (@ 0x00000020) LFSR state initialization
6754                                      control reset register           */
6755 
6756     struct {
6757       __IOM unsigned int RESERVED1 : 1;            /*!< [0..0] Reserved for future use. */
6758       __IOM unsigned int RESERVED2 : 1;            /*!< [1..1] Reserved for future use. */
6759       __IOM unsigned int USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If
6760                                         this is set bit swapped  version of LFSR
6761                                         init value will be loaded / initialized
6762                                            to LFSR state  */
6763       __IOM unsigned int RESERVED3 : 29;           /*!< [31..3] Reserved for future use. */
6764     } CRC_LFSR_INIT_CTRL_RESET_b;
6765   };
6766 
6767   union {
6768     __OM unsigned int CRC_DIN_FIFO; /*!< (@ 0x00000024) Data input FIFO register */
6769 
6770     struct {
6771       __OM unsigned int DIN_FIFO : 32; /*!< [31..0] FIFO input port is mapped to this
6772                             register. Data on which the final CRC has to be
6773                             computed has to be loaded to this FIFO */
6774     } CRC_DIN_FIFO_b;
6775   };
6776 
6777   union {
6778     __IOM unsigned int CRC_DIN_CTRL_SET; /*!< (@ 0x00000028) Input data control set
6779                                         register                            */
6780 
6781     struct {
6782       __IOM unsigned int DIN_WIDTH_REG : 5;         /*!< [4..0] Valid number of bits in the input data
6783                                 in din_width_from_reg set mode. Before writing a
6784                                 new value into this,  din_ctrl_reset_reg has to
6785                                 be written with 0x1f to clear this field as
6786                                 these are set/clear bits. */
6787       __IOM unsigned int DIN_WIDTH_FROM_REG : 1;    /*!< [5..5] Valid number of bits in the input
6788                                      data. In default, number of valid bits in
6789                                      the input data is taken from ULI (uli_be).
6790                                           If this is set, whatever is the input
6791                                      size, only din_ctrl_reg[4:0] is taken as
6792                                      valid length/width for inout data. */
6793       __IOM unsigned int DIN_WIDTH_FROM_CNT : 1;    /*!< [6..6] Valid number of bits in the input
6794                                      data. In default, number of valid bits in
6795                                      the input data is taken from ULI (uli_be).
6796                                           If this is set, a mix of ULI length
6797                                      and number of bytes remaining will form the
6798                                      valid bits (which ever is less
6799                                           that will be considered as valid
6800                                      bits).                                   */
6801       __IOM unsigned int USE_SWAPPED_DIN : 1;       /*!< [7..7] Use bit swapped input data. If this
6802                                   is set, input data will be swapped and filled
6803                                   in to FIFO. Whatever read out from FIFO will
6804                                   be directly fed to LFSR engine. */
6805       __IOM unsigned int RESET_FIFO_PTRS : 1;       /*!< [8..8] Reset fifo pointer. This
6806                                              clears the FIFO.When this is set,
6807                                              FIFO will be cleared. */
6808       __IOM unsigned int RESERVED1 : 15;            /*!< [23..9] Reserved for future use. */
6809       __IOM unsigned int FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold
6810                                         value. This has to be cleared by writing
6811                                         0x0f000000 into din_ctrl_reset before
6812                                         updating any new value. */
6813       __IOM unsigned int FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold
6814                                         value. This has to be cleared by writing
6815                                         0xf0000000 into din_ctrl_reset before
6816                                         updating any new value */
6817     } CRC_DIN_CTRL_SET_b;
6818   };
6819 
6820   union {
6821     __IOM unsigned int CRC_DIN_CTRL_RESET_REG; /*!< (@ 0x0000002C) Input data
6822                                               control set register */
6823 
6824     struct {
6825       __IOM unsigned int DIN_WIDTH_REG : 5;         /*!< [4..0] Valid number of bits in the input data
6826                                 in din_width_from_reg set mode. Before writing a
6827                                 new value into this,  din_ctrl_reset_reg has to
6828                                 be written with 0x1f to clear this field as
6829                                 these are set/clear bits. */
6830       __IOM unsigned int DIN_WIDTH_FROM_REG : 1;    /*!< [5..5] Valid number of bits in the input
6831                                      data. In default, number of valid bits in
6832                                      the input data is taken from ULI (uli_be).
6833                                           If this is set, whatever is the input
6834                                      size, only din_ctrl_reg[4:0] is taken as
6835                                      valid length/width for inout data. */
6836       __IOM unsigned int DIN_WIDTH_FROM_CNT : 1;    /*!< [6..6] Valid number of bits in the input
6837                                      data. In default, number of valid bits in
6838                                      the input data is taken from ULI (uli_be).
6839                                           If this is set, a mix of ULI length
6840                                      and number of bytes remaining will form the
6841                                      valid bits (which ever is less
6842                                           that will be considered as valid
6843                                      bits).                                   */
6844       __IOM unsigned int USE_SWAPPED_DIN : 1;       /*!< [7..7] Use bit swapped input data. If this
6845                                   is set input data will be swapped and filled
6846                                   in to FIFO. Whatever read out from FIFO will
6847                                   be directly fed to LFSR engine. */
6848       __IOM unsigned int RESERVED1 : 1;             /*!< [8..8] Reserved for future use.  */
6849       __IOM unsigned int RESERVED2 : 15;            /*!< [23..9] Reserved for future use. */
6850       __IOM unsigned int FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold
6851                                         value. This has to be cleared by writing
6852                                         0x0f000000 into din_ctrl_reset before
6853                                         updating any new value. */
6854       __IOM unsigned int FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold
6855                                         value. This has to be cleared by writing
6856                                         0xf0000000 into din_ctrl_reset before
6857                                         updating any new value */
6858     } CRC_DIN_CTRL_RESET_REG_b;
6859   };
6860 
6861   union {
6862     __IOM unsigned int CRC_DIN_NUM_BYTES; /*!< (@ 0x00000030) Data input FIFO register */
6863 
6864     struct {
6865       __IOM unsigned int DIN_NUM_BYTES : 32; /*!< [31..0] in out data number of bytes */
6866     } CRC_DIN_NUM_BYTES_b;
6867   };
6868 
6869   union {
6870     __IM unsigned int CRC_DIN_STS; /*!< (@ 0x00000034) Input data status register */
6871 
6872     struct {
6873       __IM unsigned int FIFO_EMPTY : 1;  /*!< [0..0] FIFO empty indication status */
6874       __IM unsigned int FIFO_AEMPTY : 1; /*!< [1..1] FIFO almost empty indication status. */
6875       __IM unsigned int FIFO_AFULL : 1;  /*!< [2..2] FIFO almost full indication status */
6876       __IM unsigned int FIFO_FULL : 1;   /*!< [3..3] FIFO full indication status  */
6877       __IM unsigned int FIFO_OCC : 6;    /*!< [9..4] FIFO occupancy   */
6878       __IM unsigned int RESERVED1 : 22;  /*!< [31..10] Reserved for future use. */
6879     } CRC_DIN_STS_b;
6880   };
6881 
6882   union {
6883     __IOM unsigned int CRC_LFSR_STATE; /*!< (@ 0x00000038) LFSR state register */
6884 
6885     struct {
6886       __IOM unsigned int LFSR_STATE : 32; /*!< [31..0] If LFSR dynamic loading is
6887                                          required this can be used for writing
6888                                          the LFSR state directly. */
6889     } CRC_LFSR_STATE_b;
6890   };
6891 } CRC_Type; /*!< Size = 60 (0x3c) */
6892 
6893 /* ===========================================================================================================================
6894  */
6895 /* ================                                           EFUSE
6896  * ================ */
6897 /* ===========================================================================================================================
6898  */
6899 
6900 /**
6901  * @brief The EFUSE controller is used to provide an interface to one time
6902  * program memory (EFUSE macro) to perform write and read operations (EFUSE)
6903  */
6904 
6905 typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */
6906 
6907   union {
6908     __IOM unsigned int EFUSE_DA_ADDR_REG; /*!< (@ 0x00000000) Direct Access Registers */
6909 
6910     struct {
6911       __IOM unsigned int ADDR_BITS : 16; /*!< [15..0] These bits specifies the address to write
6912                              or read from EFUSE macro model */
6913       __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */
6914     } EFUSE_DA_ADDR_REG_b;
6915   };
6916 
6917   union {
6918     __IOM unsigned int EFUSE_DA_CTRL_SET_REG; /*!< (@ 0x00000004) Direct Access Set
6919                                              Registers */
6920 
6921     struct {
6922       __IOM unsigned int PGENB : 1;      /*!< [0..0] Set Program enable      */
6923       __IOM unsigned int CSB : 1;        /*!< [1..1] Set Chip Enable        */
6924       __IOM unsigned int STROBE : 1;     /*!< [2..2] Set strobe enable     */
6925       __IOM unsigned int LOAD : 1;       /*!< [3..3] Set Load enable       */
6926       __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */
6927       __IOM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */
6928     } EFUSE_DA_CTRL_SET_REG_b;
6929   };
6930 
6931   union {
6932     __IOM unsigned int EFUSE_DA_CTRL_CLEAR_REG; /*!< (@ 0x00000008) Direct Access
6933                                                Clear Registers */
6934 
6935     struct {
6936       __IOM unsigned int PGENB : 1;     /*!< [0..0] Clear Program enable     */
6937       __IOM unsigned int CSB : 1;       /*!< [1..1] Clear Chip Enable       */
6938       __IM unsigned int RESERVED1 : 1;  /*!< [2..2] reserved1  */
6939       __IOM unsigned int LOAD : 1;      /*!< [3..3] Clear Load enable      */
6940       __IM unsigned int RESERVED2 : 12; /*!< [15..4] reserved2 */
6941       __IM unsigned int RESERVED3 : 16; /*!< [31..16] reserved3 */
6942     } EFUSE_DA_CTRL_CLEAR_REG_b;
6943   };
6944 
6945   union {
6946     __IOM unsigned int EFUSE_CTRL_REG; /*!< (@ 0x0000000C) Control Register */
6947 
6948     struct {
6949       __IOM unsigned int EFUSE_ENABLE : 1;             /*!< [0..0] This bit specifies whether the EFUSE
6950                                module is enabled or not */
6951       __IOM unsigned int EFUSE_DIRECT_PATH_ENABLE : 1; /*!< [1..1] This bit specifies whether
6952                                            the EFUSE direct path is enabled or
6953                                            not for direct accessing of the EFUSE
6954                                            pins                             */
6955       __IOM unsigned int ENABLE_EFUSE_WRITE : 1;       /*!< [2..2] Controls the switch on
6956                                                 VDDIQ for eFuse read/write. */
6957       __IM unsigned int RESERVED1 : 13;                /*!< [15..3] reserved1          */
6958       __IM unsigned int RESERVED2 : 16;                /*!< [31..16] reserved2          */
6959     } EFUSE_CTRL_REG_b;
6960   };
6961 
6962   union {
6963     __IOM unsigned int EFUSE_READ_ADDR_REG; /*!< (@ 0x00000010) Read address Register */
6964 
6965     struct {
6966       __IOM unsigned int READ_ADDR_BITS : 13; /*!< [12..0] These bits specifies the
6967                                              address from which read operation
6968                                                      has to be performed */
6969       __IM unsigned int RESERVED1 : 2;        /*!< [14..13] reserved1        */
6970       __OM unsigned int DO_READ : 1;          /*!< [15..15] Enables read FSM after EFUSE is
6971                                     enabled                          */
6972       __IM unsigned int RESERVED2 : 16;       /*!< [31..16] reserved2 */
6973     } EFUSE_READ_ADDR_REG_b;
6974   };
6975 
6976   union {
6977     __IOM unsigned int EFUSE_READ_DATA_REG; /*!< (@ 0x00000014) Read address Register */
6978 
6979     struct {
6980       __IOM unsigned int READ_DATA_BITS : 8; /*!< [7..0] These bits specifies the data bits
6981                                  that are read from a given address specified in
6982                                  the  EFUSE_READ_ADDRESS_REGISTER bits 8:0 */
6983       __IM unsigned int RESERVED1 : 7;       /*!< [14..8] reserved1     */
6984       __IM unsigned int READ_FSM_DONE : 1;   /*!< [15..15] Indicates read fsm is done.
6985                                           After this read data is available in
6986                                           EFUSE_READ_DATA_REGISTER bits 7:0 */
6987       __IM unsigned int RESERVED2 : 16;      /*!< [31..16] reserved2    */
6988     } EFUSE_READ_DATA_REG_b;
6989   };
6990 
6991   union {
6992     __IM unsigned int EFUSE_STATUS_REG; /*!< (@ 0x00000018) Read address Register */
6993 
6994     struct {
6995       __IM unsigned int EFUSE_ENABLED : 1;    /*!< [0..0] This bit specifies whether
6996                                           the EFUSE is enabled or not */
6997       __IM unsigned int RESERVED1 : 1;        /*!< [1..1] reserved1     */
6998       __IM unsigned int EFUSE_DOUT_SYNC : 8;  /*!< [9..2] This bit specifies the 8-bit data
6999                                   read out from the EFUSE macro. This is
7000                                   synchronized with pclk */
7001       __IM unsigned int STROBE_CLEAR_BIT : 1; /*!< [10..10] This bit indicates STROBE signal
7002                                    goes low after strobe
7003                                            count value reached '0' */
7004       __IM unsigned int RESERVED2 : 5;        /*!< [15..11] reserved2  */
7005       __IM unsigned int RESERVED3 : 16;       /*!< [31..16] reserved3 */
7006     } EFUSE_STATUS_REG_b;
7007   };
7008 
7009   union {
7010     __IOM unsigned int EFUSE_RD_TMNG_PARAM_REG; /*!< (@ 0x0000001C) none */
7011 
7012     struct {
7013       __IOM unsigned int TSUR_CS : 4;   /*!< [3..0] CSB to STROBE setup time into read mode */
7014       __IOM unsigned int TSQ : 4;       /*!< [7..4] Q7-Q0 access time from STROBE rising edge */
7015       __IOM unsigned int THRA : 4;      /*!< [11..8] for 32x8 macro: A4 A0 to STROBE hold
7016                                   time into Read mode 5122x8 macro: A8 A0 to
7017                                   STROBE hold time into Read mode */
7018       __IM unsigned int RESERVED1 : 4;  /*!< [15..12] reserved1  */
7019       __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */
7020     } EFUSE_RD_TMNG_PARAM_REG_b;
7021   };
7022   __IM unsigned int RESERVED;
7023 
7024   union {
7025     __IOM unsigned int EFUSE_MEM_MAP_LENGTH_REG; /*!< (@ 0x00000024) none */
7026 
7027     struct {
7028       __IOM unsigned int EFUSE_MEM_MAP_LEN : 1; /*!< [0..0] 0: 8 bit read 1: 16 bit read    */
7029       __IM unsigned int RESERVED1 : 15;         /*!< [15..1] reserved1 */
7030       __IM unsigned int RESERVED2 : 16;         /*!< [31..16] reserved2 */
7031     } EFUSE_MEM_MAP_LENGTH_REG_b;
7032   };
7033 
7034   union {
7035     __IOM
7036     unsigned int EFUSE_READ_BLOCK_STARTING_LOCATION; /*!< (@ 0x00000028) Starting
7037                                                    address from which the read
7038                                                    has to be blocked. Once the
7039                                                    end address is written, it
7040                                                    cannot be changed till power
7041                                                    on reset is given */
7042 
7043     struct {
7044       __IOM unsigned int EFUSE_READ_BLOCK_STARTING_LOCATION : 16; /*!< [15..0] Starting address
7045                                                       from which the read has to
7046                                                       be blocked. Once the end
7047                                                       address is written, it
7048                                                       cannot be changed till
7049                                                        power on reset is given.
7050                                                     */
7051       __IM unsigned int RESERVED1 : 16;                           /*!< [31..16] reserved1                */
7052     } EFUSE_READ_BLOCK_STARTING_LOCATION_b;
7053   };
7054 
7055   union {
7056     __IOM unsigned int EFUSE_READ_BLOCK_END_LOCATION; /*!< (@ 0x0000002C) Starting address from
7057                                           which the read has to be blocked. Once
7058                                           the end address is written, it cannot
7059                                           be changed till power on reset is
7060                                           given */
7061 
7062     struct {
7063       __IOM unsigned int EFUSE_READ_BLOCK_END_LOCATION : 16; /*!< [15..0] End address till
7064                                                  which the read has to be
7065                                                  blocked. Once the end address
7066                                                  is written , it cannot be
7067                                                  changed till
7068                                                        power on reset is given.
7069                                                */
7070       __IM unsigned int RESERVED1 : 16;                      /*!< [31..16] reserved1           */
7071     } EFUSE_READ_BLOCK_END_LOCATION_b;
7072   };
7073 
7074   union {
7075     __IOM unsigned int EFUSE_READ_BLOCK_ENABLE_REG; /*!< (@ 0x00000030) The Transmit Poll
7076                                         Demand register enables the Transmit DMA
7077                                         to check whether or not the current
7078                                         descriptor is owned by DMA */
7079 
7080     struct {
7081       __IOM unsigned int EFUSE_READ_BLOCK_ENABLE : 1; /*!< [0..0] Enable for blocking the read
7082                                           access from a programmable memory
7083                                           location */
7084       __IM unsigned int RESERVED1 : 15;               /*!< [15..1] reserved1    */
7085       __IM unsigned int RESERVED2 : 16;               /*!< [31..16] reserved2    */
7086     } EFUSE_READ_BLOCK_ENABLE_REG_b;
7087   };
7088 
7089   union {
7090     __IOM unsigned int EFUSE_DA_CLR_STROBE_REG; /*!< (@ 0x00000034) none */
7091 
7092     struct {
7093       __IOM unsigned int EFUSE_STROBE_CLR_CNT : 9; /*!< [8..0] Strobe signal Clear count in
7094                                        direct access mode. value
7095                                           depends on APB clock frequency of
7096                                        eFuse controller */
7097       __IOM unsigned int EFUSE_STROBE_ENABLE : 1;  /*!< [9..9] none */
7098       __IM unsigned int RESERVED1 : 6;             /*!< [15..10] reserved1            */
7099       __IM unsigned int RESERVED2 : 16;            /*!< [31..16] reserved2           */
7100     } EFUSE_DA_CLR_STROBE_REG_b;
7101   };
7102 } EFUSE_Type; /*!< Size = 56 (0x38) */
7103 
7104 /* ===========================================================================================================================
7105  */
7106 /* ================                                           I2S0
7107  * ================ */
7108 /* ===========================================================================================================================
7109  */
7110 
7111 /**
7112  * @brief I2S(Inter-IC Sound) is transferring two-channel digital audio data
7113  * from one IC device to another (I2S0)
7114  */
7115 
7116 typedef struct { /*!< (@ 0x47050000) I2S0 Structure */
7117 
7118   union {
7119     __IOM unsigned int I2S_IER; /*!< (@ 0x00000000) I2S Enable Register */
7120 
7121     struct {
7122       __IOM unsigned int IEN : 1;        /*!< [0..0] Inter Block Enable        */
7123       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7124     } I2S_IER_b;
7125   };
7126 
7127   union {
7128     __IOM unsigned int I2S_IRER; /*!< (@ 0x00000004) I2S Receiver Block Enable Register */
7129 
7130     struct {
7131       __IOM unsigned int RXEN : 1;       /*!< [0..0] Receive Block Enable, Bit Overrides
7132                                   any Individual Receive Channel Enables */
7133       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7134     } I2S_IRER_b;
7135   };
7136 
7137   union {
7138     __IOM unsigned int I2S_ITER; /*!< (@ 0x00000008) Transmitter Block Enable */
7139 
7140     struct {
7141       __IOM unsigned int TXEN : 1;       /*!< [0..0] Transmitter Block Enable, Bit Overrides any
7142                        Individual Transmit Channel Enables */
7143       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7144     } I2S_ITER_b;
7145   };
7146 
7147   union {
7148     __IOM unsigned int I2S_CER; /*!< (@ 0x0000000C) Clock Enable Register */
7149 
7150     struct {
7151       __IOM unsigned int CLKEN : 1;      /*!< [0..0] Clock generation enable/disable */
7152       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7153     } I2S_CER_b;
7154   };
7155 
7156   union {
7157     __IOM unsigned int I2S_CCR; /*!< (@ 0x00000010) Clock Configuration Register */
7158 
7159     struct {
7160       __IOM unsigned int SCLKG : 3;      /*!< [2..0] These bits are used to program the
7161                                    gating of sclk                  */
7162       __IOM unsigned int WSS : 2;        /*!< [4..3] These bits are used to program the
7163                                    number of sclk cycles           */
7164       __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */
7165     } I2S_CCR_b;
7166   };
7167 
7168   union {
7169     __OM unsigned int I2S_RXFFR; /*!< (@ 0x00000014) Receiver Block FIFO Reset Register */
7170 
7171     struct {
7172       __OM unsigned int RXFFR : 1;      /*!< [0..0] Writing a 1 To This Register Flushes
7173                                   All The RX FIFO's Receiver Block  Must be
7174                                   Disable Prior to Writing This Bit */
7175       __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7176     } I2S_RXFFR_b;
7177   };
7178 
7179   union {
7180     __OM unsigned int I2S_TXFFR; /*!< (@ 0x00000018) Transmitter Block FIFO Reset
7181                                 Register                      */
7182 
7183     struct {
7184       __OM unsigned int TXFFR : 1;      /*!< [0..0] Writing a 1 To This Register Flushes
7185                                   All The RX FIFO's Receiver Block  Must be
7186                                   Disable Prior to Writing This Bit */
7187       __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7188     } I2S_TXFFR_b;
7189   };
7190   __IM unsigned int RESERVED;
7191   __IOM I2S0_CHANNEL_CONFIG_Type CHANNEL_CONFIG[4]; /*!< (@ 0x00000020) [0..3] */
7192   __IM unsigned int RESERVED1[40];
7193 
7194   union {
7195     __IM unsigned int I2S_RXDMA; /*!< (@ 0x000001C0) Receiver Block DMA Register */
7196 
7197     struct {
7198       __IM unsigned int RXDMA : 32; /*!< [31..0] Used to cycle repeatedly through the enabled
7199                          receive channels  Reading stereo data pairs */
7200     } I2S_RXDMA_b;
7201   };
7202 
7203   union {
7204     __OM unsigned int I2S_RRXDMA; /*!< (@ 0x000001C4) Reset Receiver Block DMA Register */
7205 
7206     struct {
7207       __OM unsigned int RRXDMA : 1;     /*!< [0..0] Writing a 1 to this self-clearing
7208                                    register resets the RXDMA register */
7209       __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */
7210     } I2S_RRXDMA_b;
7211   };
7212 
7213   union {
7214     __OM unsigned int I2S_TXDMA; /*!< (@ 0x000001C8) Transmitter Block DMA Register */
7215 
7216     struct {
7217       __OM unsigned int TXDMA : 32; /*!< [31..0] Used to cycle repeatedly through
7218                                    the enabled transmit channels  allow to
7219                                    writing of stereo data pairs */
7220     } I2S_TXDMA_b;
7221   };
7222 
7223   union {
7224     __OM unsigned int I2S_RTXDMA; /*!< (@ 0x000001CC) Reset Transmitter Block DMA
7225                                  Register                       */
7226 
7227     struct {
7228       __OM unsigned int RTXDMA : 1;     /*!< [0..0] Writing a 1 to this self-clearing
7229                                    register resets the TXDMA register */
7230       __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */
7231     } I2S_RTXDMA_b;
7232   };
7233   __IM unsigned int RESERVED2[8];
7234 
7235   union {
7236     __IM unsigned int I2S_COMP_PARAM_2; /*!< (@ 0x000001F0) Component Parameter 2
7237                                        Register                             */
7238 
7239     struct {
7240       __IM unsigned int I2S_RX_WORDSIZE_0 : 3; /*!< [2..0] On Read returns the value
7241                                               of word size of receiver channel
7242                                                      0 */
7243       __IM unsigned int I2S_RX_WORDSIZE_1 : 3; /*!< [5..3] On Read returns the value
7244                                               of word size of receiver channel
7245                                                      1 */
7246       __IM unsigned int RESERVED1 : 1;         /*!< [6..6] Reserved1         */
7247       __IM unsigned int I2S_RX_WORDSIZE_2 : 3; /*!< [9..7] On Read returns the value
7248                                               of word size of receiver channel
7249                                                      2 */
7250       __IM unsigned int I2S_RX_WORDSIZE_3 : 3; /*!< [12..10] On Read returns the value of word
7251                                     size of receiver channel 3 */
7252       __IM unsigned int RESERVED2 : 19;        /*!< [31..13] Reserved2 */
7253     } I2S_COMP_PARAM_2_b;
7254   };
7255 
7256   union {
7257     __IM unsigned int I2S_COMP_PARAM_1; /*!< (@ 0x000001F4) Component Parameter 1
7258                                        Register                             */
7259 
7260     struct {
7261       __IM unsigned int APB_DATA_WIDTH : 2;        /*!< [1..0] Width of APB data bus */
7262       __IM unsigned int I2S_FIFO_DEPTH_GLOBAL : 2; /*!< [3..2] Determines FIFO depth
7263                                                   for all channels */
7264       __IM unsigned int I2S_FIFO_MODE_EN : 1;      /*!< [4..4] Determines whether component act as
7265                                    Master or Slave                */
7266       __IM unsigned int I2S_TRANSMITTER_BLOCK : 1; /*!< [5..5] Shows the presence of
7267                                                   the transmitter block */
7268       __IM unsigned int I2S_RECEIVER_BLOCK : 1;    /*!< [6..6] Shows the presence of
7269                                                   the receiver block    */
7270       __IM unsigned int I2S_RX_CHANNELS : 2;       /*!< [8..7] Returns the number of
7271                                                   receiver channels       */
7272       __IM unsigned int I2S_TX_CHANNELS : 2;       /*!< [10..9] Returns the number of
7273                                               transmitter channels   */
7274       __IM unsigned int RESERVED1 : 5;             /*!< [15..11] Reserved1         */
7275       __IM unsigned int I2S_TX_WORDSIZE_0 : 3;     /*!< [18..16] Returns the value of
7276                                               word size of transmitter channel
7277                                                      0 */
7278       __IM unsigned int I2S_TX_WORDSIZE_1 : 3;     /*!< [21..19] Returns the value of
7279                                               word size of transmitter channel
7280                                                      1 */
7281       __IM unsigned int I2S_TX_WORDSIZE_2 : 3;     /*!< [24..22] Returns the value of
7282                                               word size of transmitter channel
7283                                                      2 */
7284       __IM unsigned int I2S_TX_WORDSIZE_3 : 3;     /*!< [27..25] Returns the value of
7285                                               word size of transmitter channel
7286                                                      3 */
7287       __IM unsigned int RESERVED2 : 4;             /*!< [31..28] Reserved2         */
7288     } I2S_COMP_PARAM_1_b;
7289   };
7290 
7291   union {
7292     __IM unsigned int I2S_COMP_VERSION_REG; /*!< (@ 0x000001F8) Component Version ID */
7293 
7294     struct {
7295       __IM unsigned int I2S_COMP_VERSION : 32; /*!< [31..0] Return the component
7296                                               version(1.02) */
7297     } I2S_COMP_VERSION_REG_b;
7298   };
7299 
7300   union {
7301     __IM unsigned int I2S_COMP_TYPE_REG; /*!< (@ 0x000001FC) Component Type */
7302 
7303     struct {
7304       __IM unsigned int I2S_COMP_TYPE : 32; /*!< [31..0] Return the component type */
7305     } I2S_COMP_TYPE_REG_b;
7306   };
7307 } I2S0_Type; /*!< Size = 512 (0x200) */
7308 
7309 /* ===========================================================================================================================
7310  */
7311 /* ================                                          IID_AES
7312  * ================ */
7313 /* ===========================================================================================================================
7314  */
7315 
7316 /**
7317  * @brief The AES module provides AES encoding and decoding functionality. It
7318  * can be used in a microprocessor based environment (IID_AES)
7319  */
7320 
7321 typedef struct { /*!< (@ 0x20480500) IID_AES Structure */
7322 
7323   union {
7324     __IOM unsigned int AES_KCR; /*!< (@ 0x00000000) AES Key Control register */
7325 
7326     struct {
7327       __IOM unsigned int AES_KEY_CHNG_REQ : 1; /*!< [0..0] Programming 1 clears the current key
7328                                    and starts a request a for a new key
7329                                    Auto-reverts to 0 as soon as the request is
7330                                    accepted */
7331       __IOM unsigned int AES_KEY_SIZE : 1;     /*!< [1..1] Size of the AES key 0:
7332                                           128-bit 1: 256-bit */
7333       __IM unsigned int : 5;
7334       __IOM unsigned int AES_KEY_SRC : 1; /*!< [7..7] Source of the AES key 0:
7335                                          Interface 1: Register */
7336       __IM unsigned int : 24;
7337     } AES_KCR_b;
7338   };
7339 
7340   union {
7341     __IOM unsigned int AES_MODE_REG; /*!< (@ 0x00000004) AES Mode register */
7342 
7343     struct {
7344       __IOM unsigned int AES_MODE : 8; /*!< [7..0] The AES Mode register defines
7345                                       which mode of AES is used.           */
7346       __IM unsigned int : 24;
7347     } AES_MODE_REG_b;
7348   };
7349 
7350   union {
7351     __IOM unsigned int AES_ACT_REG; /*!< (@ 0x00000008) AES Action register */
7352 
7353     struct {
7354       __IOM unsigned int AES_ACTION : 2; /*!< [1..0] The AES Mode register defines
7355                                         which mode of AES is used.           */
7356       __IM unsigned int : 30;
7357     } AES_ACT_REG_b;
7358   };
7359   __IM unsigned int RESERVED[5];
7360 
7361   union {
7362     __IM unsigned int AES_SR_REG; /*!< (@ 0x00000020) AES Status register */
7363 
7364     struct {
7365       __IM unsigned int AES_BUSY : 1; /*!< [0..0] Indicates that the AES core is
7366                                      processing data                     */
7367       __IM unsigned int : 1;
7368       __IM unsigned int AES_CLEAR_DONE : 1;  /*!< [2..2] Indicates that the Clear
7369                                             action is finished  */
7370       __IM unsigned int AES_KEY_PRESENT : 1; /*!< [3..3] Indicates that the Clear
7371                                             action is finished */
7372       __IM unsigned int : 1;
7373       __IM unsigned int AES_KEY_REQ : 1;  /*!< [5..5] Indicates that a key must be
7374                                          provided                              */
7375       __IM unsigned int AES_DATA_REQ : 1; /*!< [6..6] Indicates that data must be
7376                                          provided */
7377       __IM unsigned int AES_DATA_AV : 1;  /*!< [7..7] Indicates that data is available */
7378       __IM unsigned int : 24;
7379     } AES_SR_REG_b;
7380   };
7381   __IM unsigned int RESERVED1[7];
7382 
7383   union {
7384     __OM unsigned int AES_KEY_REG; /*!< (@ 0x00000040) The AES Key register is used
7385                                   to program a key into the AES module. */
7386 
7387     struct {
7388       __OM unsigned int AES_KEY : 32; /*!< [31..0] 4 writes of 32 bits make up the 128-bit key
7389                            for AES, 8 writes make up the 256-bit key */
7390     } AES_KEY_REG_b;
7391   };
7392 
7393   union {
7394     __OM unsigned int AES_DIN_REG; /*!< (@ 0x00000044) AES Data In register */
7395 
7396     struct {
7397       __OM unsigned int AES_DIN : 32; /*!< [31..0] Data for encoding or decoding, 4 writes of
7398                            32 bits make up a 128-bit data word */
7399     } AES_DIN_REG_b;
7400   };
7401 
7402   union {
7403     __IM unsigned int AES_DOUT_REG; /*!< (@ 0x00000048) AES Data out register */
7404 
7405     struct {
7406       __IM unsigned int AES_DOUT : 32; /*!< [31..0] Result from encoding or decoding, 4 reads
7407                             of 32 bits make up a 128-bit data word */
7408     } AES_DOUT_REG_b;
7409   };
7410   __IM unsigned int RESERVED2[36];
7411 
7412   union {
7413     __OM unsigned int AES_IF_SR_C_REG; /*!< (@ 0x000000DC) AES Interface Status
7414                                       Clear register                        */
7415 
7416     struct {
7417       __OM unsigned int IFB_ERROR : 1; /*!< [0..0] Clears the if_error bit */
7418       __IM unsigned int : 31;
7419     } AES_IF_SR_C_REG_b;
7420   };
7421 
7422   union {
7423     __IM unsigned int AES_IF_SR_REG; /*!< (@ 0x000000E0) AES Interface Status register */
7424 
7425     struct {
7426       __IM unsigned int IF_ERROR : 1; /*!< [0..0] Indicates that an interface error
7427                                      has occurred                     */
7428       __IM unsigned int : 31;
7429     } AES_IF_SR_REG_b;
7430   };
7431 
7432   union {
7433     __IOM unsigned int AES_TEST_REG; /*!< (@ 0x000000E4) AES Test register */
7434 
7435     struct {
7436       __IOM unsigned int AES_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_aes
7437                                              module and runs a BIST */
7438       __IM unsigned int : 3;
7439       __IOM unsigned int AES_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or
7440                                               finishing up */
7441       __IOM unsigned int AES_BIST_ACTIVE : 1;  /*!< [5..5] Indicates that the BIST is
7442                                              running */
7443       __IOM unsigned int AES_BIST_OK : 1;      /*!< [6..6] Indicates that the BIST has passed */
7444       __IOM unsigned int AES_BIST_ERROR : 1;   /*!< [7..7] Indicates that the BIST has
7445                                             failed */
7446       __IM unsigned int : 24;
7447     } AES_TEST_REG_b;
7448   };
7449   __IM unsigned int RESERVED3[6];
7450 
7451   union {
7452     __IM unsigned int AES_VER_REG; /*!< (@ 0x00000100) AES Version register */
7453 
7454     struct {
7455       __IM unsigned int AES_VERSION : 32; /*!< [31..0] Version of iid_aes */
7456     } AES_VER_REG_b;
7457   };
7458 } IID_AES_Type; /*!< Size = 260 (0x104) */
7459 
7460 /* ===========================================================================================================================
7461  */
7462 /* ================                                          IID_QK
7463  * ================ */
7464 /* ===========================================================================================================================
7465  */
7466 
7467 /**
7468  * @brief The purpose of Quiddikey is to provide secure key storage without
7469  * storing the key. (IID_QK)
7470  */
7471 
7472 typedef struct { /*!< (@ 0x20480600) IID_QK Structure */
7473 
7474   union {
7475     __OM unsigned int QK_CR_REG; /*!< (@ 0x00000000) Quiddikey Control register.The
7476                                 Quiddikey Control register defines which command
7477                                 must be executed next. */
7478 
7479     struct {
7480       __OM unsigned int QK_ZEROIZE : 1; /*!< [0..0] Begin Zeroize operation and go
7481                                        to Error state                      */
7482       __OM unsigned int QK_ENROLL : 1;  /*!< [1..1] Begin Enroll operation  */
7483       __OM unsigned int QK_START : 1;   /*!< [2..2] Begin Start operation   */
7484       __OM unsigned int QK_SET_IK : 1;  /*!< [3..3] Begin Set Intrinsic Key operation */
7485       __OM unsigned int QK_SET_UK : 1;  /*!< [4..4] Begin Set User Key operation */
7486       __OM unsigned int QK_SET_XK : 1;  /*!< [5..5] Begin Set External Key operation */
7487       __OM unsigned int QK_GET_KEY : 1; /*!< [6..6] Begin Get Key operation */
7488       __IM unsigned int : 25;
7489     } QK_CR_REG_b;
7490   };
7491 
7492   union {
7493     __IOM unsigned int QK_KIDX_REG; /*!< (@ 0x00000004) The Quiddikey Key Index register
7494                         defines the key index for the next set_key command */
7495 
7496     struct {
7497       __IOM unsigned int QK_KEY_INDEX : 4; /*!< [3..0] Key index for Set Key operations */
7498       __IM unsigned int : 28;
7499     } QK_KIDX_REG_b;
7500   };
7501 
7502   union {
7503     __IOM unsigned int QK_KSZ_REG; /*!< (@ 0x00000008) Quiddikey Key Size register */
7504 
7505     struct {
7506       __IOM unsigned int QK_KEY_SIZE : 6; /*!< [5..0] Key size for Set Key operations */
7507       __IM unsigned int : 26;
7508     } QK_KSZ_REG_b;
7509   };
7510 
7511   union {
7512     __IOM unsigned int QK_KT_REG; /*!< (@ 0x0000000C) Quiddikey Key Size register */
7513 
7514     struct {
7515       __IOM unsigned int QK_KEY_TARGET : 1; /*!< [0..0] Target of reconstructed key */
7516       __IM unsigned int : 31;
7517     } QK_KT_REG_b;
7518   };
7519   __IM unsigned int RESERVED[4];
7520 
7521   union {
7522     __IM unsigned int QK_SR_REG; /*!< (@ 0x00000020) Quiddikey Status register */
7523 
7524     struct {
7525       __IM unsigned int QK_BUSY : 1;   /*!< [0..0] Indicates that operation is in progress */
7526       __IM unsigned int QK_OK : 1;     /*!< [1..1] Last operation was successful    */
7527       __IM unsigned int QK_ERROR : 1;  /*!< [2..2] Quiddikey is in the Error state
7528                                      and no operations can be performed */
7529       __IM unsigned int QK_XO_AV : 1;  /*!< [3..3] Next part of XKPD is available            */
7530       __IM unsigned int QK_KI_REQ : 1; /*!< [4..4] Request for next part of key */
7531       __IM unsigned int QK_KO_AV : 1;  /*!< [5..5] Next part of key is available  */
7532       __IM unsigned int QK_CI_REQ : 1; /*!< [6..6] Request for next part of AC/KC */
7533       __IM unsigned int QK_CO_AV : 1;  /*!< [7..7] Next part of AC/KC is available */
7534       __IM unsigned int : 24;
7535     } QK_SR_REG_b;
7536   };
7537   __IM unsigned int RESERVED1;
7538 
7539   union {
7540     __IM unsigned int QK_AR_REG; /*!< (@ 0x00000028) Quiddikey allow register */
7541 
7542     struct {
7543       __IM unsigned int QK_ALLOW_ENROLL : 1;  /*!< [0..0] Enroll operation is allowed */
7544       __IM unsigned int QK_ALLOW_START : 1;   /*!< [1..1] Start operation is allowed */
7545       __IM unsigned int QK_ALLOW_SET_KEY : 1; /*!< [2..2] Set Key operations are allowed */
7546       __IM unsigned int QK_ALLOW_GET_KEY : 1; /*!< [3..3] Get Key operation is allowed */
7547       __IM unsigned int : 3;
7548       __IM unsigned int QK_ALLOW_BIST : 1; /*!< [7..7] BIST is allowed to be started */
7549       __IM unsigned int : 24;
7550     } QK_AR_REG_b;
7551   };
7552   __IM unsigned int RESERVED2[5];
7553 
7554   union {
7555     __IOM unsigned int QK_KI_REG; /*!< (@ 0x00000040) Quiddikey Key Input register */
7556 
7557     struct {
7558       __IOM unsigned int QK_KI : 32; /*!< [31..0] Key input data */
7559     } QK_KI_REG_b;
7560   };
7561 
7562   union {
7563     __IOM unsigned int QK_CI_REG; /*!< (@ 0x00000044) Quiddikey Code Input register */
7564 
7565     struct {
7566       __IOM unsigned int QK_CI : 32; /*!< [31..0] AC/KC input data */
7567     } QK_CI_REG_b;
7568   };
7569 
7570   union {
7571     __IM unsigned int QK_CO_REG; /*!< (@ 0x00000048) Quiddikey Code Output register */
7572 
7573     struct {
7574       __IM unsigned int QK_CO : 32; /*!< [31..0] AC/KC output data */
7575     } QK_CO_REG_b;
7576   };
7577 
7578   union {
7579     __IM unsigned int QK_XO_REG; /*!< (@ 0x0000004C) Quiddikey XKPD Output register */
7580 
7581     struct {
7582       __IM unsigned int QK_XO : 32; /*!< [31..0] XKPD output data */
7583     } QK_XO_REG_b;
7584   };
7585   __IM unsigned int RESERVED3[4];
7586 
7587   union {
7588     __IM unsigned int QK_KO_IDX_REG; /*!< (@ 0x00000060) Quiddikey Key Output Index
7589                                     register                        */
7590 
7591     struct {
7592       __IM unsigned int qk_ko_index : 4; /*!< [3..0] Key index for the key that is currently
7593                               output via the Key Output register */
7594       __IM unsigned int : 28;
7595     } QK_KO_IDX_REG_b;
7596   };
7597 
7598   union {
7599     __IM unsigned int QK_KO_REG; /*!< (@ 0x00000064) Quiddikey Code Output register */
7600 
7601     struct {
7602       __IM unsigned int QK_KO : 32; /*!< [31..0] Key output data */
7603     } QK_KO_REG_b;
7604   };
7605   __IM unsigned int RESERVED4[29];
7606 
7607   union {
7608     __IM unsigned int QK_IF_SR_C_REG; /*!< (@ 0x000000DC) Quiddikey Interface Status
7609                                      register                        */
7610 
7611     struct {
7612       __IM unsigned int IF_ERROR : 1; /*!< [0..0] Clears the if_error bit */
7613       __IM unsigned int : 31;
7614     } QK_IF_SR_C_REG_b;
7615   };
7616 
7617   union {
7618     __IM unsigned int QK_IF_SR_REG; /*!< (@ 0x000000E0) Quiddikey Interface Status
7619                                    register                        */
7620 
7621     struct {
7622       __IM unsigned int IF_ERROR : 1; /*!< [0..0] Indicates that an interface error
7623                                      has occurred                     */
7624       __IM unsigned int : 31;
7625     } QK_IF_SR_REG_b;
7626   };
7627 
7628   union {
7629     __IOM unsigned int QK_TEST_REG; /*!< (@ 0x000000E4) QK Test register */
7630 
7631     struct {
7632       __IOM unsigned int QK_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_quiddikey
7633                                             module and runs a BIST */
7634       __IM unsigned int : 3;
7635       __IOM unsigned int QK_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or
7636                                              finishing up */
7637       __IOM unsigned int QK_BIST_ACTIVE : 1;  /*!< [5..5] Indicates that the BIST is
7638                                              running  */
7639       __IOM unsigned int QK_BIST_OK : 1;      /*!< [6..6] Indicates that the BIST has passed */
7640       __IOM unsigned int QK_BIST_ERROR : 1;   /*!< [7..7] Indicates that the BIST has failed */
7641       __IM unsigned int : 24;
7642     } QK_TEST_REG_b;
7643   };
7644   __IM unsigned int RESERVED5[6];
7645 
7646   union {
7647     __IM unsigned int QK_VER_REG; /*!< (@ 0x00000100) QK Version register */
7648 
7649     struct {
7650       __IM unsigned int QK_VERSION : 32; /*!< [31..0] Version of iid_qk */
7651     } QK_VER_REG_b;
7652   };
7653 } IID_QK_Type; /*!< Size = 260 (0x104) */
7654 
7655 /* ===========================================================================================================================
7656  */
7657 /* ================                                         IID_RPINE
7658  * ================ */
7659 /* ===========================================================================================================================
7660  */
7661 
7662 /**
7663  * @brief none (IID_RPINE)
7664  */
7665 
7666 typedef struct { /*!< (@ 0x20480400) IID_RPINE Structure */
7667 
7668   union {
7669     __IOM unsigned int IID_BIST_CTRL_REG; /*!< (@ 0x00000000) Quiddikey Control register.The
7670                               Quiddikey Control register defines which command
7671                               must be executed next. */
7672 
7673     struct {
7674       __IOM unsigned int QK_BIST_ENABLE : 1;  /*!< [0..0] none  */
7675       __IOM unsigned int AES_BIST_ENABLE : 1; /*!< [1..1] none */
7676       __IOM unsigned int KH_BIST_ENABLE : 1;  /*!< [2..2] none  */
7677       __IM unsigned int : 29;
7678     } IID_BIST_CTRL_REG_b;
7679   };
7680 
7681   union {
7682     __IOM unsigned int IID_BIST_STATUS_REG; /*!< (@ 0x00000004) none */
7683 
7684     struct {
7685       __IOM unsigned int QK_BIST_ACTIVE : 1;   /*!< [0..0] none */
7686       __IOM unsigned int QK_BIST_ERROR : 1;    /*!< [1..1] Indicates that the BIST has failed */
7687       __IOM unsigned int QK_BIST_OK : 1;       /*!< [2..2] Indicates that the BIST has passed */
7688       __IOM unsigned int QK_BIST_RUNNING : 1;  /*!< [3..3] Indicates that the BIST is
7689                                              running */
7690       __IOM unsigned int AES_BIST_ACTIVE : 1;  /*!< [4..4] none */
7691       __IOM unsigned int AES_BIST_ERROR : 1;   /*!< [5..5] none  */
7692       __IOM unsigned int AES_BIST_OK : 1;      /*!< [6..6] Indicates that the BIST has passed */
7693       __IOM unsigned int AES_BIST_RUNNING : 1; /*!< [7..7] Indicates that the BIST
7694                                               is running */
7695       __IOM unsigned int KH_BIST_STATUS : 1;   /*!< [8..8] none   */
7696       __IM unsigned int : 23;
7697     } IID_BIST_STATUS_REG_b;
7698   };
7699 
7700   union {
7701     __IOM unsigned int IID_CTRL_REG; /*!< (@ 0x00000008) none */
7702 
7703     struct {
7704       __IOM unsigned int AES_MAX_KEY_SIZE : 1; /*!< [0..0] 1 256 bit key, 0 128 bit key */
7705       __IOM unsigned int SOURCE_KEY_KH : 1;    /*!< [1..1] When set KH will source the key to AES
7706                                 engine. When this is not QK key output is
7707                                 connected to AES key input */
7708       __IOM unsigned int LATCH_KEY_KH : 1;     /*!< [2..2] When set KH will latch the key given by
7709                                QK. When this is not QK key output is connected
7710                                to AES key input                        */
7711       __IOM unsigned int KH_RESET_N : 1;       /*!< [3..3] 0 KH will be in reset 1 Out of reset */
7712       __IOM unsigned int KH_KEY_SIZE : 1;      /*!< [4..4] 0 128 bit key 1 256 bit key
7713                                          This is used by KH */
7714       __IOM unsigned int KH_CLOCK_RATIO : 3;   /*!< [7..5] Indicates the division factor to be
7715                                  used for generating kh_clk. */
7716       __IM unsigned int : 24;
7717     } IID_CTRL_REG_b;
7718   };
7719 
7720   union {
7721     __IOM unsigned int WKE_CTRL_REG; /*!< (@ 0x0000000C) none */
7722 
7723     struct {
7724       __IOM unsigned int ENABLE_WKE : 1;    /*!< [0..0] When WKE will be enabled. This
7725                                         is a self clearing bit.
7726                                                    Once enabled WKE can not be
7727                                         disabled till process is done */
7728       __IOM unsigned int WKE_KEY_SIZE : 1;  /*!< [1..1] 0 128 bit size 1 256 bit size */
7729       __IOM unsigned int WKE_FLUSH : 1;     /*!< [2..2] When set, WKE will flush out the data from
7730                             AES. When WEK is active,  firmware reads to AES
7731                             engine are masked. This gets cleared once four
7732                             dwords are read from AES                      */
7733       __IOM unsigned int WKE_COMPARE : 1;   /*!< [3..3] When set, WKE will compare the data from
7734                               AES engine with the data provided by firmware */
7735       __IOM unsigned int WKE_SET_KEY : 1;   /*!< [4..4] This has to be set after key
7736                                            available from AES   */
7737       __IOM unsigned int KEY_CODE_DONE : 1; /*!< [5..5] This has to be set after
7738                                            reading key code */
7739       __IM unsigned int : 26;
7740     } WKE_CTRL_REG_b;
7741   };
7742   __IM unsigned int RESERVED;
7743 
7744   union {
7745     __IOM unsigned int IID_AES_CTRL_REG; /*!< (@ 0x00000014) none */
7746 
7747     struct {
7748       __IOM unsigned int KEY_REQ_IN_DMA_PATH : 1;         /*!< [0..0] Include key req in dma path. With
7749                                      this KEY Also can be loaded using DMA. */
7750       __IOM unsigned int AES_MAX_KEY_SIZE_FRM_REG : 1;    /*!< [1..1] This is valid
7751                                                      only when
7752                                                      aes_max_key_size_frm_reg_en
7753                                                      is set. */
7754       __IOM unsigned int AES_MAX_KEY_SIZE_FRM_REG_EN : 1; /*!< [2..2] When set, WKE will flush
7755                                           out the data from AES. When WEK is
7756                                           active,  firmware reads to AES engine
7757                                           are masked. This gets cleared once
7758                                           four dwords are read from AES */
7759       __IOM unsigned int OTP_KEY_LOADING : 1;             /*!< [3..3] When set, WKE will compare
7760                                              the data from AES engine with the
7761                                              data provided by firmware */
7762       __IM unsigned int : 28;
7763     } IID_AES_CTRL_REG_b;
7764   };
7765 
7766   union {
7767     __IM unsigned int IID_AES_STS_REG; /*!< (@ 0x00000018) none */
7768 
7769     struct {
7770       __IM unsigned int DIN_FIFO_FULL : 1;   /*!< [0..0] Input data fifo full indication */
7771       __IM unsigned int DOUT_FIFO_EMPTY : 1; /*!< [1..1] Output data fifo empty
7772                                             indication */
7773       __IM unsigned int : 30;
7774     } IID_AES_STS_REG_b;
7775   };
7776   __IM unsigned int RESERVED1;
7777 
7778   union {
7779     __IOM unsigned int WKE_STATUS_REG; /*!< (@ 0x00000020) none */
7780 
7781     struct {
7782       __IOM unsigned int WKE_ACTIVE : 1;               /*!< [0..0] Will be high when WKE is active */
7783       __IOM unsigned int WKE_KEY_FEED_IN_PROGRESS : 1; /*!< [1..1] Will be high when WKE is
7784                                            feeding key to AES engine */
7785       __IOM unsigned int WKE_FLUSH_IN_PROGRESS : 1;    /*!< [2..2] Will be high when WKE flushing
7786                                         out the data from AES               */
7787       __IOM unsigned int WKE_COMPARE_IN_PROGRESS : 1;  /*!< [3..3] Will be high when WKE is
7788                                           comparing the data from AES */
7789       __IOM unsigned int WKE_SET_KEY_IN_PROGRESS : 1;  /*!< [4..4] Will be high when WKE is
7790                                            doing set key operation with  QK  */
7791       __IOM unsigned int WKE_KEY_READY : 1;            /*!< [5..5] Firmware has to load the
7792                                            authentication, which will be
7793                                            compared with AES output, when this
7794                                            bit is low */
7795       __IOM unsigned int WKE_CMP_DATA_READY : 1;       /*!< [6..6] Firmware has to load
7796                                                 the authentication, which will
7797                                                 be compared with AES output,
7798                                                 when this bit is low */
7799       __IOM unsigned int WKE_COMPARE_FAIL : 1;         /*!< [7..7] This bit will be set when
7800                                    authentication data comparison fails */
7801       __IM unsigned int : 24;
7802     } WKE_STATUS_REG_b;
7803   };
7804   __IM unsigned int RESERVED2;
7805   __IOM unsigned int WKE_DATA_REG; /*!< (@ 0x00000028) none */
7806 } IID_RPINE_Type;                  /*!< Size = 44 (0x2c)              */
7807 
7808 /* ===========================================================================================================================
7809  */
7810 /* ================                                            CT0
7811  * ================ */
7812 /* ===========================================================================================================================
7813  */
7814 
7815 /**
7816   * @brief Configurable timer is used in counting clocks, events and states with
7817   reference clock external clock and system clock (CT0)
7818   */
7819 
7820 typedef struct { /*!< (@ 0x45060000) CT0 Structure */
7821 
7822   union {
7823     __IOM unsigned int CT_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set
7824                                            register */
7825 
7826     struct {
7827       __IOM unsigned int COUNTER_IN_32_BIT_MODE : 1;        /*!< [0..0] Counter_1 and Counter_0 will
7828                                          be merged and used as a single 32 bit
7829                                          counter */
7830       __IOM unsigned int SOFT_RESET_COUNTER_0_FRM_REG : 1;  /*!< [1..1] This is applied to 32
7831                                                bits of counter only when the
7832                                                counter is in 32 bit counter mode
7833                                                otherwise this will be applied
7834                                                        to only lower 16 bits of
7835                                                counter */
7836       __IOM unsigned int PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32
7837                                                 bits of counter only when the
7838                                                 counter is in 32 bit counter
7839                                                 mode  otherwise this will be
7840                                                 applied
7841                                                        to only lower 16 bits of
7842                                                 counter */
7843       __IOM unsigned int COUNTER_0_TRIG_FRM_REG : 1;        /*!< [3..3] This enables the
7844                                                     counter to run/active */
7845       __IOM unsigned int COUNTER_0_UP_DOWN : 2;             /*!< [5..4] This enables the counter to run in
7846                                     up/down/up-down/down-up directions */
7847       __IOM unsigned int COUNTER_0_SYNC_TRIG : 1;           /*!< [6..6] This is applied to 32 bits of
7848                                           counter only when the counter     is in 32 bit
7849                                           counter mode otherwise this will be
7850                                           applied     to only lower 16 bits of counter.
7851                                           This enables the counter     to run/active
7852                                           when sync is found.     */
7853       __IOM unsigned int BUF_REG_0_EN : 1;                  /*!< [7..7] Buffer register gets enabled
7854                                           for MATCH REG. MATCH_BUF_REG is always
7855                                           available and whenever this bit is set
7856                                           only, gets copied to MATCH REG. */
7857       __IOM unsigned int RESERVED1 : 9;                     /*!< [16..8] Reserved1    */
7858       __IOM unsigned int SOFT_RESET_COUNTER_1_FRM_REG : 1;  /*!< [17..17] This resets the
7859                                                counter on the write */
7860       __IOM unsigned int PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the
7861                                                 counter on the write */
7862       __IOM unsigned int COUNTER_1_TRIG_FRM : 1;            /*!< [19..19] This enables the
7863                                                 counter to run/active */
7864       __IOM unsigned int COUNTER_1_UP_DOWN : 2;             /*!< [21..20] This enables the counter to run
7865                                     in upward direction              */
7866       __IOM unsigned int COUNTER_1_SYNC_TRIG : 1;           /*!< [22..22] This is applied to 32 bits of
7867                                       counter only when the counter is in 32 bit
7868                                       counter mode otherwise this will be
7869                                           applied to only lower 16 bits of
7870                                       counter. This enables the counter to
7871                                       run/active when sync is found. */
7872       __IOM unsigned int BUF_REG_1_EN : 1;                  /*!< [23..23] Buffer register gets enabled for MATCH
7873                                REG. MATCH_BUF_REG is always available and
7874                                whenever this bit is set only, gets copied to
7875                                MATCH REG. */
7876       __IOM unsigned int RESERVED2 : 8;                     /*!< [31..24] Reserved2 */
7877     } CT_GEN_CTRL_SET_REG_b;
7878   };
7879 
7880   union {
7881     __IOM unsigned int CT_GEN_CTRL_RESET_REG; /*!< (@ 0x00000004) General control
7882                                              reset register */
7883 
7884     struct {
7885       __IOM unsigned int COUNTER_IN_32_BIT_MODE : 1;        /*!< [0..0] Counter_1 and Counter_0 will
7886                                          be merged and used as a single 32 bit
7887                                          counter */
7888       __IM unsigned int RESERVED1 : 1;                      /*!< [1..1] Reserved1    */
7889       __IOM unsigned int PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32
7890                                                 bits of counter only when the
7891                                                 counter is in 32 bit counter
7892                                                 mode  otherwise this will be
7893                                                 applied
7894                                                        to only lower 16 bits of
7895                                                 counter */
7896       __IM unsigned int RESERVED2 : 1;                      /*!< [3..3] Reserved2           */
7897       __IOM unsigned int COUNTER_0_UP_DOWN : 2;             /*!< [5..4] This enables the counter to run in
7898                                     up/down/up-down/down-up directions */
7899       __IM unsigned int RESERVED3 : 1;                      /*!< [6..6] Reserved3     */
7900       __IOM unsigned int BUF_REG_0_EN : 1;                  /*!< [7..7] Buffer register gets enabled
7901                                           for MATCH REG. MATCH_BUF_REG is always
7902                                           available and whenever this bit is set
7903                                           only, gets copied to MATCH REG. */
7904       __IM unsigned int RESERVED4 : 9;                      /*!< [16..8] Reserved4     */
7905       __IM unsigned int RESERVED5 : 1;                      /*!< [17..17] Reserved5     */
7906       __IOM unsigned int PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the
7907                                                 counter on the write */
7908       __IM unsigned int RESERVED6 : 1;                      /*!< [19..19] Reserved6           */
7909       __IOM unsigned int COUNTER_1_UP_DOWN : 2;             /*!< [21..20] This enables the counter to run
7910                                       in upward direction              */
7911       __IM unsigned int RESERVED7 : 1;                      /*!< [22..22] Reserved7 */
7912       __IOM unsigned int BUF_REG_1_EN : 1;                  /*!< [23..23] Buffer register gets enabled for MATCH
7913                                REG. MATCH_BUF_REG is always available and
7914                                whenever this bit is set only, gets copied to
7915                                MATCH REG. */
7916       __IM unsigned int RESERVED8 : 8;                      /*!< [31..24] Reserved8 */
7917     } CT_GEN_CTRL_RESET_REG_b;
7918   };
7919 
7920   union {
7921     __IM unsigned int CT_INTR_STS; /*!< (@ 0x00000008) Interrupt status */
7922 
7923     struct {
7924       __IM unsigned int INTR_0_L : 1;            /*!< [0..0] Indicates the FIFO full signal of
7925                                      channel-0                        */
7926       __IM unsigned int FIFO_0_FULL_L : 1;       /*!< [1..1] Indicates the FIFO full
7927                                                 signal of channel-0       */
7928       __IM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Counter 0 hit zero in
7929                                                 active mode. */
7930       __IM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Counter 0 hit peak
7931                                                 (MATCH) in active mode. */
7932       __IM unsigned int RESERVED1 : 12;          /*!< [15..4] Reserved1          */
7933       __IM unsigned int INTR_1_L : 1;            /*!< [16..16] Indicates the FIFO full signal
7934                                      of channel-1                      */
7935       __IM unsigned int FIFO_1_FULL_L : 1;       /*!< [17..17] Indicates the FIFO full
7936                                           signal of channel-1 */
7937       __IM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Counter 1 hit zero in
7938                                                 active mode. */
7939       __IM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Counter 1 hit peak
7940                                                 (MATCH) in active mode. */
7941       __IM unsigned int RESERVED2 : 12;          /*!< [31..20] Reserved2          */
7942     } CT_INTR_STS_b;
7943   };
7944 
7945   union {
7946     __IOM unsigned int CT_INTR_MASK; /*!< (@ 0x0000000C) Interrupts mask */
7947 
7948     struct {
7949       __IOM unsigned int INTR_0_L : 1;            /*!< [0..0] Interrupt mask signal.      */
7950       __IOM unsigned int FIFO_0_FULL_L : 1;       /*!< [1..1] Interrupt mask signal. */
7951       __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt mask signal. */
7952       __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt mask signal.   */
7953       __IOM unsigned int RESERVED1 : 12;          /*!< [15..4] Reserved1 */
7954       __IOM unsigned int INTR_1_L : 1;            /*!< [16..16] Interrupt mask signal.   */
7955       __IOM unsigned int FIFO_1_FULL_L : 1;       /*!< [17..17] Interrupt mask signal. */
7956       __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt mask signal. */
7957       __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt mask signal.   */
7958       __IOM unsigned int RESERVED2 : 12;          /*!< [31..20] Reserved2 */
7959     } CT_INTR_MASK_b;
7960   };
7961 
7962   union {
7963     __IOM unsigned int CT_INTER_UNMASK; /*!< (@ 0x00000010) Interrupts unmask */
7964 
7965     struct {
7966       __IOM unsigned int INTR_0_L : 1;            /*!< [0..0] Interrupt unmask signal. */
7967       __IOM unsigned int FIFO_0_FULL_L : 1;       /*!< [1..1] Interrupt unmask signal. */
7968       __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt unmask signal. */
7969       __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt unmask signal.  */
7970       __IM unsigned int RESERVED1 : 12;           /*!< [15..4] Reserved1 */
7971       __IOM unsigned int INTR_1_L : 1;            /*!< [16..16] Interrupt unmask signal.  */
7972       __IOM unsigned int FIFO_1_FULL_L : 1;       /*!< [17..17] Interrupt unmask signal */
7973       __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt unmask signal. */
7974       __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt unmask signal.  */
7975       __IM unsigned int RESERVED2 : 12;           /*!< [31..20] Reserved2 */
7976     } CT_INTER_UNMASK_b;
7977   };
7978 
7979   union {
7980     __IOM unsigned int CT_INTR_ACK; /*!< (@ 0x00000014) Interrupt clear/ack register */
7981 
7982     struct {
7983       __IOM unsigned int INTR_0_L : 1;            /*!< [0..0] Interrupt ack signal.      */
7984       __IOM unsigned int FIFO_0_FULL_L : 1;       /*!< [1..1] Interrupt ack signal. */
7985       __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt ack signal. */
7986       __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt ack signal.      */
7987       __IM unsigned int RESERVED1 : 12;           /*!< [15..4] Reserved1     */
7988       __IOM unsigned int INTR_1_L : 1;            /*!< [16..16] Interrupt ack signal.      */
7989       __IOM unsigned int FIFO_1_FULL_L : 1;       /*!< [17..17] Interrupt ack signal. */
7990       __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt ack signal. */
7991       __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt ack signal.   */
7992       __IOM unsigned int RESERVED2 : 12;          /*!< [31..20] Reserved2 */
7993     } CT_INTR_ACK_b;
7994   };
7995 
7996   union {
7997     __IOM unsigned int CT_MATCH_REG; /*!< (@ 0x00000018) Match value register */
7998 
7999     struct {
8000       __IOM unsigned int COUNTER_0_MATCH : 16; /*!< [15..0] This will be used as
8001                                               lower match */
8002       __IOM unsigned int COUNTER_1_MATCH : 16; /*!< [31..16] This will be used as
8003                                               upper match */
8004     } CT_MATCH_REG_b;
8005   };
8006 
8007   union {
8008     __IOM unsigned int CT_MATCH_BUF_REG; /*!< (@ 0x0000001C) Match Buffer register */
8009 
8010     struct {
8011       __IOM unsigned int COUNTER_0_MATCH_BUF : 16; /*!< [15..0] This gets copied to MATCH
8012                                        register if bug_reg_0_en is set.  Copying
8013                                        is done when counter 0 is active and hits
8014                                           0. */
8015       __IOM unsigned int COUNTER_1_MATCH_BUF : 16; /*!< [31..16] This gets copied to MATCH
8016                                        register if bug_reg_1_en is set. Copying
8017                                        is done when counter 1 is active and hits
8018                                           0. */
8019     } CT_MATCH_BUF_REG_b;
8020   };
8021 
8022   union {
8023     __IM unsigned int CT_CAPTURE_REG; /*!< (@ 0x00000020) Capture Register */
8024 
8025     struct {
8026       __IM unsigned int COUNTER_0_CAPTURE : 16; /*!< [15..0] This is a latched value of
8027                                      counter lower part when the selected
8028                                      capture_event occurs */
8029       __IM unsigned int COUNTER_1_CAPTURE : 16; /*!< [31..16] This is a latched value of
8030                                      counter upper part when the selected
8031                                      capture_event occurs */
8032     } CT_CAPTURE_REG_b;
8033   };
8034 
8035   union {
8036     __IOM unsigned int CT_COUNTER_REG; /*!< (@ 0x00000024) Counter Register */
8037 
8038     struct {
8039       __IM unsigned int COUNTER0 : 16; /*!< [15..0] This holds the value of counter-0 */
8040       __IM unsigned int COUNTER1 : 16; /*!< [31..16] This holds the value of counter-1 */
8041     } CT_COUNTER_REG_b;
8042   };
8043 
8044   union {
8045     __IOM unsigned int CT_OCU_CTRL_REG; /*!< (@ 0x00000028) OCU control register */
8046 
8047     struct {
8048       __IOM unsigned int OUTPUT_IS_OCU_0 : 1;        /*!< [0..0] Indicates whether the output is in
8049                                   OCU mode or not for channel-0 */
8050       __IOM unsigned int SYNC_WITH_0 : 3;            /*!< [3..1] Indicates whether the other channel is in
8051                               sync with this channel */
8052       __IOM unsigned int OCU_0_DMA_MODE : 1;         /*!< [4..4] Indicates whether the OCU DMA mode is
8053                                  active or not for channel 0 */
8054       __IOM unsigned int OCU_0_MODE_8_16 : 1;        /*!< [5..5] Indicates whether entire 16 bits or
8055                                   only 8-bits of the channel 0 are used in OCU
8056                                   mode */
8057       __IOM unsigned int MAKE_OUTPUT_0_HIGH_SEL : 3; /*!< [8..6] Check counter ocus for
8058                                          possibilities. When this is hit
8059                                           output will be made high. */
8060       __IOM unsigned int MAKE_OUTPUT_0_LOW_SEL : 3;  /*!< [11..9] Check counter ocus for
8061                                         possibilities. When this is hit output
8062                                         will be made low. */
8063       __IOM unsigned int RESERVED1 : 4;              /*!< [15..12] Reserved1  */
8064       __IOM unsigned int OUTPUT_1_IS_OCU : 1;        /*!< [16..16] Indicates whether the output is in
8065                                   OCU mode or not for channel 1 */
8066       __IOM unsigned int SYNC_WITH_1 : 3;            /*!< [19..17] Indicates whether the other channel is
8067                               in sync with this channel */
8068       __IOM unsigned int OCU_1_DMA_MODE : 1;         /*!< [20..20] Indicates whether the OCU DMA mode
8069                                  is active or not for channel 1 */
8070       __IOM unsigned int OCU_1_MODE_8_16_MODE : 1;   /*!< [21..21] Indicates whether entire 16
8071                                        bits or only 8-bits of
8072                                         the channel 1 are used in OCU mode */
8073       __IOM unsigned int MAKE_OUTPUT_1_HIGH_SEL : 3; /*!< [24..22] Check counter ocus for
8074                                          possibilities. When this is
8075                                           hit output will be made high. */
8076       __IOM unsigned int MAKE_OUTPUT_1_LOW_SEL : 3;  /*!< [27..25] Check counter ocus for
8077                                         possibilities. When this is hit output
8078                                         will be made low. */
8079       __IOM unsigned int RESERVED2 : 4;              /*!< [31..28] Reserved2  */
8080     } CT_OCU_CTRL_REG_b;
8081   };
8082 
8083   union {
8084     __IOM unsigned int CT_OCU_COMPARE_REG; /*!< (@ 0x0000002C) OCU Compare Register */
8085 
8086     struct {
8087       __IOM unsigned int OCU_COMPARE_0_REG : 16; /*!< [15..0] Holds the threshold value of
8088                                      present OCU period which denotes the number
8089                                      of clock  cycles for which the OCU output
8090                                           should be considered (counter 0) */
8091       __IOM unsigned int OCU_COMPARE_1_REG : 16; /*!< [31..16] Holds the threshold value of
8092                                      present OCU period which denotes the number
8093                                      of clock  cycles for which the OCU output
8094                                           should be considered (counter 1) */
8095     } CT_OCU_COMPARE_REG_b;
8096   };
8097 
8098   union {
8099     __IOM unsigned int CT_OCU_COMPARE2_REG; /*!< (@ 0x00000030) OCU Compare2 Register */
8100 
8101     struct {
8102       __IOM unsigned int OCU_COMPARE2_0_REG : 16; /*!< [15..0] Holds the threshold
8103                                                  value of present OCU period2
8104                                                  which denotes the number of
8105                                                  clock  cycles for which the OCU
8106                                                  output should be considered
8107                                                  (counter 0) */
8108       __IOM unsigned int OCU_COMPARE2_1_REG : 16; /*!< [31..16] Holds the threshold
8109                                                  value of present OCU period2
8110                                                  which denotes the number of
8111                                                  clock  cycles for which the OCU
8112                                                  output should be considered
8113                                                  (counter 1) */
8114     } CT_OCU_COMPARE2_REG_b;
8115   };
8116 
8117   union {
8118     __IOM unsigned int CT_OCU_SYNC_REG; /*!< (@ 0x00000034) OCU Synchronization Register */
8119 
8120     struct {
8121       __IOM unsigned int OCU_SYNC_CHANNEL0_REG : 16; /*!< [15..0] Starting point of channel 0
8122                                          for synchronization purpose */
8123       __IOM unsigned int OCU_SYNC_CHANNEL1_REG : 16; /*!< [31..16] Starting point of channel 1
8124                                          for synchronization purpose          */
8125     } CT_OCU_SYNC_REG_b;
8126   };
8127 
8128   union {
8129     __IOM unsigned int CT_OCU_COMPARE_NXT_REG; /*!< (@ 0x00000038) PWM compare next
8130                                               register */
8131 
8132     struct {
8133       __IOM unsigned int OCU_COMPARE_NXT_COUNTER1 : 16; /*!< [15..0] OCU output should be high
8134                                             for counter 1 */
8135       __IOM unsigned int OCU_COMPARE_NXT_COUNTER0 : 16; /*!< [31..16] PWM output should be high
8136                                             for counter 0 */
8137     } CT_OCU_COMPARE_NXT_REG_b;
8138   };
8139 
8140   union {
8141     __IOM unsigned int CT_WFG_CTRL_REG; /*!< (@ 0x0000003C) WFG control register */
8142 
8143     struct {
8144       __IOM unsigned int MAKE_OUTPUT_0_TGL_0_SEL : 3; /*!< [2..0] Check the counter ocus
8145                                           possibilities for description for
8146                                           channel 0. */
8147       __IOM unsigned int MAKE_OUTPUT_0_TGL_1_SEL : 3; /*!< [5..3] Check the counter ocus
8148                                                 possibilities for description       for
8149                                                 channel 0.       */
8150       __IOM unsigned int RESERVED1 : 2;               /*!< [7..6] Reserved1          */
8151       __IOM unsigned int WFG_TGL_CNT_0_PEAK : 8;      /*!< [15..8] WFG mode output toggle
8152                                                 count clock for channel 0. */
8153       __IOM unsigned int MAKE_OUTPUT_1_TGL_0_SEL : 3; /*!< [18..16] Check the counter ocus
8154                                           possibilities for description for
8155                                           channel 1. */
8156       __IOM unsigned int MAKE_OUTPUT_1_TGL_1_SEL : 3; /*!< [21..19] Check the counter ocus
8157                                           possibilities for description for
8158                                           channel 1. */
8159       __IOM unsigned int RESERVED2 : 2;               /*!< [23..22] Reserved2    */
8160       __IOM unsigned int WFG_TGL_CNT_1_PEAK : 8;      /*!< [31..24] WFG mode output toggle count
8161                                      clock for channel 1                 */
8162     } CT_WFG_CTRL_REG_b;
8163   };
8164 
8165   union {
8166     __IOM unsigned int CT_OCU_COMPARE2_NXT_REG; /*!< (@ 0x00000040) PWM compare next
8167                                                register */
8168 
8169     struct {
8170       __IOM unsigned int OCU_COMPARE2_NXT_COUNTER0 : 16; /*!< [15..0] OCU output should be high
8171                                              for counter 1 */
8172       __IOM unsigned int OCU_COMPARE2_NXT_COUNTER1 : 16; /*!< [31..16] PWM output should be
8173                                              high for counter 0 */
8174     } CT_OCU_COMPARE2_NXT_REG_b;
8175   };
8176   __IM unsigned int RESERVED[3];
8177 
8178   union {
8179     __IOM unsigned int CT_START_COUNTER_EVENT_SEL; /*!< (@ 0x00000050) Start counter
8180                                                   event select register */
8181 
8182     struct {
8183       __IOM unsigned int START_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters
8184                                           mode: Event select for starting the
8185                                           Counter 0  For 32 bit counter mode:
8186                                           Event select for starting counter */
8187       __IOM unsigned int RESERVED1 : 10;                /*!< [15..6] Reserved1     */
8188       __IOM unsigned int START_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters
8189                                             mode: Event select for starting the
8190                                             Counter 1.  For 32 bit counter mode:
8191                                             Invalid. Please refer to events
8192                                             table for description */
8193       __IM unsigned int RESERVED2 : 10;                 /*!< [31..22] Reserved2      */
8194     } CT_START_COUNTER_EVENT_SEL_b;
8195   };
8196 
8197   union {
8198     __IOM unsigned int CT_START_COUNTER_AND_EVENT; /*!< (@ 0x00000054) Start counter
8199                                                   AND event register */
8200 
8201     struct {
8202       __IOM unsigned int START_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter
8203                                           mode: AND expression valids for AND
8204                                           event in start Counter 0 event For 32
8205                                           bit counter mode
8206                                           AND expression valids for AND event in
8207                                           start counter event                */
8208       __IOM unsigned int RESERVED1 : 4;                 /*!< [7..4] Reserved1      */
8209       __IOM unsigned int START_COUNTER_0_AND_VLD : 4;   /*!< [11..8] none */
8210       __IM unsigned int RESERVED2 : 4;                  /*!< [15..12] Reserved2                */
8211       __IOM unsigned int START_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters
8212                                           mode: AND expression valids for AND
8213                                           event in start counter event For 32
8214                                           bit counter mode : Invalid */
8215       __IM unsigned int RESERVED3 : 4;                  /*!< [23..20] Reserved3       */
8216       __IOM unsigned int START_COUNTER_1_AND_VLD : 4;   /*!< [27..24] none */
8217       __IM unsigned int RESERVED4 : 4;                  /*!< [31..28] Reserved4                */
8218     } CT_START_COUNTER_AND_EVENT_b;
8219   };
8220 
8221   union {
8222     __IOM unsigned int CT_START_COUNTER_OR_EVENT; /*!< (@ 0x00000058) Start counter
8223                                                  OR event register */
8224 
8225     struct {
8226       __IOM unsigned int START_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode:
8227                                           OR expression valids for OR event in
8228                                           start Counter 0 event For 32 bit
8229                                           counter mode
8230                                           OR expression valids for OR event in
8231                                           start counter event */
8232       __IOM unsigned int RESERVED1 : 4;                /*!< [7..4] Reserved1     */
8233       __IOM unsigned int START_COUNTER_0_OR_VLD : 4;   /*!< [11..8] none */
8234       __IOM unsigned int RESERVED2 : 4;                /*!< [15..12] Reserved2              */
8235       __IOM unsigned int START_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters
8236                                           mode: OR expression valids for OR
8237                                           event in start counter event For 32
8238                                           bit counter mode : Invalid. */
8239       __IM unsigned int RESERVED3 : 4;                 /*!< [23..20] Reserved3      */
8240       __IOM unsigned int START_COUNTER_1_OR_VLD : 4;   /*!< [27..24] none */
8241       __IM unsigned int RESERVED4 : 4;                 /*!< [31..28] Reserved4               */
8242     } CT_START_COUNTER_OR_EVENT_b;
8243   };
8244 
8245   union {
8246     __IOM unsigned int CT_CONTINUE_COUNTER_EVENT_SEL; /*!< (@ 0x0000005C) Continue counter
8247                                           event select register */
8248 
8249     struct {
8250       __IOM unsigned int CONTINUE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters
8251                                                mode: Event select for continuing
8252                                                        the Counter 0 For 32 bit
8253                                                counter mode: Event select for
8254                                                        continuing counter */
8255       __IOM unsigned int RESERVED1 : 10;                   /*!< [15..6] Reserved1        */
8256       __IOM unsigned int CONTINUE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit
8257                                                counters mode: Event select for
8258                                                continuing
8259                                                        the Counter 1  For 32 bit
8260                                                counter mode: Invalid. */
8261       __IM unsigned int RESERVED2 : 10;                    /*!< [31..22] Reserved2         */
8262     } CT_CONTINUE_COUNTER_EVENT_SEL_b;
8263   };
8264 
8265   union {
8266     __IOM unsigned int CT_CONTINUE_COUNTER_AND_EVENT; /*!< (@ 0x00000060) Continue counter AND
8267                                           event register */
8268 
8269     struct {
8270       __IOM unsigned int CONTINUE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter
8271                                                mode: AND expression valids for
8272                                                        AND event in continue
8273                                                Counter 0 event For 32 bit
8274                                                counter mode AND expression
8275                                                valids for AND event in continue
8276                                                counter event. */
8277       __IOM unsigned int RESERVED1 : 4;                    /*!< [7..4] Reserved1         */
8278       __IOM unsigned int CONTINUE_COUNTER_0_AND_VLD : 4;   /*!< [11..8] none */
8279       __IOM unsigned int RESERVED2 : 4;                    /*!< [15..12] Reserved2                  */
8280       __IOM unsigned int CONTINUE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit
8281                                                counters mode: AND expression
8282                                                valids for AND event in continue
8283                                                counter event For 32 bit counter
8284                                                        mode : Invalid */
8285       __IM unsigned int RESERVED3 : 4;                     /*!< [23..20] Reserved3          */
8286       __IOM unsigned int CONTINUE_COUNTER_1_AND_VLD : 4;   /*!< [27..24] none */
8287       __IM unsigned int RESERVED4 : 4;                     /*!< [31..28] Reserved4                   */
8288     } CT_CONTINUE_COUNTER_AND_EVENT_b;
8289   };
8290 
8291   union {
8292     __IOM unsigned int CT_CONTINUE_COUNTER_OR_EVENT; /*!< (@ 0x00000064) Continue counter OR
8293                                          event register */
8294 
8295     struct {
8296       __IOM unsigned int CONTINUE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter
8297                                           mode: OR expression valids for OR
8298                                           event in continue Counter 0 event For
8299                                           32 bit counter mode OR expression
8300                                           valids for OR event in continue
8301                                           counter event */
8302       __IOM unsigned int RESERVED1 : 4;                   /*!< [7..4] Reserved1        */
8303       __IOM unsigned int CONTINUE_COUNTER_0_OR_VLD : 4;   /*!< [11..8] none */
8304       __IOM unsigned int RESERVED2 : 4;                   /*!< [15..12] Reserved2                 */
8305       __IOM unsigned int CONTINUE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters
8306                                           mode: OR expression valids for OR
8307                                           event in continue counter event  For
8308                                           32 bit counter mode : Invalid */
8309       __IM unsigned int RESERVED3 : 4;                    /*!< [23..20] Reserved3         */
8310       __IOM unsigned int CONTINUE_COUNTER_1_OR_VLD : 4;   /*!< [27..24] none */
8311       __IM unsigned int RESERVED4 : 4;                    /*!< [31..28] Reserved4                  */
8312     } CT_CONTINUE_COUNTER_OR_EVENT_b;
8313   };
8314 
8315   union {
8316     __IOM unsigned int CT_STOP_COUNTER_EVENT_SEL; /*!< (@ 0x00000068) Stop counter
8317                                                  event select register */
8318 
8319     struct {
8320       __IOM unsigned int STOP_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters
8321                                           mode: Event select for Stopping the
8322                                           Counter 0 For 32 bit counter mode:
8323                                           Event select for Stopping counter */
8324       __IOM unsigned int RESERVED1 : 10;               /*!< [15..6] Reserved1    */
8325       __IOM unsigned int STOP_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters
8326                                            mode: Event select for Stopping the
8327                                            Counter 1 For 32 bit counter mode:
8328                                            Invalid                            */
8329       __IM unsigned int RESERVED2 : 10;                /*!< [31..22] Reserved2     */
8330     } CT_STOP_COUNTER_EVENT_SEL_b;
8331   };
8332 
8333   union {
8334     __IOM unsigned int CT_STOP_COUNTER_AND_EVENT; /*!< (@ 0x0000006C) Stop counter
8335                                                  AND event register */
8336 
8337     struct {
8338       __IOM unsigned int STOP_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode:
8339                                           AND expression valids for AND event in
8340                                           stop Counter 0 event  For 32 bit
8341                                           counter mode
8342                                           AND expression valids for AND event in
8343                                           stop counter event                 */
8344       __IOM unsigned int RESERVED1 : 4;                /*!< [7..4] Reserved1     */
8345       __IOM unsigned int STOP_COUNTER_0_AND_VLD : 4;   /*!< [11..8] Indicates which
8346                                                     bits in 3:0 are valid for
8347                                                     considering AND event */
8348       __IOM unsigned int RESERVED2 : 4;                /*!< [15..12] Reserved2              */
8349       __IOM unsigned int STOP_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters
8350                                           mode: AND expression valids for AND
8351                                           event in stop counter event For 32 bit
8352                                           counter mode : Invalid */
8353       __IM unsigned int RESERVED3 : 4;                 /*!< [23..20] Reserved3      */
8354       __IOM unsigned int STOP_COUNTER_1_AND_VLD : 4;   /*!< [27..24] none */
8355       __IM unsigned int RESERVED4 : 4;                 /*!< [31..28] Reserved4               */
8356     } CT_STOP_COUNTER_AND_EVENT_b;
8357   };
8358 
8359   union {
8360     __IOM unsigned int CT_STOP_COUNTER_OR_EVENT; /*!< (@ 0x00000070) Stop counter OR
8361                                                 event register */
8362 
8363     struct {
8364       __IOM unsigned int STOP_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode:
8365                                           OR expression valids for OR event in
8366                                           Stop Counter 0 event For 32 bit
8367                                           counter mode
8368                                           OR expression valids for OR event in
8369                                           Stop counter event */
8370       __IOM unsigned int RESERVED1 : 4;               /*!< [7..4] Reserved1    */
8371       __IOM unsigned int STOP_COUNTER_0_OR_VLD : 4;   /*!< [11..8] none */
8372       __IOM unsigned int RESERVED2 : 4;               /*!< [15..12] Reserved2             */
8373       __IOM unsigned int STOP_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters
8374                                           mode: OR expression valids for OR
8375                                           event in Stop counter event For 32 bit
8376                                           counter mode : Invalid */
8377       __IM unsigned int RESERVED3 : 4;                /*!< [23..20] Reserved3     */
8378       __IOM unsigned int STOP_COUNTER_1_OR_VLD : 4;   /*!< [27..24] none */
8379       __IM unsigned int RESERVED4 : 4;                /*!< [31..28] Reserved4              */
8380     } CT_STOP_COUNTER_OR_EVENT_b;
8381   };
8382 
8383   union {
8384     __IOM unsigned int CT_HALT_COUNTER_EVENT_SEL; /*!< (@ 0x00000074) Halt counter
8385                                                  event select register */
8386 
8387     struct {
8388       __IOM unsigned int HALT_COUNTER_0_EVENT_SEL : 6;  /*!< [5..0] For two 16 bit counters
8389                                          mode: Event select for Halting the
8390                                          Counter 0 For 32 bit counter mode:
8391                                          Event select for Halting counter */
8392       __OM unsigned int RESUME_FROM_HALT_COUNTER_0 : 1; /*!< [6..6] For two 16 bit counters
8393                                            mode: Event select for Halting the
8394                                            Counter 0 For 32 bit counter mode:
8395                                            Event select for Halting counter */
8396       __IM unsigned int RESERVED1 : 9;                  /*!< [15..7] Reserved1        */
8397       __IOM unsigned int HALT_COUNTER_1_EVENT_SEL : 6;  /*!< [21..16] For two 16 bit counters
8398                                           mode: Event select for Halting the
8399                                           Counter 1 For 32 bit counter mode:
8400                                           Invalid                            */
8401       __OM unsigned int RESUME_FROM_HALT_COUNTER_1 : 1; /*!< [22..22] For two 16 bit
8402                                                  counters mode: Event select for
8403                                                  Halting the Counter 0 For 32
8404                                                  bit counter mode: Event select
8405                                                  for Halting counter */
8406       __IM unsigned int RESERVED2 : 9;                  /*!< [31..23] Reserved2            */
8407     } CT_HALT_COUNTER_EVENT_SEL_b;
8408   };
8409 
8410   union {
8411     __IOM unsigned int CT_HALT_COUNTER_AND_EVENT; /*!< (@ 0x00000078) Halt counter
8412                                                  AND event register */
8413 
8414     struct {
8415       __IOM unsigned int HALT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode:
8416                                           AND expression valids for AND event in
8417                                           stop Counter 0 event For 32 bit
8418                                           counter mode
8419                                           AND expression valids for AND event in
8420                                           stop counter event                 */
8421       __IOM unsigned int RESERVED1 : 4;                /*!< [7..4] Reserved1     */
8422       __IOM unsigned int HALT_COUNTER_0_AND_VLD : 4;   /*!< [11..8] Indicates which
8423                                                     bits in 3:0 are valid for
8424                                                     considering AND event */
8425       __IM unsigned int RESERVED2 : 4;                 /*!< [15..12] Reserved2               */
8426       __IOM unsigned int HALT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters
8427                                           mode: AND expression valids for AND
8428                                           event in stop counter event For 32 bit
8429                                           counter mode : Invalid */
8430       __IM unsigned int RESERVED3 : 4;                 /*!< [23..20] Reserved3      */
8431       __IOM unsigned int HALT_COUNTER_1_AND_VLD : 4;   /*!< [27..24] none */
8432       __IM unsigned int RESERVED4 : 4;                 /*!< [31..28] Reserved4               */
8433     } CT_HALT_COUNTER_AND_EVENT_b;
8434   };
8435 
8436   union {
8437     __IOM unsigned int CT_HALT_COUNTER_OR_EVENT; /*!< (@ 0x0000007C) Halt counter OR
8438                                                 event register */
8439 
8440     struct {
8441       __IOM unsigned int HALT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode:
8442                                           OR expression valids for OR event in
8443                                           Halt Counter 0 event For 32 bit
8444                                           counter mode
8445                                           OR expression valids for OR event in
8446                                           Halt counter event */
8447       __IOM unsigned int RESERVED1 : 4;               /*!< [7..4] Reserved1    */
8448       __IOM unsigned int HALT_COUNTER_0_OR_VLD : 4;   /*!< [11..8] none */
8449       __IM unsigned int RESERVED2 : 4;                /*!< [15..12] Reserved2              */
8450       __IOM unsigned int HALT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters
8451                                           mode: OR expression valids for OR
8452                                           event in Halt counter event For 32 bit
8453                                           counter mode : Invalid */
8454       __IM unsigned int RESERVED3 : 4;                /*!< [23..20] Reserved3     */
8455       __IOM unsigned int HALT_COUNTER_1_OR_VLD : 4;   /*!< [27..24] none */
8456       __IM unsigned int RESERVED4 : 4;                /*!< [31..28] Reserved4              */
8457     } CT_HALT_COUNTER_OR_EVENT_b;
8458   };
8459 
8460   union {
8461     __IOM unsigned int CT_INCREMENT_COUNTER_EVENT_SEL; /*!< (@ 0x00000080) Increment counter
8462                                            event select register */
8463 
8464     struct {
8465       __IOM unsigned int INCREMENT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters
8466                                                 mode: Event select for
8467                                                 Incrementing the Counter 0 For
8468                                                 32 bit counter mode: Event
8469                                                 select for
8470                                                        Incrementing counter */
8471       __IM unsigned int RESERVED1 : 10;                     /*!< [15..6] Reserved1          */
8472       __IOM unsigned int INCREMENT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16
8473                                                            bit counters mode:
8474                                                            Event select for
8475                                                            Incrementing the
8476                                                            Counter 1 For 32 bit
8477                                                            counter mode: Invalid
8478                                                          */
8479       __IM unsigned int RESERVED2 : 10;                     /*!< [31..22] Reserved2 */
8480     } CT_INCREMENT_COUNTER_EVENT_SEL_b;
8481   };
8482 
8483   union {
8484     __IOM unsigned int CT_INCREMENT_COUNTER_AND_EVENT; /*!< (@ 0x00000084) Increment counter
8485                                            AND event register */
8486 
8487     struct {
8488       __IOM unsigned int INCREMENT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter
8489                                                 mode: AND expression valids for
8490                                                        AND event in stop Counter
8491                                                 0 event For 32 bit counter mode
8492                                                        AND expression valids for
8493                                                 AND event in stop counter event
8494                                               */
8495       __IOM unsigned int RESERVED1 : 4;                     /*!< [7..4] Reserved1          */
8496       __IOM unsigned int INCREMENT_COUNTER_0_AND_VLD : 4;   /*!< [11..8] none */
8497       __IM unsigned int RESERVED2 : 4;                      /*!< [15..12] Reserved2                    */
8498       __IOM unsigned int INCREMENT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit
8499                                                 counters mode: AND expression
8500                                                 valids for AND event in stop
8501                                                 counter event For 32 bit counter
8502                                                        mode : Invalid */
8503       __IM unsigned int RESERVED3 : 4;                      /*!< [23..20] Reserved3           */
8504       __IOM unsigned int INCREMENT_COUNTER_1_AND_VLD : 4;   /*!< [27..24] none */
8505       __IM unsigned int RESERVED4 : 4;                      /*!< [31..28] Reserved4                    */
8506     } CT_INCREMENT_COUNTER_AND_EVENT_b;
8507   };
8508 
8509   union {
8510     __IOM unsigned int CT_INCREMENT_COUNTER_OR_EVENT; /*!< (@ 0x00000088) Increment counter OR
8511                                           event register */
8512 
8513     struct {
8514       __IOM unsigned int INCREMENT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter
8515                                                mode: OR expression valids for OR
8516                                                event in Increment Counter 0
8517                                                event For 32 bit counter mode OR
8518                                                expression valids for OR event in
8519                                                Increment counter event */
8520       __IOM unsigned int RESERVED1 : 4;                    /*!< [7..4] Reserved1         */
8521       __IOM unsigned int INCREMENT_COUNTER_0_OR_VLD : 4;   /*!< [11..8] none */
8522       __IM unsigned int RESERVED2 : 4;                     /*!< [15..12] Reserved2                   */
8523       __IOM unsigned int INCREMENT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit
8524                                           counters mode: OR expression valids
8525                                           for OR event in Increment counter
8526                                           event For 32 bit counter mode :
8527                                           Invalid */
8528       __IM unsigned int RESERVED4 : 4;                     /*!< [23..20] Reserved4          */
8529       __IOM unsigned int INCREMENT_COUNTER_1_OR_VLD : 4;   /*!< [27..24] none */
8530       __IM unsigned int RESERVED5 : 4;                     /*!< [31..28] Reserved5                   */
8531     } CT_INCREMENT_COUNTER_OR_EVENT_b;
8532   };
8533 
8534   union {
8535     __IOM unsigned int CT_CAPTURE_COUNTER_EVENT_SEL; /*!< (@ 0x0000008C) Capture counter event
8536                                          select register                      */
8537 
8538     struct {
8539       __IOM unsigned int CAPTURE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters
8540                                               mode: Event select for Capturing
8541                                                        the Counter 0 For 32 bit
8542                                               counter mode: Event select for
8543                                                        Capturing counter */
8544       __IM unsigned int RESERVED1 : 10;                   /*!< [15..6] Reserved1        */
8545       __IOM unsigned int CAPTURE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters
8546                                               mode: Event select for Capturing
8547                                                        the Counter 1 For 32 bit
8548                                               counter mode : Invalid */
8549       __IM unsigned int RESERVED2 : 10;                   /*!< [31..22] Reserved2        */
8550     } CT_CAPTURE_COUNTER_EVENT_SEL_b;
8551   };
8552 
8553   union {
8554     __IOM unsigned int CT_CAPTURE_COUNTER_AND_EVENT; /*!< (@ 0x00000090) Capture counter AND
8555                                          event register */
8556 
8557     struct {
8558       __IOM
8559       unsigned int CAPTURE_COUNTER_0_AND_EVENT : 4;       /*!< [3..0] For two 16 bit
8560                                                        counter mode: AND expression
8561                                                        valids for      AND event in stop
8562                                                        Counter 0 event For 32 bit
8563                                                        counter mode      AND expression
8564                                                        valids for AND event in stop
8565                                                        counter event      */
8566       __IOM unsigned int RESERVED1 : 4;                   /*!< [7..4] Reserved1                 */
8567       __IOM unsigned int CAPTURE_COUNTER_0_AND_VLD : 4;   /*!< [11..8] none */
8568       __IM unsigned int RESERVED2 : 4;                    /*!< [15..12] Reserved2                  */
8569       __IOM unsigned int CAPTURE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters
8570                                           mode: AND expression valids for AND
8571                                           event in stop counter event For 32 bit
8572                                           counter mode : Invalid */
8573       __IM unsigned int RESERVED3 : 4;                    /*!< [23..20] Reserved3         */
8574       __IOM unsigned int CAPTURE_COUNTER_1_AND_VLD : 4;   /*!< [27..24] none */
8575       __IM unsigned int RESERVED4 : 4;                    /*!< [31..28] Reserved4                  */
8576     } CT_CAPTURE_COUNTER_AND_EVENT_b;
8577   };
8578 
8579   union {
8580     __IOM unsigned int CT_CAPTURE_COUNTER_OR_EVENT; /*!< (@ 0x00000094) Capture counter OR
8581                                         event register */
8582 
8583     struct {
8584       __IOM unsigned int CAPTURE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter
8585                                           mode: OR expression valids for OR
8586                                           event in Capture Counter 0 event For
8587                                           32 bit counter mode OR expression
8588                                           valids for OR event in Capture counter
8589                                           event */
8590       __IOM unsigned int RESERVED1 : 4;                  /*!< [7..4] Reserved1       */
8591       __IOM unsigned int CAPTURE_COUNTER_0_OR_VLD : 4;   /*!< [11..8] none */
8592       __IM unsigned int RESERVED2 : 4;                   /*!< [15..12] Reserved2                 */
8593       __IOM unsigned int CAPTURE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters
8594                                           mode: OR expression valids for OR
8595                                           event in Capture counter event For 32
8596                                           bit counter mode : Invalid */
8597       __IM unsigned int RESERVED3 : 4;                   /*!< [23..20] Reserved3        */
8598       __IOM unsigned int CAPTURE_COUNTER_1_OR_VLD : 4;   /*!< [27..24] none */
8599       __IM unsigned int RESERVED4 : 4;                   /*!< [31..28] Reserved4                 */
8600     } CT_CAPTURE_COUNTER_OR_EVENT_b;
8601   };
8602 
8603   union {
8604     __IOM unsigned int CT_OUTPUT_EVENT_SEL; /*!< (@ 0x00000098) Output event select
8605                                            register */
8606 
8607     struct {
8608       __IOM unsigned int OUTPUT_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode:
8609                                        Event select for output   event from Counter
8610                                        0 For 32 bit counter mode: Event select
8611                                             for output event   */
8612       __IM unsigned int RESERVED1 : 10;          /*!< [15..6] Reserved1 */
8613       __IOM unsigned int OUTPUT_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters mode:
8614                                        Event select for output
8615                                             event from counter 1 For 32 bit
8616                                        counter mode : Invalid   */
8617       __IM unsigned int RESERVED2 : 10;          /*!< [31..22] Reserved2 */
8618     } CT_OUTPUT_EVENT_SEL_b;
8619   };
8620 
8621   union {
8622     __IOM unsigned int CT_OUTPUT_AND_EVENT_REG; /*!< (@ 0x0000009C) Output AND event
8623                                                Register */
8624 
8625     struct {
8626       __IOM unsigned int OUTPUT_0_AND_EVENT : 4; /*!< [3..0] AND expression for AND event in
8627                                        output Counter_0 event.            */
8628       __IOM unsigned int RESERVED1 : 4;          /*!< [7..4] Reserved1 */
8629       __IOM unsigned int OUTPUT_0_AND_VLD : 4;   /*!< [11..8] AND expression for AND event in
8630                                       output Counter_0 event.           */
8631       __IM unsigned int RESERVED2 : 4;           /*!< [15..12] Reserved2 */
8632       __IOM unsigned int OUTPUT_1_AND_EVENT : 4; /*!< [19..16] AND expression for AND event in
8633                                       output Counter_1 event.          */
8634       __IM unsigned int RESERVED3 : 4;           /*!< [23..20] Reserved3 */
8635       __IOM unsigned int OUTPUT_1_AND_VLD : 4;   /*!< [27..24] AND expression for AND event in
8636                                       output Counter_1 event.          */
8637       __IM unsigned int RESERVED4 : 4;           /*!< [31..28] Reserved4 */
8638     } CT_OUTPUT_AND_EVENT_REG_b;
8639   };
8640 
8641   union {
8642     __IOM unsigned int CT_OUTPUT_OR_EVENT; /*!< (@ 0x000000A0) Output OR event Register */
8643 
8644     struct {
8645       __IOM unsigned int OUTPUT_0_OR_EVENT : 4; /*!< [3..0] OR expression for OR event in
8646                                        output Counter_0 event               */
8647       __IOM unsigned int RESERVED1 : 4;         /*!< [7..4] Reserved1 */
8648       __IOM unsigned int OUTPUT_0_OR_VLD : 4;   /*!< [11..8] Indicates which bits in 3:0 are
8649                                       valid for considering     OR event     */
8650       __IM unsigned int RESERVED2 : 4;          /*!< [15..12] Reserved2 */
8651       __IOM unsigned int OUTPUT_1_OR_EVENT : 4; /*!< [19..16] OR expression for OR event in
8652                                       output Counter_0 event             */
8653       __IM unsigned int RESERVED3 : 4;          /*!< [23..20] Reserved3 */
8654       __IOM unsigned int OUTPUT_1_OR_VLD : 4;   /*!< [27..24] Indicates which bits in 3:0 are
8655                                       valid for considering     OR event     */
8656       __IM unsigned int RESERVED4 : 4;          /*!< [31..28] Reserved4 */
8657     } CT_OUTPUT_OR_EVENT_b;
8658   };
8659 
8660   union {
8661     __IOM unsigned int CT_INTR_EVENT_SEL; /*!< (@ 0x000000A4) Interrupt Event Select
8662                                          Register                            */
8663 
8664     struct {
8665       __IOM unsigned int INTR_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: Event
8666                                    select for interrupt event from Counter 0 For
8667                                    32 bit counter mode: Event select
8668                                           for output event */
8669       __IM unsigned int RESERVED1 : 10;        /*!< [15..6] Reserved1        */
8670       __IOM unsigned int INTR_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters
8671                                               mode: Event select for interrupt
8672                                                      event from counter 1 For 32
8673                                               bit counter mode : Invalid */
8674       __IM unsigned int RESERVED2 : 10;        /*!< [31..22] Reserved2        */
8675     } CT_INTR_EVENT_SEL_b;
8676   };
8677 
8678   union {
8679     __IOM unsigned int CT_INTR_AND_EVENT; /*!< (@ 0x000000A8) Interrupt AND Event Register */
8680 
8681     struct {
8682       __IOM unsigned int INTR_0_AND_EVENT : 4; /*!< [3..0] None */
8683       __IOM unsigned int RESERVED1 : 4;        /*!< [7..4] Reserved1        */
8684       __IOM unsigned int INTR_0_AND_VLD : 4;   /*!< [11..8] None   */
8685       __IM unsigned int RESERVED2 : 4;         /*!< [15..12] Reserved2         */
8686       __IOM unsigned int INTR_1_AND_EVENT : 4; /*!< [19..16] None */
8687       __IM unsigned int RESERVED3 : 4;         /*!< [23..20] Reserved3         */
8688       __IOM unsigned int INTR_1_AND_VLD : 4;   /*!< [27..24] None   */
8689       __IM unsigned int RESERVED4 : 4;         /*!< [31..28] Reserved4         */
8690     } CT_INTR_AND_EVENT_b;
8691   };
8692 
8693   union {
8694     __IOM unsigned int CT_INTR_OR_EVENT_REG; /*!< (@ 0x000000AC) Interrupt OR Event
8695                                             Register */
8696 
8697     struct {
8698       __IOM unsigned int INTR_0_OR_EVENT : 4; /*!< [3..0] None */
8699       __IOM unsigned int RESERVED1 : 4;       /*!< [7..4] Reserved1       */
8700       __IOM unsigned int INTR_0_OR_VLD : 4;   /*!< [11..8] None   */
8701       __IM unsigned int RESERVED2 : 4;        /*!< [15..12] Reserved2        */
8702       __IOM unsigned int INTR_1_OR_EVENT : 4; /*!< [19..16] None */
8703       __IM unsigned int RESERVED3 : 4;        /*!< [23..20] Reserved3        */
8704       __IOM unsigned int INTR_1_OR_VLD : 4;   /*!< [27..24] None   */
8705       __IM unsigned int RESERVED4 : 4;        /*!< [31..28] Reserved4        */
8706     } CT_INTR_OR_EVENT_REG_b;
8707   };
8708 } CT0_Type; /*!< Size = 176 (0xb0) */
8709 
8710 /* ===========================================================================================================================
8711  */
8712 /* ================                                        CT_MUX_REG
8713  * ================ */
8714 /* ===========================================================================================================================
8715  */
8716 
8717 /**
8718   * @brief Configurable timer is used in counting clocks, events and states with
8719   reference clock external clock and system clock (CT_MUX_REG)
8720   */
8721 
8722 typedef struct { /*!< (@ 0x4506F000) CT_MUX_REG Structure */
8723 
8724   union {
8725     __IOM unsigned int CT_MUX_SEL_0_REG; /*!< (@ 0x00000000) MUX_SEL_0_REG Register */
8726 
8727     struct {
8728       __IOM unsigned int MUX_SEL_0 : 4;  /*!< [3..0] Select value to select first output value
8729                             fifo_0_full[0] out of all the fifo_0_full_muxed
8730                             signals of counter 0                     */
8731       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */
8732     } CT_MUX_SEL_0_REG_b;
8733   };
8734 
8735   union {
8736     __IOM unsigned int CT_MUX_SEL_1_REG; /*!< (@ 0x00000004) MUX_SEL_1_REG Register */
8737 
8738     struct {
8739       __IOM unsigned int MUX_SEL_1 : 4;  /*!< [3..0] Select value to select first output value
8740                             fifo_0_full[1] out of all the fifo_0_full_muxed
8741                             signals of counter 0                     */
8742       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */
8743     } CT_MUX_SEL_1_REG_b;
8744   };
8745 
8746   union {
8747     __IOM unsigned int CT_MUX_SEL_2_REG; /*!< (@ 0x00000008) MUX_SEL_2_REG Register */
8748 
8749     struct {
8750       __IOM unsigned int MUX_SEL_2 : 4;  /*!< [3..0] Select value to select first output value
8751                             fifo_1_full[0] out of all the fifo_1_full_muxed
8752                             signals of counter 1                     */
8753       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */
8754     } CT_MUX_SEL_2_REG_b;
8755   };
8756 
8757   union {
8758     __IOM unsigned int CT_MUX_SEL_3_REG; /*!< (@ 0x0000000C) MUX_SEL_3_REG Register */
8759 
8760     struct {
8761       __IOM unsigned int MUX_SEL_3 : 4;  /*!< [3..0] Select value to select first output value
8762                             fifo_1_full[1] out of all the fifo_1_full_muxed
8763                             signals of counter 1                     */
8764       __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */
8765     } CT_MUX_SEL_3_REG_b;
8766   };
8767   __IM unsigned int RESERVED[2];
8768 
8769   union {
8770     __IOM unsigned int CT_OUTPUT_EVENT1_ADC_SEL; /*!< (@ 0x00000018) OUTPUT_EVENT_ADC_SEL
8771                                      Register                              */
8772 
8773     struct {
8774       __IOM
8775       unsigned int OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one
8776                                            output event out of all the output
8777                                            events output_event_0 output_event_1,
8778                                            output_event_2, output_event_3 to
8779                                            enable ADC module */
8780       __IOM unsigned int RESERVED1 : 28;     /*!< [31..4] Reserved1    */
8781     } CT_OUTPUT_EVENT1_ADC_SEL_b;
8782   };
8783 
8784   union {
8785     __IOM unsigned int CT_OUTPUT_EVENT2_ADC_SEL; /*!< (@ 0x0000001C) OUTPUT_EVENT_ADC_SEL
8786                                      Register                              */
8787 
8788     struct {
8789       __IOM
8790       unsigned int OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one
8791                                            output event out of all the output
8792                                            events output_event_0 output_event_1,
8793                                            output_event_2, output_event_3 to
8794                                            enable ADC module */
8795       __IOM unsigned int RESERVED1 : 28;     /*!< [31..4] Reserved1    */
8796     } CT_OUTPUT_EVENT2_ADC_SEL_b;
8797   };
8798 } CT_MUX_REG_Type; /*!< Size = 32 (0x20) */
8799 
8800 /* ===========================================================================================================================
8801  */
8802 /* ================                                           EGPIO
8803  * ================ */
8804 /* ===========================================================================================================================
8805  */
8806 
8807 /**
8808  * @brief ENHANCED GENERAL PERPOSE INPUT/OUTPUT (EGPIO)
8809  */
8810 
8811 typedef struct {                              /*!< (@ 0x46130000) EGPIO Structure */
8812   __IOM EGPIO_PIN_CONFIG_Type PIN_CONFIG[80]; /*!< (@ 0x00000000) [0..79] */
8813   __IM unsigned int RESERVED[704];
8814   __IOM EGPIO_PORT_CONFIG_Type PORT_CONFIG[6]; /*!< (@ 0x00001000) [0..5] */
8815   __IM unsigned int RESERVED1[80];
8816   __IOM EGPIO_INTR_Type INTR[8];                   /*!< (@ 0x00001200) [0..7] */
8817   __IOM EGPIO_GPIO_GRP_INTR_Type GPIO_GRP_INTR[4]; /*!< (@ 0x00001240) [0..3] */
8818 } EGPIO_Type;                                      /*!< Size = 4704 (0x1260)           */
8819 
8820 /* ===========================================================================================================================
8821  */
8822 /* ================                                           SDIO0
8823  * ================ */
8824 /* ===========================================================================================================================
8825  */
8826 
8827 /**
8828  * @brief The Secure Digital I/O (SDIO) Slave module implements the
8829  * functionality of the SDIO card based on the SDIO specifications version 2.0.
8830  * (SDIO0)
8831  */
8832 
8833 typedef struct { /*!< (@ 0x40000000) SDIO0 Structure */
8834 
8835   union {
8836     __IOM unsigned int SDIO_INTR_FN1_STATUS_CLEAR_REG; /*!< (@ 0x00000000) SDIO Function1
8837                                            Interrupt Enable Register */
8838 
8839     struct {
8840       __IOM unsigned int SDIO_WR_INT_CLR : 1;      /*!< [0..0] This bit is used to enable
8841                                              CMD53 write interrupt. =1
8842                                                      Interrupt is enabled =0 -
8843                                              Interrupt is disabled */
8844       __IOM unsigned int SDIO_RD_INT_CLR : 1;      /*!< [1..1] This bit is used to enable
8845                                              CMD53 read interrupt */
8846       __IOM unsigned int SDIO_CSA_INT_CLR : 1;     /*!< [2..2] This bit is used to
8847                                                 enable CMD53 CSA interrupt   */
8848       __IOM unsigned int SDIO_CMD52_INT_CLR : 1;   /*!< [3..3] This bit is used to
8849                                                 enable CMD52 interrupt */
8850       __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power
8851                                        level change interrupt            */
8852       __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC
8853                                        error interrupt                     */
8854       __IOM unsigned int SDIO_ABORT_INT_CLR : 1;   /*!< [6..6] This bit is used to
8855                                                 enable abort interrupt */
8856       __IOM unsigned int SDIO_TOUT_INT_CLR : 1;    /*!< [7..7] This bit is used to enable ?read
8857                                     FIFO wait time over? interrupt */
8858       __IOM unsigned int SDIO_WR_RDZ : 1;          /*!< [8..8] SDIO_WR_RDZ */
8859       __IOM unsigned int SDIO_CSA_ACCESS : 1;      /*!< [9..9] csa_window_access When set, indicates
8860                                   that current request is for CSA window
8861                                   register. This is only status signal */
8862       __IOM unsigned int RES : 22;                 /*!< [31..10] reserved1 */
8863     } SDIO_INTR_FN1_STATUS_CLEAR_REG_b;
8864   };
8865 
8866   union {
8867     __IOM unsigned int SDIO_INTR_FN1_ENABLE_REG; /*!< (@ 0x00000004) SDIO Function1
8868                                                 Interrupt Enable Register */
8869 
8870     struct {
8871       __IOM unsigned int SDIO_WR_INT_EN : 1;      /*!< [0..0] This bit is used to enable
8872                                              CMD53 write interrupt.  */
8873       __IOM unsigned int SDIO_RD_INT_EN : 1;      /*!< [1..1] This bit is used to enable
8874                                              CMD53 read interrupt  */
8875       __IOM unsigned int SDIO_CSA_INT_EN : 1;     /*!< [2..2] This bit is used to enable
8876                                              CMD53 CSA interrupt */
8877       __IOM unsigned int SDIO_CMD52_INT_EN : 1;   /*!< [3..3] This bit is used to
8878                                                enable CMD52 interrupt */
8879       __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power
8880                                       level change interrupt            */
8881       __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to
8882                                                  enable CRC error interrupt */
8883       __IOM unsigned int SDIO_ABORT_INT_EN : 1;   /*!< [6..6] This bit is used to
8884                                                  enable abort interrupt   */
8885       __IOM unsigned int SDIO_TOUT_INT_EN : 1;    /*!< [7..7] This bit is used to enable ?read
8886                                    FIFO wait time over? interrupt */
8887       __IOM unsigned int RES : 24;                /*!< [31..8] reserved5  */
8888     } SDIO_INTR_FN1_ENABLE_REG_b;
8889   };
8890 
8891   union {
8892     __IOM unsigned int SDIO_INTR_FN1_MASK_REG; /*!< (@ 0x00000008) SDIO Function1
8893                                               Interrupt Mask Register */
8894 
8895     struct {
8896       __IOM unsigned int SDIO_WR_INT_MSK : 1;  /*!< [0..0] This bit is used to mask
8897                                              CMD53 write interrupt */
8898       __IOM unsigned int SDIO_RD_INT_MSK : 1;  /*!< [1..1] This bit is used to mask
8899                                              CMD53 read interrupt */
8900       __IOM unsigned int SDIO_CSA_MSK : 1;     /*!< [2..2] This bit is used to mask CMD53 CSA
8901                                interrupt.Setting this bit will mask the
8902                                interrupt Clearing this bit has no effect */
8903       __IOM unsigned int SDIO_CMD52_MSK : 1;   /*!< [3..3] This bit is used to mask
8904                                               CMD52 interrupt   */
8905       __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask
8906                                               power level change interrupt */
8907       __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask
8908                                               CRC error interrupt */
8909       __IOM unsigned int SDIO_ABORT_MSK : 1;   /*!< [6..6] This bit is used to mask abort
8910                                  interrupt Setting this bit will mask the
8911                                  interrupt Clearing this bit has no effect */
8912       __IOM unsigned int SDIO_TOUT_MSK : 1;    /*!< [7..7] This bit is used to mask read FIFO wait
8913                                 time over interrupt        */
8914       __IOM unsigned int RES : 24;             /*!< [31..8] reserved5 */
8915     } SDIO_INTR_FN1_MASK_REG_b;
8916   };
8917 
8918   union {
8919     __IOM unsigned int SDIO_INTR_FN1_UNMASK_REG; /*!< (@ 0x0000000C) SDIO Function1
8920                                                 Interrupt UnMask Register */
8921 
8922     struct {
8923       __IOM unsigned int SDIO_WR_INT_UNMSK : 1;  /*!< [0..0] This bit is used to
8924                                                unmask CMD53 write interrupt */
8925       __IOM unsigned int SDIO_RD_INT_UNMSK : 1;  /*!< [1..1] This bit is used to
8926                                                unmask CMD53 read interrupt */
8927       __IOM unsigned int SDIO_CSA_UNMSK : 1;     /*!< [2..2] This bit is used to unmask CMD53 CSA
8928                                  interrupt.Setting this bit will mask the
8929                                  interrupt Clearing this bit has no effect */
8930       __IOM unsigned int SDIO_CMD52_UNMSK : 1;   /*!< [3..3] This bit is used to
8931                                               unmask CMD52 interrupt */
8932       __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power
8933                                      level change interrupt            */
8934       __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to
8935                                                 unmask CRC error interrupt */
8936       __IOM
8937       unsigned int SDIO_ABORT_UNMSK : 1;      /*!< [6..6] This bit is used to unmask
8938                                             abort interrupt Setting this bit
8939                                             will mask the interrupt Clearing
8940                                             this bit has no effect */
8941       __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO
8942                                   wait time over interrupt      */
8943       __IOM unsigned int RES : 24;            /*!< [31..8] reserved5 */
8944     } SDIO_INTR_FN1_UNMASK_REG_b;
8945   };
8946 
8947   union {
8948     __IM unsigned int SDIO_BLK_LEN_REG; /*!< (@ 0x00000010) SDIO Block Length Register */
8949 
8950     struct {
8951       __IM unsigned int SDIO_BLK_LEN : 12; /*!< [11..0] Length of each block for the
8952                                           last received CMD53 */
8953       __IM unsigned int RES : 20;          /*!< [31..12] reserved5          */
8954     } SDIO_BLK_LEN_REG_b;
8955   };
8956 
8957   union {
8958     __IM unsigned int SDIO_BLK_CNT_REG; /*!< (@ 0x00000014) SDIO Block Length Register */
8959 
8960     struct {
8961       __IM unsigned int SDIO_BLK_CNT : 9; /*!< [8..0] Block count for the last
8962                                          received CMD53 */
8963       __IM unsigned int RES : 23;         /*!< [31..9] reserved5         */
8964     } SDIO_BLK_CNT_REG_b;
8965   };
8966 
8967   union {
8968     __IM unsigned int SDIO_ADDRESS_REG; /*!< (@ 0x00000018) SDIO Address Register */
8969 
8970     struct {
8971       __IM unsigned int SDIO_ADDR : 16; /*!< [15..0] Lower 16-bits of the 17-bit address field
8972                              in the last received CMD53 */
8973       __IM unsigned int RES : 16;       /*!< [31..16] reserved5 */
8974     } SDIO_ADDRESS_REG_b;
8975   };
8976   __IOM unsigned int SDIO_CMD52_RDATA_REGISTER; /*!< (@ 0x0000001C) SDIO CMD52 RDATA
8977                                                Register */
8978   __IOM unsigned int SDIO_CMD52_WDATA_REGISTER; /*!< (@ 0x00000020) SDIO CMD52 WDATA
8979                                                Register */
8980 
8981   union {
8982     __IM unsigned int SDIO_INTR_STATUS_REG; /*!< (@ 0x00000024) SDIO Interrupt
8983                                            Status Register */
8984 
8985     struct {
8986       __IM unsigned int SDIO_INT_ERROR : 1; /*!< [0..0] Interrupt is pending because of error
8987                                  condition from any of the functions */
8988       __IM unsigned int SDIO_INT_FN1 : 1;   /*!< [1..1] Interrupt is pending for function1 */
8989       __IM unsigned int SDIO_INT_FN2 : 1;   /*!< [2..2] Interrupt is pending for function2 */
8990       __IM unsigned int SDIO_INT_FN3 : 1;   /*!< [3..3] Interrupt is pending for function3 */
8991       __IM unsigned int SDIO_INT_FN4 : 1;   /*!< [4..4] Interrupt is pending for function4 */
8992       __IM unsigned int SDIO_INT_FN5 : 1;   /*!< [5..5] Interrupt is pending for function5   */
8993       __IM unsigned int RES : 26;           /*!< [31..6] reserved5 */
8994     } SDIO_INTR_STATUS_REG_b;
8995   };
8996 
8997   union {
8998     __IM unsigned int SDIO_INTR_FN_NUMBER_REG; /*!< (@ 0x00000028) SDIO Interrupt
8999                                               Function Number Register */
9000 
9001     struct {
9002       __IM unsigned int SDIO_INTR_FN_NUM : 3; /*!< [2..0] Indicates the function number to
9003                                    which interrupt is pending.       */
9004       __IM unsigned int RES : 29;             /*!< [31..3] reserved5   */
9005     } SDIO_INTR_FN_NUMBER_REG_b;
9006   };
9007 
9008   union {
9009     __IM unsigned int SDIO_FIFO_STATUS_REG; /*!< (@ 0x0000002C) SDIO FIFO Status Register */
9010 
9011     struct {
9012       __IM unsigned int SDIO_WFIFO_FULL : 1;        /*!< [0..0] When set, indicates that
9013                                              WFIFO is full WFIFO is used
9014                                                       in SDIO reads from host for
9015                                              sending data from AHB to Host  */
9016       __IM unsigned int SDIO_WFIFO_AFULL : 1;       /*!< [1..1] When set, indicates that
9017                                              WFIFO is almost full */
9018       __IM unsigned int SDIO_RFIFO_EMPTY : 1;       /*!< [2..2] When set, indicates that RFIFO is
9019                                    empty RFIFO is used in SDIO writes from host
9020                                    for sending data from host to AHB */
9021       __IM unsigned int SDIO_RFIFO_AEMPTY : 1;      /*!< [3..3] When set, indicates that
9022                                               RFIFO is almost empty */
9023       __IM unsigned int SDIO_CURRENT_FN_NUM : 3;    /*!< [6..4] Indicates the function number of
9024                                       the last received command         */
9025       __IM unsigned int SDIO_BUS_CONTROL_STATE : 5; /*!< [11..7] Indicates the function number
9026                                          of the last received command        */
9027       __IM unsigned int RES : 20;                   /*!< [31..12] reserved5         */
9028     } SDIO_FIFO_STATUS_REG_b;
9029   };
9030 
9031   union {
9032     __IM unsigned int SDIO_FIFO_OCC_REG; /*!< (@ 0x00000030) SDIO FIFO Occupancy Register */
9033 
9034     struct {
9035       __IM unsigned int SDIO_WFIFO_OCC : 8;   /*!< [7..0] Indicates the occupancy
9036                                              level of the write FIFO   */
9037       __IM unsigned int SDIO_RFIFO_AVAIL : 8; /*!< [15..8] Indicates the available
9038                                              space in the read FIFO */
9039       __IM unsigned int RES : 16;             /*!< [31..16] reserved5             */
9040     } SDIO_FIFO_OCC_REG_b;
9041   };
9042 
9043   union {
9044     __IOM unsigned int SDIO_HOST_INTR_SET_REG; /*!< (@ 0x00000034) SDIO Host
9045                                               Interrupt Set Register */
9046 
9047     struct {
9048       __IOM unsigned int SDIO_INTSET_FN2 : 1; /*!< [0..0] This bit is used to raise an
9049                                   interrupt to host for function2. Setting this
9050                                   bit will raise the interrupt Clearing this
9051                                           bit has no effect */
9052       __IOM unsigned int SDIO_INTSET_FN3 : 1; /*!< [1..1] This bit is used to raise an
9053                                   interrupt to host for function3. Setting this
9054                                   bit will raise the interrupt Clearing this
9055                                           bit has no effect */
9056       __IOM unsigned int SDIO_INTSET_FN4 : 1; /*!< [2..2] This bit is used to raise an
9057                                   interrupt to host for function4. Setting this
9058                                   bit will raise the interrupt Clearing this
9059                                           bit has no effect */
9060       __IOM unsigned int SDIO_INTSET_FN5 : 1; /*!< [3..3] This bit is used to raise an
9061                                   interrupt to host for function5. Setting this
9062                                   bit will raise the interrupt Clearing this
9063                                           bit has no effect */
9064       __IOM unsigned int RES : 28;            /*!< [31..4] reserved5 */
9065     } SDIO_HOST_INTR_SET_REG_b;
9066   };
9067 
9068   union {
9069     __IOM unsigned int SDIO_HOST_INTR_CLEAR_REG; /*!< (@ 0x00000038) SDIO Host
9070                                                 Interrupt Clear Register */
9071 
9072     struct {
9073       __IOM unsigned int SDIO_INTCLR_FN2 : 1; /*!< [0..0] This bit is used to clear the
9074                                   interrupt to host for function2. Setting this
9075                                   bit will clear the interrupt Clearing this
9076                                           bit has no effect */
9077       __IOM unsigned int SDIO_INTCLR_FN3 : 1; /*!< [1..1] This bit is used to clear the
9078                                   interrupt to host for function3. Setting this
9079                                   bit will clear the interrupt Clearing this
9080                                           bit has no effect */
9081       __IOM unsigned int SDIO_INTCLR_FN4 : 1; /*!< [2..2] This bit is used to clear the
9082                                   interrupt to host for function4. Setting this
9083                                   bit will clear the interrupt Clearing this
9084                                           bit has no effectt */
9085       __IOM unsigned int SDIO_INTCLR_FN5 : 1; /*!< [3..3] This bit is used to clear the
9086                                   interrupt to host for function5. Setting this
9087                                   bit will clear the interrupt Clearing this
9088                                           bit has no effect */
9089       __IOM unsigned int RES : 28;            /*!< [31..4] reserved5 */
9090     } SDIO_HOST_INTR_CLEAR_REG_b;
9091   };
9092   __IM unsigned int RESERVED;
9093 
9094   union {
9095     __OM unsigned int SDIO_RFIFO_DATA_REG[16]; /*!< (@ 0x00000040) SDIO Read FIFO
9096                                               Data Register */
9097 
9098     struct {
9099       __OM unsigned int SDIO_RFIFO : 32; /*!< [31..0] Data to be written into SDIO Read FIFO
9100                               has to be written in this register. */
9101     } SDIO_RFIFO_DATA_REG_b[16];
9102   };
9103 
9104   union {
9105     __IM unsigned int SDIO_WFIFO_DATA_REG[16]; /*!< (@ 0x00000080) SDIO Write FIFO
9106                                               Data Register */
9107 
9108     struct {
9109       __IM unsigned int SDIO_WFIFO : 32; /*!< [31..0] SDIO Write FIFO data can be
9110                                         read through this register.           */
9111     } SDIO_WFIFO_DATA_REG_b[16];
9112   };
9113 
9114   union {
9115     __IOM unsigned int SDIO_INTR_FN2_STATUS_CLEAR_REG; /*!< (@ 0x000000C0) SDIO Function2
9116                                            Status Clear Register */
9117 
9118     struct {
9119       __IOM unsigned int SDIO_WR_INT_CLR : 1;      /*!< [0..0] This bit is used to enable
9120                                              CMD53 write interrupt. =1
9121                                                      Interrupt is enabled =0 -
9122                                              Interrupt is disabled */
9123       __IOM unsigned int SDIO_RD_INT_CLR : 1;      /*!< [1..1] This bit is used to enable
9124                                              CMD53 read interrupt */
9125       __IOM unsigned int SDIO_CSA_INT_CLR : 1;     /*!< [2..2] This bit is used to
9126                                                 enable CMD53 CSA interrupt   */
9127       __IOM unsigned int SDIO_CMD52_INT_CLR : 1;   /*!< [3..3] This bit is used to
9128                                                 enable CMD52 interrupt */
9129       __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power
9130                                        level change interrupt            */
9131       __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC
9132                                        error interrupt                     */
9133       __IOM unsigned int SDIO_ABORT_INT_CLR : 1;   /*!< [6..6] This bit is used to
9134                                                 enable abort interrupt */
9135       __IOM unsigned int SDIO_TOUT_INT_CLR : 1;    /*!< [7..7] This bit is used to enable ?read
9136                                     FIFO wait time over? interrupt */
9137       __IOM unsigned int RES : 24;                 /*!< [31..8] reserved5   */
9138     } SDIO_INTR_FN2_STATUS_CLEAR_REG_b;
9139   };
9140 
9141   union {
9142     __IOM unsigned int SDIO_INTR_FN2_ENABLE_REG; /*!< (@ 0x000000C4) SDIO Function1
9143                                                 Interrupt Enable Register */
9144 
9145     struct {
9146       __IOM unsigned int SDIO_WR_INT_EN : 1;      /*!< [0..0] This bit is used to enable
9147                                              CMD53 write interrupt.  */
9148       __IOM unsigned int SDIO_RD_INT_EN : 1;      /*!< [1..1] This bit is used to enable
9149                                              CMD53 read interrupt  */
9150       __IOM unsigned int SDIO_CSA_INT_EN : 1;     /*!< [2..2] This bit is used to enable
9151                                              CMD53 CSA interrupt */
9152       __IOM unsigned int SDIO_CMD52_INT_EN : 1;   /*!< [3..3] This bit is used to
9153                                                enable CMD52 interrupt */
9154       __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power
9155                                       level change interrupt            */
9156       __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to
9157                                                  enable CRC error interrupt */
9158       __IOM unsigned int SDIO_ABORT_INT_EN : 1;   /*!< [6..6] This bit is used to
9159                                                  enable abort interrupt   */
9160       __IOM unsigned int SDIO_TOUT_INT_EN : 1;    /*!< [7..7] This bit is used to enable ?read
9161                                    FIFO wait time over? interrupt */
9162       __IOM unsigned int RES : 24;                /*!< [31..8] reserved5  */
9163     } SDIO_INTR_FN2_ENABLE_REG_b;
9164   };
9165 
9166   union {
9167     __IOM unsigned int SDIO_INTR_FN2_MASK_REG; /*!< (@ 0x000000C8) SDIO Function2
9168                                               Interrupt Mask Register */
9169 
9170     struct {
9171       __IOM unsigned int SDIO_WR_INT_MSK : 1;  /*!< [0..0] This bit is used to mask
9172                                              CMD53 write interrupt */
9173       __IOM unsigned int SDIO_RD_INT_MSK : 1;  /*!< [1..1] This bit is used to mask
9174                                              CMD53 read interrupt */
9175       __IOM unsigned int SDIO_CSA_MSK : 1;     /*!< [2..2] This bit is used to mask CMD53 CSA
9176                                interrupt.Setting this bit will mask the
9177                                interrupt Clearing this bit has no effect */
9178       __IOM unsigned int SDIO_CMD52_MSK : 1;   /*!< [3..3] This bit is used to mask
9179                                               CMD52 interrupt   */
9180       __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask
9181                                               power level change interrupt */
9182       __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask
9183                                               CRC error interrupt */
9184       __IOM unsigned int SDIO_ABORT_MSK : 1;   /*!< [6..6] This bit is used to mask abort
9185                                  interrupt Setting this bit will mask the
9186                                  interrupt Clearing this bit has no effect */
9187       __IOM unsigned int SDIO_TOUT_MSK : 1;    /*!< [7..7] This bit is used to mask read FIFO wait
9188                                 time over interrupt        */
9189       __IOM unsigned int RES : 24;             /*!< [31..8] reserved5 */
9190     } SDIO_INTR_FN2_MASK_REG_b;
9191   };
9192 
9193   union {
9194     __IOM unsigned int SDIO_INTR_FN2_UNMASK_REG; /*!< (@ 0x000000CC) SDIO Function2
9195                                                 Interrupt Mask Register */
9196 
9197     struct {
9198       __IOM unsigned int SDIO_WR_INT_UNMSK : 1;  /*!< [0..0] This bit is used to
9199                                                unmask CMD53 write interrupt */
9200       __IOM unsigned int SDIO_RD_INT_UNMSK : 1;  /*!< [1..1] This bit is used to
9201                                                unmask CMD53 read interrupt */
9202       __IOM unsigned int SDIO_CSA_UNMSK : 1;     /*!< [2..2] This bit is used to unmask CMD53 CSA
9203                                  interrupt.Setting this bit will mask the
9204                                  interrupt Clearing this bit has no effect */
9205       __IOM unsigned int SDIO_CMD52_UNMSK : 1;   /*!< [3..3] This bit is used to
9206                                               unmask CMD52 interrupt */
9207       __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power
9208                                      level change interrupt            */
9209       __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to
9210                                                 unmask CRC error interrupt */
9211       __IOM
9212       unsigned int SDIO_ABORT_UNMSK : 1;      /*!< [6..6] This bit is used to unmask
9213                                             abort interrupt Setting this bit
9214                                             will mask the interrupt Clearing
9215                                             this bit has no effect */
9216       __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO
9217                                   wait time over interrupt      */
9218       __IOM unsigned int RES : 24;            /*!< [31..8] reserved5 */
9219     } SDIO_INTR_FN2_UNMASK_REG_b;
9220   };
9221 
9222   union {
9223     __IOM unsigned int SDIO_INTR_FN3_STATUS_CLEAR_REG; /*!< (@ 0x000000D0) SDIO Function3
9224                                            Status Clear Register */
9225 
9226     struct {
9227       __IOM unsigned int SDIO_WR_INT_CLR : 1;      /*!< [0..0] This bit is used to enable
9228                                              CMD53 write interrupt. =1
9229                                                      Interrupt is enabled =0 -
9230                                              Interrupt is disabled */
9231       __IOM unsigned int SDIO_RD_INT_CLR : 1;      /*!< [1..1] This bit is used to enable
9232                                              CMD53 read interrupt */
9233       __IOM unsigned int SDIO_CSA_INT_CLR : 1;     /*!< [2..2] This bit is used to
9234                                                 enable CMD53 CSA interrupt   */
9235       __IOM unsigned int SDIO_CMD52_INT_CLR : 1;   /*!< [3..3] This bit is used to
9236                                                 enable CMD52 interrupt */
9237       __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power
9238                                        level change interrupt            */
9239       __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC
9240                                        error interrupt                     */
9241       __IOM unsigned int SDIO_ABORT_INT_CLR : 1;   /*!< [6..6] This bit is used to
9242                                                 enable abort interrupt */
9243       __IOM unsigned int SDIO_TOUT_INT_CLR : 1;    /*!< [7..7] This bit is used to enable ?read
9244                                     FIFO wait time over? interrupt */
9245       __IOM unsigned int RES : 24;                 /*!< [31..8] reserved5   */
9246     } SDIO_INTR_FN3_STATUS_CLEAR_REG_b;
9247   };
9248 
9249   union {
9250     __IOM unsigned int SDIO_INTR_FN3_ENABLE_REG; /*!< (@ 0x000000D4) SDIO Function3
9251                                                 Interrupt Enable Register */
9252 
9253     struct {
9254       __IOM unsigned int SDIO_WR_INT_EN : 1;      /*!< [0..0] This bit is used to enable
9255                                              CMD53 write interrupt.  */
9256       __IOM unsigned int SDIO_RD_INT_EN : 1;      /*!< [1..1] This bit is used to enable
9257                                              CMD53 read interrupt  */
9258       __IOM unsigned int SDIO_CSA_INT_EN : 1;     /*!< [2..2] This bit is used to enable
9259                                              CMD53 CSA interrupt */
9260       __IOM unsigned int SDIO_CMD52_INT_EN : 1;   /*!< [3..3] This bit is used to
9261                                                enable CMD52 interrupt */
9262       __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power
9263                                       level change interrupt            */
9264       __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to
9265                                                  enable CRC error interrupt */
9266       __IOM unsigned int SDIO_ABORT_INT_EN : 1;   /*!< [6..6] This bit is used to
9267                                                  enable abort interrupt   */
9268       __IOM unsigned int SDIO_TOUT_INT_EN : 1;    /*!< [7..7] This bit is used to enable ?read
9269                                    FIFO wait time over? interrupt */
9270       __IOM unsigned int RES : 24;                /*!< [31..8] reserved5  */
9271     } SDIO_INTR_FN3_ENABLE_REG_b;
9272   };
9273 
9274   union {
9275     __IOM unsigned int SDIO_INTR_FN3_MASK_REG; /*!< (@ 0x000000D8) SDIO Function3
9276                                               Interrupt Mask Register */
9277 
9278     struct {
9279       __IOM unsigned int SDIO_WR_INT_MSK : 1;  /*!< [0..0] This bit is used to mask
9280                                              CMD53 write interrupt */
9281       __IOM unsigned int SDIO_RD_INT_MSK : 1;  /*!< [1..1] This bit is used to mask
9282                                              CMD53 read interrupt */
9283       __IOM unsigned int SDIO_CSA_MSK : 1;     /*!< [2..2] This bit is used to mask CMD53 CSA
9284                                interrupt.Setting this bit will mask the
9285                                interrupt Clearing this bit has no effect */
9286       __IOM unsigned int SDIO_CMD52_MSK : 1;   /*!< [3..3] This bit is used to mask
9287                                               CMD52 interrupt   */
9288       __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask
9289                                               power level change interrupt */
9290       __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask
9291                                               CRC error interrupt */
9292       __IOM unsigned int SDIO_ABORT_MSK : 1;   /*!< [6..6] This bit is used to mask abort
9293                                  interrupt Setting this bit will mask the
9294                                  interrupt Clearing this bit has no effect */
9295       __IOM unsigned int SDIO_TOUT_MSK : 1;    /*!< [7..7] This bit is used to mask read FIFO wait
9296                                 time over interrupt        */
9297       __IOM unsigned int RES : 24;             /*!< [31..8] reserved5 */
9298     } SDIO_INTR_FN3_MASK_REG_b;
9299   };
9300 
9301   union {
9302     __IOM unsigned int SDIO_INTR_FN3_UNMASK_REG; /*!< (@ 0x000000DC) SDIO Function3
9303                                                 Interrupt Mask Register */
9304 
9305     struct {
9306       __IOM unsigned int SDIO_WR_INT_UNMSK : 1;  /*!< [0..0] This bit is used to
9307                                                unmask CMD53 write interrupt */
9308       __IOM unsigned int SDIO_RD_INT_UNMSK : 1;  /*!< [1..1] This bit is used to
9309                                                unmask CMD53 read interrupt */
9310       __IOM unsigned int SDIO_CSA_UNMSK : 1;     /*!< [2..2] This bit is used to unmask CMD53 CSA
9311                                  interrupt.Setting this bit will mask the
9312                                  interrupt Clearing this bit has no effect */
9313       __IOM unsigned int SDIO_CMD52_UNMSK : 1;   /*!< [3..3] This bit is used to
9314                                               unmask CMD52 interrupt */
9315       __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power
9316                                      level change interrupt            */
9317       __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to
9318                                                 unmask CRC error interrupt */
9319       __IOM
9320       unsigned int SDIO_ABORT_UNMSK : 1;      /*!< [6..6] This bit is used to unmask
9321                                             abort interrupt Setting this bit
9322                                             will mask the interrupt Clearing
9323                                             this bit has no effect */
9324       __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO
9325                                   wait time over interrupt      */
9326       __IOM unsigned int RES : 24;            /*!< [31..8] reserved5 */
9327     } SDIO_INTR_FN3_UNMASK_REG_b;
9328   };
9329 
9330   union {
9331     __IOM unsigned int SDIO_INTR_FN4_STATUS_CLEAR_REG; /*!< (@ 0x000000E0) SDIO Function4
9332                                            Status Clear Register */
9333 
9334     struct {
9335       __IOM unsigned int SDIO_WR_INT_CLR : 1;      /*!< [0..0] This bit is used to enable
9336                                              CMD53 write interrupt. =1
9337                                                      Interrupt is enabled =0 -
9338                                              Interrupt is disabled */
9339       __IOM unsigned int SDIO_RD_INT_CLR : 1;      /*!< [1..1] This bit is used to enable
9340                                              CMD53 read interrupt */
9341       __IOM unsigned int SDIO_CSA_INT_CLR : 1;     /*!< [2..2] This bit is used to
9342                                                 enable CMD53 CSA interrupt   */
9343       __IOM unsigned int SDIO_CMD52_INT_CLR : 1;   /*!< [3..3] This bit is used to
9344                                                 enable CMD52 interrupt */
9345       __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power
9346                                        level change interrupt            */
9347       __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC
9348                                        error interrupt                     */
9349       __IOM unsigned int SDIO_ABORT_INT_CLR : 1;   /*!< [6..6] This bit is used to
9350                                                 enable abort interrupt */
9351       __IOM unsigned int SDIO_TOUT_INT_CLR : 1;    /*!< [7..7] This bit is used to enable ?read
9352                                     FIFO wait time over? interrupt */
9353       __IOM unsigned int RES : 24;                 /*!< [31..8] reserved5   */
9354     } SDIO_INTR_FN4_STATUS_CLEAR_REG_b;
9355   };
9356 
9357   union {
9358     __IOM unsigned int SDIO_INTR_FN4_ENABLE_REG; /*!< (@ 0x000000E4) SDIO Function4
9359                                                 Interrupt Enable Register */
9360 
9361     struct {
9362       __IOM unsigned int SDIO_WR_INT_EN : 1;      /*!< [0..0] This bit is used to enable
9363                                              CMD53 write interrupt.  */
9364       __IOM unsigned int SDIO_RD_INT_EN : 1;      /*!< [1..1] This bit is used to enable
9365                                              CMD53 read interrupt  */
9366       __IOM unsigned int SDIO_CSA_INT_EN : 1;     /*!< [2..2] This bit is used to enable
9367                                              CMD53 CSA interrupt */
9368       __IOM unsigned int SDIO_CMD52_INT_EN : 1;   /*!< [3..3] This bit is used to
9369                                                enable CMD52 interrupt */
9370       __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power
9371                                       level change interrupt            */
9372       __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to
9373                                                  enable CRC error interrupt */
9374       __IOM unsigned int SDIO_ABORT_INT_EN : 1;   /*!< [6..6] This bit is used to
9375                                                  enable abort interrupt   */
9376       __IOM unsigned int SDIO_TOUT_INT_EN : 1;    /*!< [7..7] This bit is used to enable ?read
9377                                    FIFO wait time over? interrupt */
9378       __IOM unsigned int RES : 24;                /*!< [31..8] reserved5  */
9379     } SDIO_INTR_FN4_ENABLE_REG_b;
9380   };
9381 
9382   union {
9383     __IOM unsigned int SDIO_INTR_FN4_MASK_REG; /*!< (@ 0x000000E8) SDIO Function4
9384                                               Interrupt Mask Register */
9385 
9386     struct {
9387       __IOM unsigned int SDIO_WR_INT_MSK : 1;  /*!< [0..0] This bit is used to mask
9388                                              CMD53 write interrupt */
9389       __IOM unsigned int SDIO_RD_INT_MSK : 1;  /*!< [1..1] This bit is used to mask
9390                                              CMD53 read interrupt */
9391       __IOM unsigned int SDIO_CSA_MSK : 1;     /*!< [2..2] This bit is used to mask CMD53 CSA
9392                                interrupt.Setting this bit will mask the
9393                                interrupt Clearing this bit has no effect */
9394       __IOM unsigned int SDIO_CMD52_MSK : 1;   /*!< [3..3] This bit is used to mask
9395                                               CMD52 interrupt   */
9396       __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask
9397                                               power level change interrupt */
9398       __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask
9399                                               CRC error interrupt */
9400       __IOM unsigned int SDIO_ABORT_MSK : 1;   /*!< [6..6] This bit is used to mask abort
9401                                  interrupt Setting this bit will mask the
9402                                  interrupt Clearing this bit has no effect */
9403       __IOM unsigned int SDIO_TOUT_MSK : 1;    /*!< [7..7] This bit is used to mask read FIFO wait
9404                                 time over interrupt        */
9405       __IOM unsigned int RES : 24;             /*!< [31..8] reserved5 */
9406     } SDIO_INTR_FN4_MASK_REG_b;
9407   };
9408 
9409   union {
9410     __IOM unsigned int SDIO_INTR_FN4_UNMASK_REG; /*!< (@ 0x000000EC) SDIO Function4
9411                                                 Interrupt Mask Register */
9412 
9413     struct {
9414       __IOM unsigned int SDIO_WR_INT_UNMSK : 1;  /*!< [0..0] This bit is used to
9415                                                unmask CMD53 write interrupt */
9416       __IOM unsigned int SDIO_RD_INT_UNMSK : 1;  /*!< [1..1] This bit is used to
9417                                                unmask CMD53 read interrupt */
9418       __IOM unsigned int SDIO_CSA_UNMSK : 1;     /*!< [2..2] This bit is used to unmask CMD53 CSA
9419                                  interrupt.Setting this bit will mask the
9420                                  interrupt Clearing this bit has no effect */
9421       __IOM unsigned int SDIO_CMD52_UNMSK : 1;   /*!< [3..3] This bit is used to
9422                                               unmask CMD52 interrupt */
9423       __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power
9424                                      level change interrupt            */
9425       __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to
9426                                                 unmask CRC error interrupt */
9427       __IOM
9428       unsigned int SDIO_ABORT_UNMSK : 1;      /*!< [6..6] This bit is used to unmask
9429                                             abort interrupt Setting this bit
9430                                             will mask the interrupt Clearing
9431                                             this bit has no effect */
9432       __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO
9433                                   wait time over interrupt      */
9434       __IOM unsigned int RES : 24;            /*!< [31..8] reserved5 */
9435     } SDIO_INTR_FN4_UNMASK_REG_b;
9436   };
9437 
9438   union {
9439     __IOM unsigned int SDIO_INTR_FN5_STATUS_CLEAR_REG; /*!< (@ 0x000000F0) SDIO Function5
9440                                            Status Clear Register */
9441 
9442     struct {
9443       __IOM unsigned int SDIO_WR_INT_CLR : 1;      /*!< [0..0] This bit is used to enable
9444                                              CMD53 write interrupt. =1
9445                                                      Interrupt is enabled =0 -
9446                                              Interrupt is disabled */
9447       __IOM unsigned int SDIO_RD_INT_CLR : 1;      /*!< [1..1] This bit is used to enable
9448                                              CMD53 read interrupt */
9449       __IOM unsigned int SDIO_CSA_INT_CLR : 1;     /*!< [2..2] This bit is used to
9450                                                 enable CMD53 CSA interrupt   */
9451       __IOM unsigned int SDIO_CMD52_INT_CLR : 1;   /*!< [3..3] This bit is used to
9452                                                 enable CMD52 interrupt */
9453       __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power
9454                                        level change interrupt            */
9455       __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC
9456                                        error interrupt                     */
9457       __IOM unsigned int SDIO_ABORT_INT_CLR : 1;   /*!< [6..6] This bit is used to
9458                                                 enable abort interrupt */
9459       __IOM unsigned int SDIO_TOUT_INT_CLR : 1;    /*!< [7..7] This bit is used to enable ?read
9460                                     FIFO wait time over? interrupt */
9461       __IOM unsigned int RES : 24;                 /*!< [31..8] reserved5   */
9462     } SDIO_INTR_FN5_STATUS_CLEAR_REG_b;
9463   };
9464 
9465   union {
9466     __IOM unsigned int SDIO_INTR_FN5_ENABLE_REG; /*!< (@ 0x000000F4) SDIO Function5
9467                                                 Interrupt Enable Register */
9468 
9469     struct {
9470       __IOM unsigned int SDIO_WR_INT_EN : 1;      /*!< [0..0] This bit is used to enable
9471                                              CMD53 write interrupt.  */
9472       __IOM unsigned int SDIO_RD_INT_EN : 1;      /*!< [1..1] This bit is used to enable
9473                                              CMD53 read interrupt  */
9474       __IOM unsigned int SDIO_CSA_INT_EN : 1;     /*!< [2..2] This bit is used to enable
9475                                              CMD53 CSA interrupt */
9476       __IOM unsigned int SDIO_CMD52_INT_EN : 1;   /*!< [3..3] This bit is used to
9477                                                enable CMD52 interrupt */
9478       __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power
9479                                       level change interrupt            */
9480       __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to
9481                                                  enable CRC error interrupt */
9482       __IOM unsigned int SDIO_ABORT_INT_EN : 1;   /*!< [6..6] This bit is used to
9483                                                  enable abort interrupt   */
9484       __IOM unsigned int SDIO_TOUT_INT_EN : 1;    /*!< [7..7] This bit is used to enable ?read
9485                                    FIFO wait time over? interrupt */
9486       __IOM unsigned int RES : 24;                /*!< [31..8] reserved5  */
9487     } SDIO_INTR_FN5_ENABLE_REG_b;
9488   };
9489 
9490   union {
9491     __IOM unsigned int SDIO_INTR_FN5_MASK_REG; /*!< (@ 0x000000F8) SDIO Function5
9492                                               Interrupt Mask Register */
9493 
9494     struct {
9495       __IOM unsigned int SDIO_WR_INT_MSK : 1;  /*!< [0..0] This bit is used to mask
9496                                              CMD53 write interrupt */
9497       __IOM unsigned int SDIO_RD_INT_MSK : 1;  /*!< [1..1] This bit is used to mask
9498                                              CMD53 read interrupt */
9499       __IOM unsigned int SDIO_CSA_MSK : 1;     /*!< [2..2] This bit is used to mask CMD53 CSA
9500                                interrupt.Setting this bit will mask the
9501                                interrupt Clearing this bit has no effect */
9502       __IOM unsigned int SDIO_CMD52_MSK : 1;   /*!< [3..3] This bit is used to mask
9503                                               CMD52 interrupt   */
9504       __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask
9505                                               power level change interrupt */
9506       __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask
9507                                               CRC error interrupt */
9508       __IOM unsigned int SDIO_ABORT_MSK : 1;   /*!< [6..6] This bit is used to mask abort
9509                                  interrupt Setting this bit will mask the
9510                                  interrupt Clearing this bit has no effect */
9511       __IOM unsigned int SDIO_TOUT_MSK : 1;    /*!< [7..7] This bit is used to mask read FIFO wait
9512                                 time over interrupt        */
9513       __IOM unsigned int RES : 24;             /*!< [31..8] reserved5 */
9514     } SDIO_INTR_FN5_MASK_REG_b;
9515   };
9516 
9517   union {
9518     __IOM unsigned int SDIO_INTR_FN5_UNMASK_REG; /*!< (@ 0x000000FC) SDIO Function5
9519                                                 Interrupt Mask Register */
9520 
9521     struct {
9522       __IOM unsigned int SDIO_WR_INT_UNMSK : 1;  /*!< [0..0] This bit is used to
9523                                                unmask CMD53 write interrupt */
9524       __IOM unsigned int SDIO_RD_INT_UNMSK : 1;  /*!< [1..1] This bit is used to
9525                                                unmask CMD53 read interrupt */
9526       __IOM unsigned int SDIO_CSA_UNMSK : 1;     /*!< [2..2] This bit is used to unmask CMD53 CSA
9527                                  interrupt.Setting this bit will mask the
9528                                  interrupt Clearing this bit has no effect */
9529       __IOM unsigned int SDIO_CMD52_UNMSK : 1;   /*!< [3..3] This bit is used to
9530                                               unmask CMD52 interrupt */
9531       __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power
9532                                      level change interrupt            */
9533       __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to
9534                                                 unmask CRC error interrupt */
9535       __IOM
9536       unsigned int SDIO_ABORT_UNMSK : 1;      /*!< [6..6] This bit is used to unmask
9537                                             abort interrupt Setting this bit
9538                                             will mask the interrupt Clearing
9539                                             this bit has no effect */
9540       __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO
9541                                   wait time over interrupt      */
9542       __IOM unsigned int RES : 24;            /*!< [31..8] reserved5 */
9543     } SDIO_INTR_FN5_UNMASK_REG_b;
9544   };
9545 
9546   union {
9547     __IOM unsigned int SDIO_ERROR_COND_CHK_ENABLE_REG; /*!< (@ 0x00000100) SDIO error condition
9548                                            check enable register */
9549 
9550     struct {
9551       __IOM unsigned int SDIO_CRC_EN : 1;               /*!< [0..0] When set, stops the DMA from doing data
9552                             accesses till CRC error interrupt is cleared */
9553       __IOM unsigned int SDIO_ABORT_EN : 1;             /*!< [1..1] When set, stops the DMA from doing data
9554                               accesses till ABORT interrupt is cleared */
9555       __IOM unsigned int SDIO_SPI_RD_DATA_ERROR_EN : 1; /*!< [2..2] When set, stops the DMA
9556                                           from doing data accesses till read
9557                                           data error interrupt is cleared in SPI
9558                                           mode                          */
9559       __IOM unsigned int RES : 29;                      /*!< [31..3] reserved5           */
9560     } SDIO_ERROR_COND_CHK_ENABLE_REG_b;
9561   };
9562 
9563   union {
9564     __IOM unsigned int SDIO_ERROR_COND_STATE_REG; /*!< (@ 0x00000104) SDIO error
9565                                                  condition state register */
9566 
9567     struct {
9568       __IOM unsigned int SDIO_ERROR_BYTE_CNT : 12; /*!< [11..0] Indicates byte count when one
9569                                        of the error condition occurred */
9570       __IOM unsigned int RESERVED1 : 4;            /*!< [15..12] RESERVED1 */
9571       __IOM unsigned int SDIO_ERROR_BLK_CNT : 7;   /*!< [22..16] Indicates block count when one
9572                                        of error condition occurred       */
9573       __IOM unsigned int RESERVED2 : 9;            /*!< [31..23] RESERVED2 */
9574     } SDIO_ERROR_COND_STATE_REG_b;
9575   };
9576 
9577   union {
9578     __IM unsigned int SDIO_BOOT_CONFIG_VALS_0_REG; /*!< (@ 0x00000108) SDIO Boot
9579                                                   Config Values Register 0 */
9580 
9581     struct {
9582       __IM unsigned int OCR_R : 24;     /*!< [23..0] Operating conditions. The value
9583                                        written by bootloader     can be read here.     */
9584       __IM unsigned int CSA_MSBYTE : 8; /*!< [31..24] MS byre of CSA address.  Lower
9585                                        24 bits of CSA will come through SDIO CSA
9586                                        registers.  Whenever CSA access is
9587                                                      done, 32-bit address will
9588                                        be prepared using these fields. */
9589     } SDIO_BOOT_CONFIG_VALS_0_REG_b;
9590   };
9591 
9592   union {
9593     __IM unsigned int SDIO_BOOT_CONFIG_VALS_1_REG; /*!< (@ 0x0000010C) SDIO Boot
9594                                                   Config Values Register 1 */
9595 
9596     struct {
9597       __IM unsigned int NO_OF_IO_FUNCTIONS : 3;              /*!< [2..0] Indicates number functions
9598                                      supported. The value written
9599                                            by bootloader can be read here. */
9600       __IM unsigned int COMBOCARD : 1;                       /*!< [3..3] When set, combo mode will be enabled. */
9601       __IM unsigned int SDMEM_IGNOTRE_SDMEM_PRESENT : 1;     /*!< [4..4] When set, sdmem_present
9602                                            signal, coming from GPIO, will be
9603                                            ignored. */
9604       __IM unsigned int SDMEM_DRIVE_HIZ_MB_READ : 1;         /*!< [5..5] When set, High will be driven
9605                                        in the second cycle of interrupt period
9606                                        during sd memory mb read transfer */
9607       __IM unsigned int SDMEM_DISABLE_INTERRUPT_MB_READ : 1; /*!< [6..6] When set,
9608                                                             interrupt will be
9609                                                             not be driven during
9610                                                             sd memory mb read
9611                                                             transfer */
9612       __IM unsigned int IGNORE_DISABLE_HS : 1;               /*!< [7..7] if ignore_disable_hs is set,
9613                                        sdmem_disable_high_speed_switching    coming
9614                                        from combo mode module is ignored    */
9615       __IM unsigned int RESERVED2 : 24;                      /*!< [31..8] RESERVED2 */
9616     } SDIO_BOOT_CONFIG_VALS_1_REG_b;
9617   };
9618 } SDIO0_Type; /*!< Size = 272 (0x110) */
9619 
9620 /* ===========================================================================================================================
9621  */
9622 /* ================                                         SPI_SLAVE
9623  * ================ */
9624 /* ===========================================================================================================================
9625  */
9626 
9627 /**
9628   * @brief The SPI Interface is a full duplex serial host interface, which
9629   supports 8-bit and 32-bit data granularity. It also supports gated mode of SPI
9630   clock and both the low and the high frequency modes (SPI_SLAVE)
9631   */
9632 
9633 typedef struct { /*!< (@ 0x20200000) SPI_SLAVE Structure */
9634 
9635   union {
9636     __IOM uint8_t SPI_HOST_INTR; /*!< (@ 0x00000000) SPI Host interupt resgister. */
9637 
9638     struct {
9639       __IOM uint8_t SPI_HOST_INTR : 8; /*!< [7..0] These bits indicate the interrupt
9640                                 vector value coming from system side. */
9641     } SPI_HOST_INTR_b;
9642   };
9643   __IM uint8_t RESERVED;
9644 
9645   union {
9646     __IOM uint8_t SPI_RFIFO_START; /*!< (@ 0x00000002) SPI FIFO start Level Register. */
9647 
9648     struct {
9649       __IOM uint8_t SPI_RFIFO_ST : 8; /*!< [7..0] These bits indicate the interrupt vector
9650                                value coming from system side. */
9651     } SPI_RFIFO_START_b;
9652   };
9653   __IM uint8_t RESERVED1;
9654 
9655   union {
9656     __IOM uint8_t SPI_RFIFO_AFULL_LEV; /*!< (@ 0x00000004) SPI RFIFO AFULL Level
9657                                           Register. */
9658 
9659     struct {
9660       __IOM uint8_t SPI_RFIFO_AFULL_LEV : 8; /*!< [7..0] These bits are used to program
9661                                       the FIFO occupancy level to trigger the
9662                                       Almost Full indication. */
9663     } SPI_RFIFO_AFULL_LEV_b;
9664   };
9665   __IM uint8_t RESERVED2;
9666 
9667   union {
9668     __IOM uint8_t SPI_RFIFO_AEMPTY_LEV; /*!< (@ 0x00000006) SPI WFIFO Almost
9669                                            Empty Register. */
9670 
9671     struct {
9672       __IOM uint8_t SPI_RFIFO_AEMPTY_LEV : 8; /*!< [7..0] These bits are used to
9673                                                  program the occupancy level to
9674                                                      trigger the Almost Empty
9675                                                  indication. */
9676     } SPI_RFIFO_AEMPTY_LEV_b;
9677   };
9678   __IM uint8_t RESERVED3;
9679 
9680   union {
9681     __IOM uint8_t SPI_MODE; /*!< (@ 0x00000008) SPI Mode Register. */
9682 
9683     struct {
9684       __IOM uint8_t SPI_OP_MODE : 1; /*!< [0..0] This bit is used to program the
9685                                         mode of working of SPI Interface. */
9686       __IOM uint8_t SPI_FIX_EN : 1;  /*!< [1..1] This bit is used to enable the
9687                                         fix made for bus_ctrl_busy  being asserted
9688                                         when success_state is being asserted
9689                                         getting  deasserted when FSM has decided
9690                                         to move to BUSY_STATE or  not.  */
9691       __IOM uint8_t VHS_EN : 1;      /*!< [2..2] This bit is used to enable Very high
9692                                    speed mode (120Mhz).          */
9693       __IOM uint8_t BYPASS_INIT : 1; /*!< [3..3] This bit is used to bypass the
9694                                         SPI initialization.0 -
9695                                                      Doesn't bypass,1 - bypasses
9696                                         SPI initialization */
9697       __IOM uint8_t RESERVED1 : 4;   /*!< [7..4] reserved1   */
9698     } SPI_MODE_b;
9699   };
9700   __IM uint8_t RESERVED4;
9701 
9702   union {
9703     __IOM uint16_t SPI_INTR_STATUS; /*!< (@ 0x0000000A) SPI interrupt status register. */
9704 
9705     struct {
9706       __IOM uint16_t SPI_WR_REQ : 1;      /*!< [0..0] Write request received. */
9707       __IOM uint16_t SPI_RD_REQ : 1;      /*!< [1..1] Read request received. */
9708       __IOM uint16_t SPI_CS_DEASSERT : 1; /*!< [2..2] SPI chip deassert interrupt.       */
9709       __IOM uint16_t RESERVED1 : 13;      /*!< [15..3] reserved1 */
9710     } SPI_INTR_STATUS_b;
9711   };
9712 
9713   union {
9714     __IOM uint16_t SPI_INTR_EN; /*!< (@ 0x0000000C) SPI interrupt enable register. */
9715 
9716     struct {
9717       __IOM uint16_t SPI_WR_INT_EN : 1;          /*!< [0..0] This bit is used to enable
9718                                            the write interrupt. */
9719       __IOM uint16_t SPI_RD_INT_EN : 1;          /*!< [1..1] This bit is used to enable
9720                                            the read interrupt. */
9721       __IOM uint16_t SPI_CS_DEASSERT_INT_EN : 1; /*!< [2..2] This bit is used to enable the
9722                                          interrupt due to wrong deassertion of
9723                                          CS. */
9724       __IOM uint16_t RESERVED1 : 13;             /*!< [15..3] reserved1  */
9725     } SPI_INTR_EN_b;
9726   };
9727 
9728   union {
9729     __IOM uint16_t SPI_INTR_MASK; /*!< (@ 0x0000000E) SPI interrupt Mask register */
9730 
9731     struct {
9732       __IOM uint16_t SPI_WR_INTR_MSK : 1;         /*!< [0..0] This bit is used to mask
9733                                              the write interrupt. */
9734       __IOM uint16_t SPI_RD_INTR_MSK : 1;         /*!< [1..1] This bit is used to mask
9735                                              the read interrupt. */
9736       __IOM uint16_t SPI_CS_DEASSERT_INT_MSK : 1; /*!< [2..2] This bit is used to mask the
9737                                           CS deassertion interrupt. */
9738       __IOM uint16_t RESERVED1 : 13;              /*!< [15..3] reserved1   */
9739     } SPI_INTR_MASK_b;
9740   };
9741 
9742   union {
9743     __IOM uint16_t SPI_INTR_UNMASK; /*!< (@ 0x00000010) SPI interrupt unmask register */
9744 
9745     struct {
9746       __IOM uint16_t SPI_WR_INT_UNMASK : 1;         /*!< [0..0] This bit is used to
9747                                                unmask the write interrupt. */
9748       __IOM uint16_t SPI_RD_INTR_UNMSK : 1;         /*!< [1..1] This bit is used to
9749                                                unmask the read interrupt. */
9750       __IOM uint16_t SPI_CS_DEASSERT_INT_UNMSK : 1; /*!< [2..2] This bit is used to unmask
9751                                             the CS deassertion interrupt. */
9752       __IOM uint16_t RESERVED1 : 13;                /*!< [15..3] reserved1     */
9753     } SPI_INTR_UNMASK_b;
9754   };
9755 
9756   union {
9757     __IM uint16_t SPI_LENGTH; /*!< (@ 0x00000012) SPI Length Register */
9758 
9759     struct {
9760       __IM uint16_t SPI_LEN : 16; /*!< [15..0] These bit indicate the length of
9761                                      the transfer as transmitted
9762                                                      in the Commands C3 and C4.
9763                                    */
9764     } SPI_LENGTH_b;
9765   };
9766 
9767   union {
9768     __IM uint16_t SPI_COMMAND; /*!< (@ 0x00000014) SPI Command Register */
9769 
9770     struct {
9771       __IM uint16_t SPI_C1 : 8; /*!< [7..0] These bits store the received command C1. */
9772       __IM uint16_t SPI_C2 : 8; /*!< [15..8] These bits store the received
9773                                    command C2.                         */
9774     } SPI_COMMAND_b;
9775   };
9776 
9777   union {
9778     __IM uint16_t SPI_DEV_ID; /*!< (@ 0x00000016) SPI Device ID Register */
9779 
9780     struct {
9781       __IM uint16_t SPI_DEVID : 16; /*!< [15..0] These bits store the Device ID
9782                                        information.                       */
9783     } SPI_DEV_ID_b;
9784   };
9785 
9786   union {
9787     __IM uint16_t SPI_VERSION; /*!< (@ 0x00000018) SPI Device ID Register */
9788 
9789     struct {
9790       __IM uint16_t SPI_VERNO : 8; /*!< [7..0] These bits store the version number. */
9791       __IM uint16_t RESERVED1 : 8; /*!< [15..8] reserved1 */
9792     } SPI_VERSION_b;
9793   };
9794 
9795   union {
9796     __IM uint16_t SPI_STATUS; /*!< (@ 0x0000001A) SPI Status Register */
9797 
9798     struct {
9799       __IM uint16_t SPI_RFIFO_FULL : 1;   /*!< [0..0] This bit indicates if the
9800                                             read FIFO is almost full.  */
9801       __IM uint16_t SPI_RFIFO_AFULL : 1;  /*!< [1..1] This bit indicates if the
9802                                             read FIFO is almost full. */
9803       __IM uint16_t SPI_WFIFO_EMPTY : 1;  /*!< [2..2] This bit indicates if write
9804                                             FIFO is empty. */
9805       __IM uint16_t SPI_WFIFO_AEMPTY : 1; /*!< [3..3] This bit indicates if
9806                                              write FIFO is almost empty. */
9807       __IM uint16_t SPI_RFIFO_EMPTY : 1;  /*!< [4..4] This bit indicates if read FIFO is
9808                                   empty (Read from SOC to host). */
9809       __IM uint16_t SPI_RFIFO_AEMPTY : 1; /*!< [5..5] This bit indicates if read FIFO is
9810                                    empty (Read from SOC to host). */
9811       __IM uint16_t SPI_WFIFO_FULL : 1;   /*!< [6..6] This bit indicates if write FIFO is
9812                                  full (Write from Host to SOC). */
9813       __IM uint16_t SPI_WFIFO_AFULL : 1;  /*!< [7..7] This bit indicates if write FIFO is
9814                                   full (Write from Host to SOC). */
9815       __IM uint16_t RESERVED1 : 8;        /*!< [15..8] reserved1 */
9816     } SPI_STATUS_b;
9817   };
9818 
9819   union {
9820     __IM uint16_t SPI_BC_STATE; /*!< (@ 0x0000001C) SPI Bus Controller State Register */
9821 
9822     struct {
9823       __IM uint16_t SPI_BC : 14;   /*!< [13..0] These bits indicate the Bus
9824                                       Controller FSM state.                 */
9825       __IM uint16_t RESERVED1 : 2; /*!< [15..14] reserved1 */
9826     } SPI_BC_STATE_b;
9827   };
9828   __IM uint16_t RESERVED5;
9829   __IM unsigned int RESERVED6[23];
9830 
9831   union {
9832     __IOM uint16_t SPI_SYS_RESET_REQ; /*!< (@ 0x0000007C) SPI SYS Reset Req Register */
9833 
9834     struct {
9835       __IOM
9836       uint16_t SPI_SYS_RESET_REQ : 1; /*!< [0..0] When set generates system reset
9837                                         request to reset controller. This gets
9838                                         reset once, reset controller generates
9839                                         reset. Host should not reset this bit.
9840                                         With this reset request, reset
9841                                         controller generates non por reset. */
9842       __IOM uint16_t RESERVED1 : 15;  /*!< [15..1] reserved1 */
9843     } SPI_SYS_RESET_REQ_b;
9844   };
9845 
9846   union {
9847     __IOM uint16_t SPI_WAKE_UP; /*!< (@ 0x0000007E) SPI Wakeup Register */
9848 
9849     struct {
9850       __IOM uint16_t SPI_WAKEUP : 1;        /*!< [0..0] Wakeup Interrupt,Interrupt for waking up
9851                              the system from Deep Sleep. */
9852       __IOM uint16_t SPI_DEEP_SLEEP_ST : 1; /*!< [1..1] Deep Sleep Start,Indicates the
9853                                         device to enter Deep Sleep
9854                                               state for maximum power save.     */
9855       __IOM uint16_t RESERVED1 : 14;        /*!< [15..2] reserved1 */
9856     } SPI_WAKE_UP_b;
9857   };
9858   __IM unsigned int RESERVED7[192];
9859 
9860   union {
9861     __IM unsigned int SPI_RFIFO_DATA; /*!< (@ 0x00000380) SPI RFIFO Data Register */
9862 
9863     struct {
9864       __IM unsigned int SPI_RFIFO : 32; /*!< [31..0] These bits store the data
9865                                        received from the host */
9866     } SPI_RFIFO_DATA_b;
9867   };
9868   __IM unsigned int RESERVED8[15];
9869 
9870   union {
9871     __OM unsigned int SPI_WFIFO_DATA; /*!< (@ 0x000003C0) SPI WFIFO Data Register */
9872 
9873     struct {
9874       __OM unsigned int SPI_WFIFO : 32; /*!< [31..0] These bits are used to write,
9875                                        the data to be sent to the host. */
9876     } SPI_WFIFO_DATA_b;
9877   };
9878 } SPI_SLAVE_Type; /*!< Size = 964 (0x3c4) */
9879 
9880 /* ===========================================================================================================================
9881  */
9882 /* ================                                           M4CLK
9883  * ================ */
9884 /* ===========================================================================================================================
9885  */
9886 
9887 /**
9888  * @brief MCU HP (High Performance) domain contains the Cortex-M4F Processor,
9889  * FPU, Debugger, MCU High Speed Interfaces, MCU HP Peripherals, MCU HP DMA and
9890  * MCU/SZP shareable Interfaces (M4CLK)
9891  */
9892 
9893 typedef struct { /*!< (@ 0x46000000) M4CLK Structure */
9894 
9895   union {
9896     __IOM unsigned int CLK_ENABLE_SET_REG1; /*!< (@ 0x00000000) Clock Enable Set
9897                                            Register 1 */
9898 
9899     struct {
9900       __IOM unsigned int USART1_PCLK_ENABLE_b : 1;          /*!< [0..0] Static Clock gating Enable for
9901                                        usart1 pclk1'b1 => Clock
9902                                           is enabled 1'b0 => Invalid */
9903       __IOM unsigned int USART1_SCLK_ENABLE_b : 1;          /*!< [1..1] Static Clock gating Enable for
9904                                        usart1 sclk1'b1 => Clock
9905                                           is enabled 1'b0 => Invalid */
9906       __IOM unsigned int USART2_PCLK_ENABLE_b : 1;          /*!< [2..2] Static Clock gating Enable for
9907                                        usart2 pclk1'b1 => Clock
9908                                           is enabled 1'b0 => Invalid */
9909       __IOM unsigned int USART2_SCLK_ENABLE_b : 1;          /*!< [3..3] Static Clock gating Enable for
9910                                        usart2 sclk1'b1 => Clock
9911                                           is enabled 1'b0 => Invalid */
9912       __IOM unsigned int Reserved1 : 5;                     /*!< [8..4] It is recommended to write these
9913                                        bits to 0.                        */
9914       __IOM unsigned int CT_CLK_ENABLE_b : 1;               /*!< [9..9] Static Clock gating Enable
9915                                             for sct clk1'b1 => Clock is
9916                                             enabled 1'b0 => Invalid. */
9917       __IOM unsigned int CT_PCLK_ENABLE_b : 1;              /*!< [10..10] Static Clock gating
9918                                              Enable for sct pclk1'b1 => Clock
9919                                              is enabled 1'b0 => Invalid. */
9920       __IOM unsigned int ICACHE_CLK_ENABLE_b : 1;           /*!< [11..11] Static Clock gating Enable for
9921                                      icache clk1'b1 => Clock
9922                                      is enabled 1'b0 => Invalid. */
9923       __IOM unsigned int ICACHE_CLK_2X_ENABLE_b : 1;        /*!< [12..12] Static Clock gating Enable
9924                                         for icache 2x clk1'b1 => Clock is
9925                                         enabled 1'b0 => Invalid. */
9926       __IOM unsigned int RPDMA_HCLK_ENABLE_b : 1;           /*!< [13..13] Static Clock gating Enable for
9927                                      rpdma hclk1'b1 => Clock
9928                                      is enabled 1'b0 => Invalid. */
9929       __IOM unsigned int SOC_PLL_SPI_CLK_ENABLE_b : 1;      /*!< [14..14] Static Clock gating Enable
9930                                           for soc pll spi clk1'b1
9931                                           => Clock is enabled 1'b0 => Invalid.
9932                                         */
9933       __IOM unsigned int Reserved2 : 1;                     /*!< [15..15] It is recommended to write
9934                                            these bits to 0.                      */
9935       __IOM unsigned int IID_CLK_ENABLE_b : 1;              /*!< [16..16] Static Clock gating
9936                                               Enable for iid clk1'b1 => Clock
9937                                                is enabled 1'b0 => Invalid. */
9938       __IOM unsigned int SDIO_SYS_HCLK_ENABLE_b : 1;        /*!< [17..17] Static Clock gating Enable
9939                                          for sdio sys hclk1'b1 => Clock is
9940                                          enabled 1'b0 => Invalid */
9941       __IOM unsigned int CRC_CLK_ENABLE_b : 1;              /*!< [18..18] Static Clock gating
9942                                               Enable for crc clk1'b1 => Clock
9943                                                is enabled 1'b0 => Invalid */
9944       __IOM unsigned int Reserved3 : 3;                     /*!< [21..19] It is recommended to write
9945                                        these bits to 0.                      */
9946       __IOM unsigned int HWRNG_PCLK_ENABLE_b : 1;           /*!< [22..22] Static Clock gating Enable for
9947                                       HWRNG pclk1'b1 => Clock
9948                                         is enabled 1'b0 => Invalid. */
9949       __IOM unsigned int GNSS_MEM_CLK_ENABLE_b : 1;         /*!< [23..23] Static Clock gating Enable
9950                                         for GNSS mem clk1'b1 =>
9951                                           Clock is enabled 1'b0 => Invalid */
9952       __IOM unsigned int Reserved4 : 3;                     /*!< [26..24] It is recommended to write
9953                                         these bits to 0.                      */
9954       __IOM unsigned int MASK_HOST_CLK_WAIT_FIX_b : 1;      /*!< [27..27] This bit decides whether
9955                                           to wait for a fixed number of xtal
9956                                           clock cycles(based on
9957                                           mask31_host_clk_cnt) or wait for a
9958                                           internally generated signal to come
9959                                           out of WAIT state in host mux FSM 1'b1
9960                                           => Wait for fixed number of xtal clk
9961                                           cycles 1'b0 => Invalid This bit along
9962                                           with mask_host_clk_available_fix and
9963                                           mask31_host_clk_cnt are to take care
9964                                           in case of any bugs. */
9965       __IOM unsigned int MASK31_HOST_CLK_CNT_b : 1;         /*!< [28..28] When mask_host_clk_wait_fix
9966                                        is 1'b1, this bit decides whether to
9967                                        count for 32 0r 16 xtal clock cycles to
9968                                        come out of WAIT state in host mux FSM
9969                                        1'b1 => Wait for 32 clock cycles 1'b0 =>
9970                                        Invalid This bit along with
9971                                        mask_host_clk_available_fix and
9972                                        mask_host_clk_wait_fix are to take care
9973                                        in case of any bugs. */
9974       __IOM unsigned int Reserved5 : 1;                     /*!< [29..29] It is recommended to write
9975                                         these bits to 0.                      */
9976       __IOM unsigned int MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides
9977                                                 whether to consider negedge of
9978                                                 host_clk_available in the
9979                                                 generation of clock enable for
9980                                                 host_clk gate in host mux 1'b1
9981                                                 => Don't consider 1'b0 =>
9982                                                 Invalid This bit along with
9983                                                 mask_host_clk_wait_fix and
9984                                                 mask31_host_clk_cnt
9985                                                        are to take care in case
9986                                                 of any bugs. */
9987       __IOM unsigned int ULPSS_CLK_ENABLE_b : 1;            /*!< [31..31] Static Clock gating Enable for
9988                                      m4 soc_clk to ulpss1'b1
9989                                           => Clock is enabled 1'b0 => Invalid.
9990                                    */
9991     } CLK_ENABLE_SET_REG1_b;
9992   };
9993 
9994   union {
9995     __IOM unsigned int CLK_ENABLE_CLEAR_REG1; /*!< (@ 0x00000004) Clock Enable Clear
9996                                              Register 1 */
9997 
9998     struct {
9999       __IOM unsigned int USART1_PCLK_ENABLE_b : 1;          /*!< [0..0] Static Clock Clear
10000                                                   for usart1 pclk1'b1 => Clock
10001                                                   is Clear 1'b0 => Invalid */
10002       __IOM unsigned int USART1_SCLK_ENABLE_b : 1;          /*!< [1..1] Static Clock Clear
10003                                                   for usart1 sclk1'b1 => Clock
10004                                                   is Clear 1'b0 => Invalid */
10005       __IOM unsigned int USART2_PCLK_ENABLE_b : 1;          /*!< [2..2] Static Clock Clear
10006                                                   for usart2 pclk 1'b1 => Clock
10007                                                   is Clear 1'b0 => Invalid */
10008       __IOM unsigned int USART2_SCLK_ENABLE_b : 1;          /*!< [3..3] Static Clock Clear
10009                                                   for usart2 sclk1'b1 => Clock
10010                                                   is Clear 1'b0 => Invalid */
10011       __IOM unsigned int Reserved1 : 5;                     /*!< [8..4] It is recommended to write these
10012                                        bits to 0.                        */
10013       __IOM unsigned int CT_CLK_ENABLE_b : 1;               /*!< [9..9] Static Clock Clear for sct clk1'b1 =>
10014                                   Clock is Clear 1'b0 => Invalid. */
10015       __IOM unsigned int CT_PCLK_ENABLE_b : 1;              /*!< [10..10] Static Clock Clear for
10016                                               sct pclk1'b1 => Clock is Clear
10017                                                1'b0 => Invalid. */
10018       __IOM unsigned int ICACHE_CLK_ENABLE_b : 1;           /*!< [11..11] Static Clock Clear
10019                                                  for icache clk1'b1 => Clock is
10020                                                  Clear 1'b0 => Invalid. */
10021       __IOM unsigned int ICACHE_CLK_2X_ENABLE_b : 1;        /*!< [12..12] Static Clock Clear for
10022                                          icache 2x clk1'b1 => Clock is Clear
10023                                          1'b0 => Invalid. */
10024       __IOM unsigned int RPDMA_HCLK_ENABLE_b : 1;           /*!< [13..13] Static Clock Clear
10025                                                  for rpdma hclk1'b1 => Clock is
10026                                                  Clear 1'b0 => Invalid. */
10027       __IOM unsigned int SOC_PLL_SPI_CLK_ENABLE_b : 1;      /*!< [14..14] Static Clock Clear for soc
10028                                           pll spi clk1'b1 => Clock
10029                                           is Clear 1'b0 => Invalid. */
10030       __IOM unsigned int Reserved2 : 1;                     /*!< [15..15] It is recommended to write
10031                                            these bits to 0.                      */
10032       __IOM unsigned int IID_CLK_ENABLE_b : 1;              /*!< [16..16] Static Clock Clear for iid clk1'b1
10033                                    => Clock is Clear 1'b0 => Invalid. */
10034       __IOM unsigned int SDIO_SYS_HCLK_ENABLE_b : 1;        /*!< [17..17] Static Clock Clear for sdio
10035                                          sys hclk1'b1 => Clock is
10036                                           Clear 1'b0 => Invalid */
10037       __IOM unsigned int CRC_CLK_ENABLE_b : 1;              /*!< [18..18] Static Clock Clear for crc clk1'b1
10038                                    => Clock is Clear 1'b0 => Invalid */
10039       __IOM unsigned int Reserved3 : 3;                     /*!< [21..19] It is recommended to write
10040                                        these bits to 0.                      */
10041       __IOM unsigned int HWRNG_PCLK_ENABLE_b : 1;           /*!< [22..22] Static Clock Clear
10042                                                    for HWRNG pclk1'b1 => Clock is
10043                                                    Clear   1'b0 => Invalid.   */
10044       __IOM unsigned int GNSS_MEM_CLK_ENABLE_b : 1;         /*!< [23..23] Static Clock Clear
10045                                                    for GNSS mem clk1'b1 => Clock
10046                                                    is Clear 1'b0 => Invalid */
10047       __IOM unsigned int Reserved4 : 3;                     /*!< [26..24] It is recommended to write
10048                                        these bits to 0.                      */
10049       __IOM unsigned int MASK_HOST_CLK_WAIT_FIX_b : 1;      /*!< [27..27] This bit decides whether
10050                                           to wait for a fixed number of xtal
10051                                           clock cycles(based on
10052                                           mask31_host_clk_cnt) or wait for a
10053                                           internally generated signal to come
10054                                           out of WAIT state in host mux FSM 1'b1
10055                                           => Wait for fixed number of xtal clk
10056                                           cycles 1'b0 => Invalid This bit along
10057                                           with mask_host_clk_available_fix and
10058                                           mask31_host_clk_cnt are to take care
10059                                           in case of any bugs. */
10060       __IOM unsigned int MASK31_HOST_CLK_CNT_b : 1;         /*!< [28..28] When mask_host_clk_wait_fix
10061                                        is 1'b1, this bit decides whether to
10062                                        count for 32 0r 16 xtal clock cycles to
10063                                        come out of WAIT state in host mux FSM
10064                                        1'b1 => Wait for 32 clock cycles 1'b0 =>
10065                                        Invalid This bit along with
10066                                        mask_host_clk_available_fix and
10067                                        mask_host_clk_wait_fix are to take care
10068                                        in case of any bugs. */
10069       __IOM unsigned int Reserved5 : 1;                     /*!< [29..29] It is recommended to write
10070                                         these bits to 0.                      */
10071       __IOM unsigned int MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides
10072                                                 whether to consider negedge of
10073                                                 host_clk_available in the
10074                                                 generation of clock enable for
10075                                                 host_clk gate in host mux 1'b1
10076                                                 => Don't consider 1'b0 =>
10077                                                 Invalid This bit along with
10078                                                 mask_host_clk_wait_fix and
10079                                                 mask31_host_clk_cnt
10080                                                        are to take care in case
10081                                                 of any bugs. */
10082       __IOM unsigned int ULPSS_CLK_ENABLE_b : 1;            /*!< [31..31] Static Clock gating Enable for
10083                                      m4 soc_clk to ulpss1'b1
10084                                           => Clock is enabled 1'b0 => Invalid.
10085                                    */
10086     } CLK_ENABLE_CLEAR_REG1_b;
10087   };
10088 
10089   union {
10090     __IOM unsigned int CLK_ENABLE_SET_REG2; /*!< (@ 0x00000008) Clock Enable Set
10091                                            Register 2 */
10092 
10093     struct {
10094       __IOM unsigned int GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable
10095                                              for gen spi master1 hclk 1'b1
10096                                                        => Clock is enabled 1'b0
10097                                              => Invalid */
10098       __IOM unsigned int Reserved1 : 5;                  /*!< [5..1] It is recommended to write these
10099                                        bits to 0.                        */
10100       __IOM unsigned int UDMA_HCLK_ENABLE_b : 1;         /*!< [6..6] Static Clock gating Enable for
10101                                      udma hclk 1'b1 => Clock
10102                                      is enabled 1'b0 => Invalid. */
10103       __IOM unsigned int I2C_BUS_CLK_ENABLE_b : 1;       /*!< [7..7] Static Clock gating Enable for
10104                                        i2c-1 bus clk1'b1 => Clock is enabled
10105                                        1'b0 => Invalid. */
10106       __IOM unsigned int I2C_2_BUS_CLK_ENABLE_b : 1;     /*!< [8..8] Static Clock gating Enable for
10107                                          i2c-2 bus clk 1'b1 =>
10108                                          Clock is enabled 1'b0 => Invalid. */
10109       __IOM unsigned int SSI_SLV_PCLK_ENABLE_b : 1;      /*!< [9..9] Static Clock gating Enable for
10110                                         ssi slave pclk 1'b1 =>
10111                                         Clock is enabled 1'b0 => Invalid. */
10112       __IOM
10113       unsigned int SSI_SLV_SCLK_ENABLE_b : 1;         /*!< [10..10] Static Clock gating
10114                                                  Enable for ssi slave sclk 1'b1
10115                                                  => Clock is enabled 1'b0 =>
10116                                                  Invalid. */
10117       __IOM unsigned int QSPI_CLK_ENABLE_b : 1;       /*!< [11..11] Static Clock gating
10118                                                  Enable for qspi clk 1'b1 => Clock
10119                                                  is enabled 1'b0 => Invalid.   */
10120       __IOM unsigned int QSPI_HCLK_ENABLE_b : 1;      /*!< [12..12] Static Clock gating Enable for
10121                                      qspi hclk 1'b1 => Clock
10122                                      is enabled 1'b0 => Invalid. */
10123       __IOM unsigned int I2SM_SCLK_ENABLE_b : 1;      /*!< [13..13] Static Clock gating Enable for
10124                                      sclk of I2S at Root Clock generation 1'b1
10125                                      => Clock is enabled 1'b0 => Invalid. */
10126       __IOM unsigned int I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable
10127                                           for i2s interface sclk 1'b1
10128                                           => Clock is enabled 1'b0 => Invalid.
10129                                         */
10130       __IOM unsigned int I2SM_PCLK_ENABLE_b : 1;      /*!< [15..15] Static Clock gating Enable for
10131                                        i2s master pclk 1'b1
10132                                        => Clock is enabled 1'b0 => Invalid.   */
10133       __IOM unsigned int Reserved2 : 1;               /*!< [16..16] It is recommended to write
10134                                        these bits to 0.                      */
10135       __IOM unsigned int QE_PCLK_ENABLE_b : 1;        /*!< [17..17] Static Clock gating Enable for qe
10136                                    pclk 1'b1 => Clock is enabled 1'b0 =>
10137                                    Invalid. */
10138       __IOM unsigned int MCPWM_PCLK_ENABLE_b : 1;     /*!< [18..18] Static Clock gating Enable for
10139                                        mcpwm pclk 1'b1 => Clock  is enabled 1'b0
10140                                        => Invalid.  */
10141       __IOM unsigned int Reserved3 : 1;               /*!< [19..19] It is recommended to write
10142                                        these bits to 0.                      */
10143       __IOM unsigned int SGPIO_PCLK_ENABLE_b : 1;     /*!< [20..20] Static Clock gating Enable for
10144                                       sgpio pclk 1'b1 => Clock is enabled 1'b0
10145                                       => Invalid. */
10146       __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1;     /*!< [21..21] Static Clock gating Enable for
10147                                       egpio pclk 1'b1 => Clock is enabled 1'b0
10148                                       => Invalid. */
10149       __IOM unsigned int ARM_CLK_ENABLE_b : 1;        /*!< [22..22] Static Clock gating
10150                                               Enable for arm clk 1'b1 => Clock
10151                                                 is enabled 1'b0 => Invalid. */
10152       __IOM unsigned int SSI_MST_PCLK_ENABLE_b : 1;   /*!< [23..23] Static Clock gating Enable
10153                                         for ssi master pclk 1'b1
10154                                           => Clock is enabled 1'b0 => Invalid.
10155                                       */
10156       __IOM unsigned int SSI_MST_SCLK_ENABLE_b : 1;   /*!< [24..24] Static Clock gating Enable
10157                                         for ssi master sclk 1'b1
10158                                           => Clock is enabled 1'b0 => Invalid.
10159                                       */
10160       __IOM unsigned int Reserved4 : 1;               /*!< [25..25] It is recommended to write
10161                                         these bits to 0.                      */
10162       __IOM unsigned int MEM_CLK_ULP_ENABLE_b : 1;    /*!< [26..26] Static Clock gating Enable for
10163                                        mem ulp clk 1'b1 =>
10164                                          Clock is enabled 1'b0 => Invalid. */
10165       __IOM unsigned int ROM_CLK_ENABLE_b : 1;        /*!< [27..27] Static Clock gating
10166                                               Enable for rom clk 1'b1 => Clock
10167                                                 is enabled 1'b0 => Invalid. */
10168       __IOM unsigned int PLL_INTF_CLK_ENABLE_b : 1;   /*!< [28..28] Static Clock gating Enable
10169                                         for pll intf clk 1'b1 => Clock is
10170                                         enabled 1'b0 => Invalid. */
10171       __IOM unsigned int Reserved5 : 3;               /*!< [31..29] It is recommended to write
10172                                         these bits to 0.                      */
10173     } CLK_ENABLE_SET_REG2_b;
10174   };
10175 
10176   union {
10177     __IOM unsigned int CLK_ENABLE_CLEAR_REG2; /*!< (@ 0x0000000C) Clock Enable Clear
10178                                              Register 2 */
10179 
10180     struct {
10181       __IOM unsigned int GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for gen
10182                                              spi master1 hclk 1'b1 => Clock is
10183                                              Clear 1'b0 => Invalid */
10184       __IOM unsigned int Reserved1 : 5;                  /*!< [5..1] It is recommended to write these
10185                                        bits to 0.                        */
10186       __IOM unsigned int UDMA_HCLK_ENABLE_b : 1;         /*!< [6..6] Static Clock Clear for
10187                                                 udma hclk 1'b1 => Clock is Clear
10188                                                  1'b0 => Invalid. */
10189       __IOM unsigned int I2C_BUS_CLK_ENABLE_b : 1;       /*!< [7..7] Static Clock Clear
10190                                                   for i2c-1 bus clk1'b1 => Clock
10191                                                   is Clear 1'b0 => Invalid. */
10192       __IOM unsigned int I2C_2_BUS_CLK_ENABLE_b : 1;     /*!< [8..8] Static Clock Clear for i2c-2
10193                                          bus clk 1'b1 => Clock is
10194                                           Clear 1'b0 => Invalid. */
10195       __IOM unsigned int SSI_SLV_PCLK_ENABLE_b : 1;      /*!< [9..9] Static Clock Clear for ssi
10196                                         slave pclk 1'b1 => Clock is Clear 1'b0
10197                                         => Invalid. */
10198       __IOM unsigned int SSI_SLV_SCLK_ENABLE_b : 1;      /*!< [10..10] Static Clock Clear for ssi
10199                                         slave sclk 1'b1 => Clock is Clear 1'b0
10200                                         => Invalid. */
10201       __IOM unsigned int QSPI_CLK_ENABLE_b : 1;          /*!< [11..11] Static Clock Clear for qspi clk
10202                                     1'b1 => Clock is Clear 1'b0 => Invalid. */
10203       __IOM unsigned int QSPI_HCLK_ENABLE_b : 1;         /*!< [12..12] Static Clock Clear
10204                                                 for qspi hclk 1'b1 => Clock is
10205                                                 Clear 1'b0 => Invalid. */
10206       __IOM unsigned int I2SM_SCLK_ENABLE_b : 1;         /*!< [13..13] Static Clock Clear
10207                                                 for sclk of I2S at Root Clock
10208                                                 generation 1'b1 => Clock is
10209                                                 Clear 1'b0 => Invalid. */
10210       __IOM unsigned int I2SM_INTF_SCLK_ENABLE_b : 1;    /*!< [14..14] Static Clock Clear for i2s
10211                                           interface sclk 1'b1 => Clock
10212                                           is Clear 1'b0 => Invalid. */
10213       __IOM unsigned int I2SM_PCLK_ENABLE_b : 1;         /*!< [15..15] Static Clock Clear for i2s
10214                                        master pclk 1'b1 => Clock
10215                                        is Clear 1'b0 => Invalid.   */
10216       __IOM unsigned int Reserved2 : 1;                  /*!< [16..16] It is recommended to write
10217                                        these bits to 0.                      */
10218       __IOM unsigned int QE_PCLK_ENABLE_b : 1;           /*!< [17..17] Static Clock Clear for qe pclk
10219                                    1'b1 => Clock is Clear 1'b0 => Invalid. */
10220       __IOM unsigned int MCPWM_PCLK_ENABLE_b : 1;        /*!< [18..18] Static Clock Clear
10221                                                  for mcpwm pclk 1'b1 => Clock is
10222                                                      Clear 1'b0 => Invalid. */
10223       __IOM unsigned int Reserved3 : 1;                  /*!< [19..19] It is recommended to write
10224                                        these bits to 0.                      */
10225       __IOM unsigned int SGPIO_PCLK_ENABLE_b : 1;        /*!< [20..20] Static Clock Clear
10226                                                  for sgpio pclk 1'b1 => Clock is
10227                                                    Clear 1'b0 => Invalid. */
10228       __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1;        /*!< [21..21] Static Clock Clear
10229                                                  for egpio pclk 1'b1 => Clock is
10230                                                    Clear 1'b0 => Invalid. */
10231       __IOM unsigned int ARM_CLK_ENABLE_b : 1;           /*!< [22..22] Static Clock Clear for arm clk
10232                                    1'b1 => Clock is Clear 1'b0 => Invalid. */
10233       __IOM unsigned int SSI_MST_PCLK_ENABLE_b : 1;      /*!< [23..23] Static Clock Clear for ssi
10234                                         master pclk 1'b1 => Clock
10235                                           is Clear 1'b0 => Invalid. */
10236       __IOM unsigned int SSI_MST_SCLK_ENABLE_b : 1;      /*!< [24..24] Static Clock Clear for ssi
10237                                         master sclk 1'b1 => Clock
10238                                           is Clear 1'b0 => Invalid. */
10239       __IOM unsigned int Reserved4 : 1;                  /*!< [25..25] It is recommended to write
10240                                         these bits to 0.                      */
10241       __IOM unsigned int MEM_CLK_ULP_ENABLE_b : 1;       /*!< [26..26] Static Clock Clear
10242                                                   for mem ulp clk 1'b1 => Clock
10243                                                   is Clear 1'b0 => Invalid. */
10244       __IOM unsigned int ROM_CLK_ENABLE_b : 1;           /*!< [27..27] Static Clock Clear for rom clk
10245                                    1'b1 => Clock is Clear 1'b0 => Invalid. */
10246       __IOM unsigned int PLL_INTF_CLK_ENABLE_b : 1;      /*!< [28..28] Static Clock Clear for pll
10247                                         intf clk 1'b1 => Clock is
10248                                           Clear 1'b0 => Invalid. */
10249       __IOM unsigned int Reserved5 : 3;                  /*!< [31..29] It is recommended to write
10250                                         these bits to 0.                      */
10251     } CLK_ENABLE_CLEAR_REG2_b;
10252   };
10253 
10254   union {
10255     __IOM unsigned int CLK_ENABLE_SET_REG3; /*!< (@ 0x00000010) Clock Enable Set
10256                                            Register 3 */
10257 
10258     struct {
10259       __IOM unsigned int BUS_CLK_ENABLE_b : 1;                   /*!< [0..0] Static Clock gating
10260                                               Enable for bus clk 1'b1 => Clock
10261                                                  is enabled 1'b0 => Invalid */
10262       __IOM unsigned int M4_CORE_CLK_ENABLE_b : 1;               /*!< [1..1] Static Clock gating Enable for
10263                                        M4 Core clk 1'b1 => Clock
10264                                           is enabled 1'b0 => Invalid. */
10265       __IOM unsigned int CM_BUS_CLK_ENABLE_b : 1;                /*!< [2..2] Static Clock gating Enable for cm
10266                                       bus clk1'b1 => Clock is enabled1'b0 =>
10267                                       Invalid. */
10268       __IOM unsigned int Reserved1 : 1;                          /*!< [3..3] It is recommended to write these
10269                                        bits to 0.                        */
10270       __IOM unsigned int MISC_CONFIG_PCLK_ENABLE_b : 1;          /*!< [4..4] Static Clock gating Enable
10271                                             for misc config regs clk 1'b1
10272                                                  => Clock is enabled 1'b0 =>
10273                                             Invalid. */
10274       __IOM unsigned int EFUSE_CLK_ENABLE_b : 1;                 /*!< [5..5] Static Clock gating Enable for
10275                                      efuse clk 1'b1 => Clock
10276                                           is enabled 1'b0 => Invalid. */
10277       __IOM unsigned int ICM_CLK_ENABLE_b : 1;                   /*!< [6..6] Static Clock gating Enable for icm
10278                                    clk 1'b1 => Clock
10279                                         is enabled 1'b0 => Invalid. */
10280       __IOM unsigned int Reserved2 : 6;                          /*!< [12..7] It is recommended to write
10281                                        these bits to 0.                       */
10282       __IOM unsigned int QSPI_CLK_ONEHOT_ENABLE_b : 1;           /*!< [13..13] Static Clock gating Enable
10283                                           for QSPI clock generated from the
10284                                           dynamic mux 1b1 - Clock is enabled 1b0
10285                                           - Invalid.                */
10286       __IOM unsigned int QSPI_M4_SOC_SYNC_b : 1;                 /*!< [14..14] Specifies whether QSPI clock is
10287                                      in sync with Soc clock. Before enabling
10288                                      this make sure that qspi_clk_onehot_enable
10289                                           is 1b0 to enable glitch free switching
10290                                      1b1 - QSPI clock is in sync with M4 clock
10291                                      1b0 - Invalid. */
10292       __IOM unsigned int Reserved3 : 1;                          /*!< [15..15] It is recommended to write
10293                                        these bits to 0.                      */
10294       __IOM unsigned int EGPIO_CLK_ENABLE_b : 1;                 /*!< [16..16] Static Clock gating enable for
10295                                      Enhanced-GPIO 1b1 -
10296                                          Clock is enabled 1b0 - Invalid. */
10297       __IOM unsigned int I2C_CLK_ENABLE_b : 1;                   /*!< [17..17] Static Clock gating enable for
10298                                    I2C-1 Module 1b1 - Clock is enabled 1b0 -
10299                                    Invalid. */
10300       __IOM unsigned int I2C_2_CLK_ENABLE_b : 1;                 /*!< [18..18] Static Clock gating enable for
10301                                      I2C-2 Module 1b1 - Clock is enabled 1b0 -
10302                                      Invalid. */
10303       __IOM unsigned int EFUSE_PCLK_ENABLE_b : 1;                /*!< [19..19] Static Clock gating
10304                                                  enable for EFUSE APB Interface
10305                                                      1b1 - Clock is enabled 1b0
10306                                                  - Invalid. */
10307       __IOM unsigned int SGPIO_CLK_ENABLE_b : 1;                 /*!< [20..20] Static Clock gating enable for
10308                                      SIO Module 1b1 - Clock is enabled 1b0 -
10309                                      Invalid. */
10310       __IOM unsigned int TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1;  /*!< [21..21] Unused. */
10311       __IOM unsigned int TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */
10312       __IOM unsigned int TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */
10313       __IOM unsigned int Reserved4 : 1;                          /*!< [24..24] It is recommended to write
10314                                        these bits to 0.                      */
10315       __IOM unsigned int ROM_MISC_STATIC_ENABLE_b : 1;           /*!< [25..25] Static Clock gating enable
10316                                           for rom ahb Clock 1b1 - Clock is
10317                                           enabled 1b0 - Invalid. */
10318       __IOM unsigned int M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1;      /*!< [26..26] Static Clock gating
10319                                                 enable for M4-SOC Other Clock
10320                                                 1b1
10321                                                        - Clock is enabled 1b0 -
10322                                                 Invalid. */
10323       __IOM unsigned int ICACHE_ENABLE_b : 1;                    /*!< [27..27] Static Clock gating enable for
10324                                        Icache. This has to      be enable for Icache
10325                                        operations. 1b1 - Clock is enabled      1b0 -
10326                                        Invalid.      */
10327       __IOM unsigned int Reserved5 : 4;                          /*!< [31..28] It is recommended to write
10328                                        these bits to 0.                      */
10329     } CLK_ENABLE_SET_REG3_b;
10330   };
10331 
10332   union {
10333     __IOM unsigned int CLK_ENABLE_CLEAR_REG3; /*!< (@ 0x00000014) Clock Enable Clear
10334                                              Register 3 */
10335 
10336     struct {
10337       __IOM unsigned int BUS_CLK_ENABLE_b : 1;                   /*!< [0..0] Static Clock Clear for bus clk 1'b1
10338                                    => Clock is Clear 1'b0 => Invalid */
10339       __IOM unsigned int M4_CORE_CLK_ENABLE_b : 1;               /*!< [1..1] Static Clock Clear
10340                                                   for M4 Core clk 1'b1 => Clock
10341                                                   is Clear 1'b0 => Invalid. */
10342       __IOM unsigned int CM_BUS_CLK_ENABLE_b : 1;                /*!< [2..2] Static Clock gating Enable for cm
10343                                       bus clk1'b1 => Clock is enabled1'b0 =>
10344                                       Invalid. */
10345       __IOM unsigned int Reserved1 : 1;                          /*!< [3..3] It is recommended to write these
10346                                        bits to 0.                        */
10347       __IOM unsigned int MISC_CONFIG_PCLK_ENABLE_b : 1;          /*!< [4..4] Static Clock Clear for misc
10348                                             config regs clk 1'b1 => Clock is
10349                                             Clear 1'b0 => Invalid. */
10350       __IOM unsigned int EFUSE_CLK_ENABLE_b : 1;                 /*!< [5..5] Static Clock Clear for
10351                                                 efuse clk 1'b1 => Clock is Clear
10352                                                      1'b0 => Invalid. */
10353       __IOM unsigned int ICM_CLK_ENABLE_b : 1;                   /*!< [6..6] Static Clock Clear for icm clk 1'b1
10354                                    => Clock is Clear 1'b0 => Invalid. */
10355       __IOM unsigned int Reserved2 : 6;                          /*!< [12..7] It is recommended to write
10356                                        these bits to 0.                       */
10357       __IOM unsigned int QSPI_CLK_ONEHOT_ENABLE_b : 1;           /*!< [13..13] Static Clock Clear for
10358                                           QSPI clock generated from the
10359                                           dynamic mux 1b1 - Clock is Gated 1b0 -
10360                                           Invalid.                           */
10361       __IOM unsigned int QSPI_M4_SOC_SYNC_b : 1;                 /*!< [14..14] Specifies whether QSPI clock is
10362                                      in sync with Soc clock. Before enabling
10363                                      this make sure that qspi_clk_onehot_enable
10364                                           is 1b0 to enable glitch free switching
10365                                      1b1 - QSPI clock is in sync with M4 clock
10366                                      1b0 - Invalid. */
10367       __IOM unsigned int Reserved3 : 1;                          /*!< [15..15] It is recommended to write
10368                                        these bits to 0.                      */
10369       __IOM unsigned int EGPIO_CLK_ENABLE_b : 1;                 /*!< [16..16] Static Clock Disable for
10370                                      Enhanced-GPIO 1b1 - Clock
10371                                          is Disable 1b0 - Invalid. */
10372       __IOM unsigned int I2C_CLK_ENABLE_b : 1;                   /*!< [17..17] Static Clock Disable
10373                                                 for I2C-1 Module 1b1 - Clock is
10374                                                     Disable 1b0 - Invalid.   */
10375       __IOM unsigned int I2C_2_CLK_ENABLE_b : 1;                 /*!< [18..18] Static Clock Disable
10376                                                 for I2C-2 Module 1b1 - Clock is
10377                                                     Disable 1b0 - Invalid. */
10378       __IOM unsigned int EFUSE_PCLK_ENABLE_b : 1;                /*!< [19..19] Static Clock Disable for EFUSE
10379                                       APB Interface 1b1 -
10380                                           Clock is Disable 1b0 - Invalid. */
10381       __IOM unsigned int SGPIO_CLK_ENABLE_b : 1;                 /*!< [20..20] Static Clock gating enable for
10382                                      SIO Module 1b1 - Clock is enabled 1b0 -
10383                                      Invalid. */
10384       __IOM unsigned int TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1;  /*!< [21..21] Unused. */
10385       __IOM unsigned int TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */
10386       __IOM unsigned int TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */
10387       __IOM unsigned int Reserved4 : 1;                          /*!< [24..24] It is recommended to write
10388                                        these bits to 0.                      */
10389       __IOM unsigned int ROM_MISC_STATIC_ENABLE_b : 1;           /*!< [25..25] Static Clock Disable for
10390                                           rom ahb Clock 1b1 - Clock is Disable
10391                                           1b0 - Invalid. */
10392       __IOM unsigned int M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1;      /*!< [26..26] Static Clock Disable
10393                                                 for M4-SOC Other Clock 1b1 -
10394                                                 Clock
10395                                                        is Disable 1b0 - Invalid.
10396                                               */
10397       __IOM unsigned int ICACHE_ENABLE_b : 1;                    /*!< [27..27] Static Clock Disable for Icache.
10398                                   This has to be enable for Icache operations.
10399                                   1b1 - Clock is Disable 1b0 - Invalid. */
10400       __IOM unsigned int Reserved5 : 4;                          /*!< [31..28] It is recommended to write
10401                                        these bits to 0.                      */
10402     } CLK_ENABLE_CLEAR_REG3_b;
10403   };
10404 
10405   union {
10406     __IOM unsigned int CLK_CONFIG_REG1; /*!< (@ 0x00000018) Clock Config Register 1 */
10407 
10408     struct {
10409       __IOM unsigned int QSPI_CLK_SEL : 3;     /*!< [2..0] Selects one of the following clocks for
10410                                ssi master 000
10411                                   - ULP Ref Clock(generated inside M4SS based on
10412                                m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock
10413                                Clock (program bypass_intf_pll_clk if the bypass
10414                                clock has to be selected) 010 - Modem PLL
10415                                   Clock2(Not Intended for the programmer)
10416                                (program bypass_modem_pll_clk
10417                                   if the bypass clock has to be selected) 011 -
10418                                SoC PLL Clock               */
10419       __IOM unsigned int QSPI_CLK_DIV_FAC : 6; /*!< [8..3] Clock divison factor for QSPI. If
10420                                    qspi_clk_enable is 1b0 clock is gated. Else
10421                                    1)when qspi_clk_swallow_sel is 1b1 and
10422                                    qspi_odd_div_sel is 1b0 output clock is a
10423                                    swallowed clock with the following frequency.
10424                                    6h0,6h1 => clk_out = clk_in >6h1 => clk_out =
10425                                    clk_in/ qspi_clk_div_fac 2)when
10426                                       qspi_clk_swallow_sel is 1b0 */
10427       __IOM
10428       unsigned int QSPI_CLK_SWALLOW_SEL : 1;           /*!< [9..9] Clock select for clock
10429                                             swallow or clock divider for QSPI  1b0
10430                                             => 50% divider is selected with
10431                                             division factor qspi_clk_div_fac  1b1
10432                                             => Swallowed clock is selected with
10433                                             division factor  qspi_clk_div_fac
10434                                             Before Changing this ensure that the
10435                                             input  clocks are gated  */
10436       __IOM unsigned int SLP_RF_CLK_SEL : 1;           /*!< [10..10] clock select for
10437                                             m4_soc_rf_ref_clk 0 - m4_soc_clk 1
10438                                                - rf_ref_clk. */
10439       __IOM unsigned int SSI_MST_SCLK_DIV_FAC : 4;     /*!< [14..11] Clock division factor for
10440                                        ssi_mst_sclk. If ssi_mst_sclk_enable is
10441                                        1b0 clock is gated. Else output clock is
10442                                        a swallowed clock with the following
10443                                        frequency. 4h0,4h1 => Divider
10444                                               is bypassed >4h1 => clk_out =
10445                                        clk_in/ ssi_mst_sclk_div_fac. */
10446       __IOM unsigned int SSI_MST_SCLK_SEL : 3;         /*!< [17..15] Selects one of the following
10447                                    clocks for ssi master 000 - ULP Ref
10448                                    Clock(generated inside M4SS based on
10449                                    m4ss_ref_clk_sel from NPSS) 001 - SoC PLL
10450                                    Clock(program bypass_soc_pll_clk if the
10451                                    bypass clock has to be selected) 010 - Modem
10452                                    PLL Clock1(Not Intended for the programmer)
10453                                    (program bypass_modem_pll_clk if the bypass
10454                                    clock has to be selected) 011 - Intf PLL
10455                                           Clock(program bypass_intf_pll_clk if
10456                                    the                                  */
10457       __IOM unsigned int PLL_INTF_CLK_SEL : 1;         /*!< [18..18] Selects one of the following
10458                                    clocks for pll intf clock 0 - Intf Pll
10459                                    Clock(program bypass_intf_pll_clk if the
10460                                    bypass clock has to be selected) 1 - SoC Pll
10461                                    Clock(program bypass_soc_pll_clk if the
10462                                    bypass clock has to be selected) */
10463       __IOM unsigned int PLL_INTF_CLK_DIV_FAC : 4;     /*!< [22..19] Clock division factor for
10464                                        pll_intf_clk. If pll_intf_clk_enable is
10465                                        1b0 clock is gated. Else, when
10466                                        pll_intf_clk_swallow_sel is 1b1, output
10467                                        clock is a swallowed clock. when
10468                                        pll_intf_clk_swallow_sel is 1b0, output
10469                                        clock is a 50 Per duty cycle clock. */
10470       __IOM unsigned int PLL_INTF_CLK_SWALLOW_SEL : 1; /*!< [23..23] Clock select for clock
10471                                           swallow or clock divider for PLL INTF
10472                                           Clk 1b0 - 50% divider is selected with
10473                                           division factor 2; 1b1 - Swallowed
10474                                           clock is selected with division
10475                                           factor pll_intf_clk_div_fac */
10476       __IOM unsigned int GEN_SPI_MST1_SCLK_SEL : 3;    /*!< [26..24] Selects one of the following
10477                                        clocks for USART1 clk 000 -
10478                                        m4_soc_clk_for_other_clocks 001 - ulp ref
10479                                        Clock(generated inside M4SS based on
10480                                        m4ss_ref_clk_sel from NPSS) 010 - SoC PLL
10481                                        Clock(program bypass_soc_pll_clk if the
10482                                        bypass clock has to be selected) 011 -
10483                                        Modem PLL Clock2(Not Intended for the
10484                                        pragrammer) (program bypass_modem_pll_clk
10485                                        if the bypass clock has to be sele */
10486       __IOM unsigned int Reserved1 : 5;                /*!< [31..27] It is recommended to write
10487                                         these bits to 0.                      */
10488     } CLK_CONFIG_REG1_b;
10489   };
10490 
10491   union {
10492     __IOM unsigned int CLK_CONFIG_REG2; /*!< (@ 0x0000001C) Clock Config Register 1 */
10493 
10494     struct {
10495       __IOM unsigned int USART1_SCLK_SEL : 3;      /*!< [2..0] Selects one of the following clocks
10496                                   for USART1 clk 000
10497                                       - ulp ref Clock(generated inside M4SS
10498                                   based on m4ss_ref_clk_sel from NPSS) 001 - SoC
10499                                   PLL Clock(program bypass_soc_pll_clk if the
10500                                   bypass clock has to be selected) 010 - Modem
10501                                   PLL Clock2(Not Intended for the
10502                                   pragrammer)(program bypass_modem_pll_clk if
10503                                   the bypass clock has to be selected) 011 -
10504                                   Intf PLL
10505                                       Clock(program bypass_intf_pll_clk if the b
10506                                 */
10507       __IOM unsigned int USART1_SCLK_DIV_FAC : 4;  /*!< [6..3] Clock division factor for USART1
10508                                       Clock. If usart1_sclk_enable is 1b0 clock
10509                                       is gated. Else output clock is a swallowed
10510                                           clock. */
10511       __IOM unsigned int USART2_SCLK_SEL : 3;      /*!< [9..7] Selects one of the following clocks
10512                                   for USART2 clk 000
10513                                       - ulp ref Clock(generated inside M4SS
10514                                   based on m4ss_ref_clk_sel from NPSS) 001 - SoC
10515                                   PLL Clock(program bypass_soc_pll_clk if the
10516                                   bypass clock has to be selected) 010 - Modem
10517                                   PLL Clock2(Not Intended for the
10518                                   pragrammer)(program bypass_modem_pll_clk if
10519                                   the bypass clock has to be selected) 011 -
10520                                   Intf PLL
10521                                       Clock(program bypass_intf_pll_clk if the b
10522                                 */
10523       __IOM unsigned int USART2_SCLK_DIV_FAC : 4;  /*!< [13..10] Clock division factor for
10524                                         USART2 Clock. If usart2_sclk_enable   is 1b0
10525                                         clock is gated. Else output clock is a
10526                                         swallowed   clock.   */
10527       __IOM unsigned int Reserved1 : 14;           /*!< [27..14] It is recommended to write
10528                                         these bits to 0.                      */
10529       __IOM unsigned int QSPI_ODD_DIV_SEL : 1;     /*!< [28..28] Clock select for clock swallow or
10530                                    50% even clock divider or 50% odd divider
10531                                    clock for QSPI 1b1 - 50% odd clock divider
10532                                       output is selected with division factor
10533                                    qspi_clk_div_fac 1b0 - 50% even clock divider
10534                                    output or swallowed is selected
10535                                       with division factor qspi_clk_div_fac
10536                                    based on qspi_clk_swallow_sel.      */
10537       __IOM unsigned int USART1_SCLK_FRAC_SEL : 1; /*!< [29..29] Selects the type of divider
10538                                        for uart1_clk 1b0 - Clock Swallow is
10539                                        selected 1b1 - Fractional Divider is
10540                                        selected.                 */
10541       __IOM unsigned int USART2_SCLK_FRAC_SEL : 1; /*!< [30..30] Selects the type of divider
10542                                        for uart2_clk 1b0 - Clock Swallow is
10543                                        selected 1b1 - Fractional Divider is
10544                                        selected.                 */
10545       __IOM unsigned int USART3_SCLK_FRAC_SEL : 1; /*!< [31..31] Selects the type of divider
10546                                        for uart3_clk 1b0 - Clock Swallow is
10547                                        selected 1b1 - Fractional Divider is
10548                                        selected.                 */
10549     } CLK_CONFIG_REG2_b;
10550   };
10551 
10552   union {
10553     __IOM unsigned int CLK_CONFIG_REG3; /*!< (@ 0x00000020) Clock Config Register 3 */
10554 
10555     struct {
10556       __IOM unsigned int Reserved1 : 8;          /*!< [7..0] It is recommended to write these
10557                                        bits to 0.                        */
10558       __IOM unsigned int MCU_CLKOUT_SEL : 4;     /*!< [11..8] Clock Select for the clock
10559                                             on mcu_clkout (Mapped to GPIO) */
10560       __IOM unsigned int MCU_CLKOUT_DIV_FAC : 6; /*!< [17..12] Division factor for
10561                                                 mcu_clkout (Mapped to GPIO) */
10562       __IOM unsigned int MCU_CLKOUT_ENABLE : 1;  /*!< [18..18] Clock Enable for the clock on
10563                                         nwp_clkout (Mapped to     GPIO) 1b0 - Clock is
10564                                         Gated 1b1 - Clock is Enabled     */
10565       __IOM unsigned int Reserved2 : 13;         /*!< [31..19] It is recommended to write
10566                                         these bits to 0.                      */
10567     } CLK_CONFIG_REG3_b;
10568   };
10569 
10570   union {
10571     __IOM unsigned int CLK_CONFIG_REG4; /*!< (@ 0x00000024) Clock Config Register 4 */
10572 
10573     struct {
10574       __IOM unsigned int SOC_PLL_CLK_BYP_SEL : 2;             /*!< [1..0] Selects one of the bypass clocks
10575                                       for SoC PLL Clock                 */
10576       __IOM unsigned int I2S_PLL_CLK_BYP_SEL : 2;             /*!< [3..2] Selects one of the bypass clocks
10577                                       for I2S PLL Clock                 */
10578       __IOM unsigned int MODEM_PLL_CLK_BYP_SEL : 2;           /*!< [5..4] Selects one of the bypass
10579                                         clocks for Modem PLL Clock */
10580       __IOM unsigned int INTF_PLL_CLK_BYP_SEL : 2;            /*!< [7..6] Selects one of the bypass clocks
10581                                        for Intf PLL Clock                */
10582       __IOM unsigned int SOC_INTF_PLL_BYPCLK_CLKCLNR_ON : 1;  /*!< [8..8] Clock cleaner ON
10583                                                  Control for SoC PLL Bypass
10584                                                  Clock          */
10585       __IOM unsigned int SOC_INTF_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [9..9] Clock cleaner OFF
10586                                                   Control for SoC PLL Bypass
10587                                                   Clock        */
10588       __IOM unsigned int Reserved1 : 2;                       /*!< [11..10] It is recommended to write
10589                                        these bits to 0.                      */
10590       __IOM unsigned int I2S_PLL_BYPCLK_CLKCLNR_ON : 1;       /*!< [12..12] Clock cleaner ON Control
10591                                             for I2S PLL Bypass Clock. */
10592       __IOM unsigned int I2S_PLL_BYPCLK_CLKCLNR_OFF : 1;      /*!< [13..13] Clock cleaner
10593                                                         OFF Control for I2S PLL
10594                                                         Bypass Clock. */
10595       __IOM unsigned int MODEM_PLL_BYPCLK_CLKCLNR_ON : 1;     /*!< [14..14] Clock cleaner ON
10596                                               Control for Modem PLL Bypass
10597                                               Clock.        */
10598       __IOM unsigned int MODEM_PLL_BYPCLK_CLKCLNR_OFF : 1;    /*!< [15..15] Clock cleaner OFF
10599                                                Control for Modem PLL Bypass
10600                                                Clock.      */
10601       __IOM unsigned int BYPASS_SOC_PLL_CLK : 1;              /*!< [16..16] Select to choose bypass clock or
10602                                      PLL clock  1b0 - soc_pll_clk 1b1 - One of
10603                                      the bypass clocks based on
10604                                      soc_pll_clk_byp_sel.              */
10605       __IOM unsigned int BYPASS_I2S_PLL_CLK : 1;              /*!< [17..17] Select to choose bypass clock or
10606                                      PLL clock  1b0 - i2s_pll_clk 1b1 - One of
10607                                      the bypass clocks based on
10608                                      soc_pll_clk_byp_sel.              */
10609       __IOM unsigned int BYPASS_MODEM_PLL_CLK1 : 1;           /*!< [18..18] Select to choose bypass clock
10610                                         or PLL clock 1b0 - modem_pll_clk1
10611                                                        1b1 - One of the bypass
10612                                         clocks based on modem_pll_clk_byp_sel.
10613                                       */
10614       __IOM unsigned int BYPASS_MODEM_PLL_CLK2 : 1;           /*!< [19..19] Select to choose bypass clock
10615                                         or PLL clock  1b0 - modem_pll_clk2
10616                                                        1b1 - One of the bypass
10617                                         clocks based on modem_pll_clk_byp_sel.
10618                                       */
10619       __IOM unsigned int BYPASS_INTF_PLL_CLK : 1;             /*!< [20..20] Select to choose bypass clock
10620                                       or PLL clock  1b0 - intf_pll_clk
10621                                                 1b1 - One of the bypass clocks
10622                                       based on soc_pll_clk_byp_sel. */
10623       __IOM unsigned int SLEEP_CLK_SEL : 2;                   /*!< [22..21] Select to choose sleep clk
10624                                            00 - ulp_32khz_rc_clk 01
10625                                                      - ulp_32khz_xtal_clk 10 -
10626                                            Gated 11 - ulp_32khz_ro_clk. */
10627       __IOM unsigned int Reserved2 : 2;                       /*!< [24..23] It is recommended to write
10628                                            these bits to 0.                      */
10629       __IOM unsigned int ULPSS_CLK_DIV_FAC : 6;               /*!< [30..25] Clock division factor for clock
10630                                     to ULPSS. If ulpss_clk_enable is 1b0 clock
10631                                     is gated. Else output clock is a divided
10632                                     clock with the following frequency. 6h0 -
10633                                     Divider is bypassed > 6h0 - clk_out =
10634                                     clk_in/ 2* ulpss_clk_div_fac */
10635       __IOM unsigned int Reserved3 : 1;                       /*!< [31..31] It is recommended to write
10636                                        these bits to 0.                      */
10637     } CLK_CONFIG_REG4_b;
10638   };
10639 
10640   union {
10641     __IOM unsigned int CLK_CONFIG_REG5; /*!< (@ 0x00000028) Clock Config Register 5 */
10642 
10643     struct {
10644       __IOM unsigned int M4_SOC_CLK_SEL : 4;      /*!< [3..0] Selects one of the clock sources for
10645                                  M4 SoC clock. These clocks are selected for
10646                                  m4_soc_clk when 1)m4_soc_host_clk_sel is 1b0 or
10647                                  2)when m4_soc_host_clk_sel is 1b1, xtal is
10648                                  ON(xtal_off from slp_fsm should be zero) and
10649                                  host_clk_available(from host logic) is 1b0.
10650                                  0000 - ULP Ref Clock (generated inside M4SS
10651                                  based on m4ss_ref_clk_sel from NPSS) 0001 -
10652                                  Reserved 0010 - */
10653       __IOM unsigned int M4_SOC_CLK_DIV_FAC : 6;  /*!< [9..4] Clock divison factor for NWP SoC
10654                                      Clock If ta_soc_clk_enable(from NPSS) is
10655                                      1b0 clock is gated. Else output clock is a
10656                                      swallowed clock with the following
10657                                      frequency. 6h0,6h1 - Divider is bypassed
10658                                      >6h1 - clk_out = clk_in/ ta_soc_clk_div_fac
10659                                    */
10660       __IOM unsigned int I2S_CLK_SEL : 1;         /*!< [10..10] Selects one of the following clocks for
10661                               config timer I2S interface 00/11 - I2S PLL Clock
10662                               (program bypass_i2s_pll_clk if the bypass clock
10663                               has to be selected) 01 - I2S PLL Clock_1 (program
10664                               bypass_i2s_pll_clk_1 if the bypass clock has to
10665                                       be selected) 10 -
10666                               m4_soc_clk_for_other_clocks */
10667       __IOM unsigned int I2S_CLK_DIV_FAC : 6;     /*!< [16..11] Clock division factor for i2s_clk.
10668                                   Else output clock is a 50% divided clock with
10669                                   the following frequency. 6h0
10670                                           - Divider is bypassed >6h0 - clk_out =
10671                                   clk_in/ 2*i2s_clk_div_fac          */
10672       __IOM unsigned int CT_CLK_SEL : 3;          /*!< [19..17] Selects one of the following clocks for
10673                              config timer 000 - ulp ref Clock(generated inside
10674                              M4SS based on m4ss_ref_clk_sel from NPSS) 001 -
10675                              Intf PLL Clock(program bypass_intf_pll_clk if the
10676                              bypass clock has to be selected) 010 - SoC PLL
10677                              Clock(program bypass_soc_pll_clk if the bypass
10678                              clock has to be selected) 011 -
10679                              m4_soc_clk_for_other_clocks 100,110 - Invalid */
10680       __IOM unsigned int CT_CLK_DIV_FAC : 6;      /*!< [25..20] Clock division factor for sct_clk.
10681                                  If sct_clk_enable is 1b0 clock is gated. Else
10682                                  output clock is a 50% divided clock with the
10683                                  following frequency. 6h0 - Divider is bypassed
10684                                          >6h0 - clk_out = clk_in/
10685                                  2*sct_clk_div_fac */
10686       __IOM unsigned int M4_SOC_HOST_CLK_SEL : 1; /*!< [26..26] Selects the previous muxed
10687                                        output(xtal_clk) or host_clk  as the clock
10688                                        source for M4 SoC clock based on the
10689                                        following  combinations of {xtal_off(from
10690                                        slp fsm), host_clk_available(from  host
10691                                        logic),m4_soc_host_clk_sel} XX0 - xtal_clk
10692                                        001 - After  wait time based on
10693                                        mask_host_clk_wait_fix ; xtal_clk X11
10694                                            - host_clk 101 - No Clock  */
10695       __IOM unsigned int Reserved1 : 1;           /*!< [27..27] It is recommended to write
10696                                        these bits to 0.                      */
10697       __IOM unsigned int ULPSS_ODD_DIV_SEL : 1;   /*!< [28..28] Selects the type of divider for
10698                                     m4_soc_clk_2ulpss 1b0
10699                                           - Clock Divider(even) is selected 1b1
10700                                     - Odd Divider is selected. */
10701       __IOM unsigned int Reserved2 : 2;           /*!< [30..29] It is recommended to write
10702                                        these bits to 0.                      */
10703       __IOM unsigned int I2S_CLK_SEL_1 : 1;       /*!< [31..31] Selects one of the following clocks
10704                                 for config timer for I2S interface 00/11 - I2S
10705                                 PLL Clock (program bypass_i2s_pll_clk if the
10706                                 bypass clock has to be selected) 01 - I2S PLL
10707                                 Clock_1 (program bypass_i2s_pll_clk_1 if the
10708                                 bypass clock has to be selected) 10 -
10709                                 m4_soc_clk_for_other_clocks */
10710     } CLK_CONFIG_REG5_b;
10711   };
10712   __IM unsigned int RESERVED[6];
10713 
10714   union {
10715     __IOM unsigned int DYN_CLK_GATE_DISABLE_REG; /*!< (@ 0x00000044) Dynamic Clock
10716                                                 Gate Disable Register */
10717 
10718     struct {
10719       __IOM unsigned int SDIO_SYS_HCLK_DYN_CTRL_DISABLE_b : 1;    /*!< [0..0] Dynamic clock gate
10720                                                    disable control sdio sys
10721                                                    clk1'b0 => Dynamic control of
10722                                                    the clock is disbaled 1'b1 =>
10723                                                    Dynamic
10724                                                        control of the clock is
10725                                                    enabled */
10726       __IOM unsigned int BUS_CLK_DYN_CTRL_DISABLE_b : 1;          /*!< [1..1] Dynamic clock gate disable
10727                                              control bus clk1'b0 => Dynamic
10728                                                        control of the clock is
10729                                              disbaled 1'b1 => Dynamic control
10730                                                        of the clock is enabled
10731                                            */
10732       __IOM unsigned int Reserved1 : 2;                           /*!< [3..2] It is recommended to write these
10733                                        bits to 0.                        */
10734       __IOM unsigned int GPDMA_HCLK_DYN_CTRL_DISABLE_b : 1;       /*!< [4..4] Dynamic clock gate
10735                                                 disable control gpdma clk1'b0 =>
10736                                                 Dynamic control of the clock is
10737                                                 disbaled 1'b1 => Dynamic control
10738                                                        of the clock is enabled
10739                                               */
10740       __IOM unsigned int EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1;       /*!< [5..5] Dynamic clock gate
10741                                                 disable control egpio clk1'b0 =>
10742                                                 Dynamic control of the clock is
10743                                                 disbaled 1'b1 => Dynamic control
10744                                                        of the clock is enabled
10745                                               */
10746       __IOM unsigned int SGPIO_PCLK_DYN_CTRL_DISABLE_b : 1;       /*!< [6..6] Dynamic clock gate
10747                                                 disable control sgpio clk1'b0 =>
10748                                                 Dynamic control of the clock is
10749                                                 disbaled 1'b1 => Dynamic control
10750                                                        of the clock is enabled
10751                                               */
10752       __IOM unsigned int TOT_CLK_DYN_CTRL_DISABLE_b : 1;          /*!< [7..7] Dynamic clock gate disable
10753                                              control tot clk1'b0 => Dynamic
10754                                                        control of the clock is
10755                                              disbaled 1'b1 => Dynamic control
10756                                                        of the clock is enabled
10757                                            */
10758       __IOM unsigned int Reserved2 : 1;                           /*!< [8..8] It is recommended to write these
10759                                        bits to 0.                        */
10760       __IOM unsigned int USART1_SCLK_DYN_CTRL_DISABLE_b : 1;      /*!< [9..9] Dynamic clock gate
10761                                                  disable control usart1 sclk1'b0
10762                                                  => Dynamic control of the clock
10763                                                  is disbaled 1'b1 => Dynamic
10764                                                        control of the clock is
10765                                                  enabled. */
10766       __IOM unsigned int USART1_PCLK_DYN_CTRL_DISABLE_b : 1;      /*!< [10..10] Dynamic clock gate
10767                                                  disable control usart1 pclk1'b0
10768                                                        => Dynamic control of the
10769                                                  clock is disbaled 1'b1 =>
10770                                                  Dynamic
10771                                                        control of the clock is
10772                                                  enabled. */
10773       __IOM unsigned int USART2_SCLK_DYN_CTRL_DISABLE_b : 1;      /*!< [11..11] Dynamic clock gate
10774                                                  disable control usart2 sclk1'b0
10775                                                        => Dynamic control of the
10776                                                  clock is disbaled 1'b1 =>
10777                                                  Dynamic
10778                                                        control of the clock is
10779                                                  enabled. */
10780       __IOM unsigned int USART2_PCLK_DYN_CTRL_DISABLE_b : 1;      /*!< [12..12] Dynamic clock gate
10781                                                  disable control usart2 pclk1'b0
10782                                                        => Dynamic control of the
10783                                                  clock is disbaled 1'b1 =>
10784                                                  Dynamic
10785                                                        control of the clock is
10786                                                  enabled. */
10787       __IOM unsigned int Reserved3 : 2;                           /*!< [14..13] It is recommended to write
10788                                        these bits to 0.                      */
10789       __IOM unsigned int SSI_SLV_SCLK_DYN_CTRL_DISABLE_b : 1;     /*!< [15..15] Dynamic clock gate
10790                                                   disable control ssi slave
10791                                                   sclk1'b0
10792                                                        => Dynamic control of the
10793                                                   clock is disbaled 1'b1 =>
10794                                                   Dynamic control of the clock
10795                                                   is enabled */
10796       __IOM unsigned int SSI_SLV_PCLK_DYN_CTRL_DISABLE_b : 1;     /*!< [16..16] Dynamic clock gate
10797                                                   disable control ssi slave
10798                                                   pclk1'b0
10799                                                        => Dynamic control of the
10800                                                   clock is disbaled 1'b1 =>
10801                                                   Dynamic control of the clock
10802                                                   is enabled */
10803       __IOM unsigned int Reserved4 : 2;                           /*!< [18..17] It is recommended to write
10804                                        these bits to 0.                      */
10805       __IOM unsigned int SEMAPHORE_CLK_DYN_CTRL_DISABLE_b : 1;    /*!< [19..19] Dynamic clock gate
10806                                                    disable control semaphore
10807                                                    clk1'b0
10808                                                        => Dynamic control of the
10809                                                    clock is disbaled 1'b1 =>
10810                                                    Dynamic
10811                                                        control of the clock is
10812                                                    enabled. */
10813       __IOM unsigned int ARM_CLK_DYN_CTRL_DISABLE_b : 1;          /*!< [20..20] Dynamic clock gate
10814                                              disable control arm clk1'b0 =>
10815                                              Dynamic control of the clock is
10816                                              disbaled 1'b1 => Dynamic control
10817                                                        of the clock is enabled.
10818                                            */
10819       __IOM unsigned int SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1;     /*!< [21..21] Dynamic clock gate
10820                                                   disable control ssi mst
10821                                                   sclk1'b0
10822                                                        => Dynamic control of the
10823                                                   clock is disbaled 1'b1 =>
10824                                                   Dynamic control of the clock
10825                                                   is enabled. */
10826       __IOM unsigned int Reserved5 : 2;                           /*!< [23..22] It is recommended to write
10827                                        these bits to 0.                      */
10828       __IOM unsigned int MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1;      /*!< [24..24] Dynamic clock gate
10829                                                  disable control mem clk1'b0 =>
10830                                                  Dynamic control of the clock is
10831                                                  disbaled 1'b1 => Dynamic
10832                                                  control of the clock is
10833                                                  enabled. */
10834       __IOM unsigned int Reserved6 : 3;                           /*!< [27..25] It is recommended to write
10835                                        these bits to 0.                      */
10836       __IOM unsigned int SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1;     /*!< [28..28] Dynamic clock gate
10837                                                   disable control ssi mst pclk
10838                                                   1'b0
10839                                                        => Dynamic control of the
10840                                                   clock is disbaled 1'b1 =>
10841                                                   Dynamic control of the clock
10842                                                   is enabled */
10843       __IOM unsigned int ICACHE_DYN_GATING_DISABLE_b : 1;         /*!< [29..29] Dynamic clock gate
10844                                               disable control icache clk1'b0 =>
10845                                                        Dynamic control of the
10846                                               clock is disbaled 1'b1 => Dynamic
10847                                                        control of the clock is
10848                                               enabled */
10849       __IOM unsigned int Reserved7 : 1;                           /*!< [30..30] It is recommended to write
10850                                        these bits to 0.                      */
10851       __IOM unsigned int MISC_CONFIG_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [31..31] Dynamic clock
10852                                                       gate disable control miscn
10853                                                       config pclk 1'b0 =>
10854                                                       Dynamic control of the
10855                                                       clock is disbaled 1'b1 =>
10856                                                        Dynamic control of the
10857                                                       clock is enabled. */
10858     } DYN_CLK_GATE_DISABLE_REG_b;
10859   };
10860   __IM unsigned int RESERVED1[2];
10861 
10862   union {
10863     __IOM unsigned int PLL_ENABLE_SET_REG; /*!< (@ 0x00000050) PLL Enable Set Register */
10864 
10865     struct {
10866       __IOM unsigned int SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 =>
10867                                       soft reset is enabled1'b0
10868                                           => Invalid */
10869       __IOM unsigned int Reserved1 : 31;          /*!< [31..1] It is recommended to write
10870                                         these bits to 0. */
10871     } PLL_ENABLE_SET_REG_b;
10872   };
10873 
10874   union {
10875     __IOM unsigned int PLL_ENABLE_CLEAR_REG; /*!< (@ 0x00000054) PLL Enable Clear Register */
10876 
10877     struct {
10878       __IOM unsigned int SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 =>
10879                                       soft reset is disabled1'b0
10880                                           => Invalid */
10881       __IOM unsigned int Reserved1 : 31;          /*!< [31..1] It is recommended to write
10882                                         these bits to 0. */
10883     } PLL_ENABLE_CLEAR_REG_b;
10884   };
10885 
10886   union {
10887     __IM unsigned int PLL_STAT_REG; /*!< (@ 0x00000058) PLL Status Register */
10888 
10889     struct {
10890       __IM unsigned int LCDPLL_LOCK : 1;                 /*!< [0..0] Lock Signal from LCD PLL  */
10891       __IM unsigned int DDRPLL_LOCK : 1;                 /*!< [1..1] Lock Signal from DDR PLL  */
10892       __IM unsigned int APPLL_LOCK : 1;                  /*!< [2..2] Lock Signal from AP PLL   */
10893       __IM unsigned int INTFPLL_LOCK : 1;                /*!< [3..3] Lock Signal from INTF PLL */
10894       __IM unsigned int I2SPLL_LOCK : 1;                 /*!< [4..4] Lock Signal from I2S PLL  */
10895       __IM unsigned int SOCPLL_LOCK : 1;                 /*!< [5..5] Lock Signal from SoC PLL  */
10896       __IM unsigned int MODEMPLL_LOCK : 1;               /*!< [6..6] Lock Signal from Modem PLL */
10897       __IM unsigned int PLL_LOCK_DATA_TRIG : 1;          /*!< [7..7] This is set to 1'b1 when the PLL
10898                                      Locks are equal to pll_lock_int_data_r
10899                                                        g */
10900       __IM unsigned int M4_SOC_CLK_SWITCHED : 1;         /*!< [8..8] Indication from M4 SoC
10901                                                 Clock Dynamic mux that the
10902                                                 switching happened */
10903       __IM unsigned int QSPI_CLK_SWITCHED : 1;           /*!< [9..9] Indication from QSPI Clock Dynamic
10904                                     mux that the switching happened */
10905       __IM unsigned int USART1_SCLK_SWITCHED : 1;        /*!< [10..10] Indication from
10906                                                  USART1 Clock Dynamic mux that
10907                                                  the switching happened */
10908       __IM unsigned int USART2_SCLK_SWITCHED : 1;        /*!< [11..11] Indication from
10909                                                  USART1 Clock Dynamic mux that
10910                                                  the switching happened */
10911       __IM unsigned int GEN_SPI_MST1_SCLK_SWITCHED : 1;  /*!< [12..12] Indication from USART2
10912                                              Clock Dynamic mux that the
10913                                              switching happened */
10914       __IM unsigned int SSI_MST_SCLK_SWITCHED : 1;       /*!< [13..13] Indication from SSi
10915                                                   Master SClock Dynamic mux that
10916                                                      the switching happened */
10917       __IM unsigned int Reserved1 : 1;                   /*!< [14..14] It is recommended to write
10918                                       these bits to 0.                      */
10919       __IM unsigned int CT_CLK_SWITCHED : 1;             /*!< [15..15] Indication from SCT Clock Dynamic
10920                                   mux that the switching happened */
10921       __IM unsigned int M4_TA_SOC_CLK_SWITCHED_SDIO : 1; /*!< [16..16] Indication
10922                                                         from M4-NWP Soc SDIO
10923                                                         Clock Dynamic mux that
10924                                                            the switching
10925                                                         happened(TBD) */
10926       __IM unsigned int I2S_CLK_SWITCHED : 1;            /*!< [17..17] Indication from I2S Clock Dynamic
10927                                    mux that the switching happened */
10928       __IM unsigned int PLL_INTF_CLK_SWITCHED : 1;       /*!< [18..18] Indication from Pll
10929                                                   Intf Clock Dynamic mux that
10930                                                   the switching happened */
10931       __IM unsigned int Reserved2 : 2;                   /*!< [20..19] It is recommended to write
10932                                       these bits to 0.                      */
10933       __IM unsigned int SLEEP_CLK_SWITCHED : 1;          /*!< [21..21] Indication from Sleep
10934                                                 clcok Dynamic mux that the
10935                                                 switching  happened  */
10936       __IM unsigned int MCU_CLKOUT_SWITCHED : 1;         /*!< [22..22] Indication from
10937                                                 mcu_clkout Dynamic mux that the
10938                                                 switching happened */
10939       __IM unsigned int QSPI_2_CLK_SWITCHED : 1;         /*!< [23..23] Indication from QSPI
10940                                                 Clock Dynamic mux that the
10941                                                 switching happened */
10942       __IM unsigned int TASS_M4SS_64K_CLK_SWITCHED : 1;  /*!< [24..24] Indication when NWP
10943                                                 accessing 2nd memory chunk of M4,
10944                                                 clock to Dynamic mux switching
10945                                                 happened      */
10946       __IM unsigned int CC_CLOCK_MUX_SWITCHED : 1;       /*!< [25..25] Indication from cc
10947                                                   clock Dynamic mux that the
10948                                                   switching happened */
10949       __IM unsigned int TASS_M4SS_192K_CLK_SWITCHED : 1; /*!< [26..26] Indication when NWP
10950                                              accessing 0th memory chunk of M4,
10951                                              clock to Dynamic mux switching
10952                                              happened   */
10953       __IM unsigned int USART1_CLK_SWITCHED : 1;         /*!< [27..27] Indication from
10954                                              usart1 sclk or pclk Dynamic mux
10955                                              that the switching happened */
10956       __IM unsigned int USART2_CLK_SWITCHED : 1;         /*!< [28..28] Indication from
10957                                              usart2 sclk or pclk Dynamic mux
10958                                              that the switching happened */
10959       __IM unsigned int TASS_M4SS_64K0_CLK_SWITCHED : 1; /*!< [29..29] Indication when NWP
10960                                            accessing 1st memory chunk of M4,
10961                                            clock to Dynamic mux switching
10962                                            happened */
10963       __IM unsigned int CLK_FREE_OR_SLP_SWITCHED : 1;    /*!< [30..30] Indication from
10964                                               clk_free_or_slp Dynamic mux that the
10965                                               switching happened       */
10966       __IM unsigned int ULP_REF_CLK_SWITCHED : 1;        /*!< [31..31] Indication from
10967                                                  ulp_ref_clk Dynamic mux that
10968                                                  the switching happened */
10969     } PLL_STAT_REG_b;
10970   };
10971 
10972   union {
10973     __IOM unsigned int PLL_LOCK_INT_MASK_REG; /*!< (@ 0x0000005C) PLL Lock Interrupt
10974                                              Mask Register */
10975 
10976     struct {
10977       __IOM unsigned int LCD_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;           /*!< [0..0] 1'b1 =>
10978                                                        Masked;1'b0 => Not Masked
10979                                                      */
10980       __IOM unsigned int DDR_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;           /*!< [1..1] 1'b1 =>
10981                                                        Masked;1'b0 => Not Masked
10982                                                      */
10983       __IOM unsigned int AP_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;            /*!< [2..2] 1'b1 =>
10984                                                       Masked;1'b0 => Not Masked
10985                                                     */
10986       __IOM unsigned int INTF_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;          /*!< [3..3] 1'b1 =>
10987                                                         Masked;1'b0 => Not
10988                                                         Masked */
10989       __IOM unsigned int I2S_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;           /*!< [4..4] 1'b1 =>
10990                                                        Masked;1'b0 => Not Masked
10991                                                      */
10992       __IOM unsigned int SOC_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;           /*!< [5..5] 1'b1 =>
10993                                                        Masked;1'b0 => Not Masked
10994                                                      */
10995       __IOM unsigned int MODEM_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1;         /*!< [6..6] 1'b1 =>
10996                                                          Masked;1'b0 => Not
10997                                                          Masked */
10998       __IOM unsigned int PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_RISING_EDGE : 1;  /*!< [7..7] 1'b1 =>
10999                                                                 Masked;1'b0 =>
11000                                                                 Not Masked */
11001       __IOM unsigned int LCD_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;          /*!< [8..8] 1'b1 =>
11002                                                         Masked;1'b0 => Not
11003                                                         Masked */
11004       __IOM unsigned int DDR_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;          /*!< [9..9] 1'b1 =>
11005                                                         Masked;1'b0 => Not
11006                                                         Masked */
11007       __IOM unsigned int AP_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;           /*!< [10..10] 1'b1 =>
11008                                                        Masked;1'b0 => Not Masked
11009                                                      */
11010       __IOM unsigned int INTF_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;         /*!< [11..11] 1'b1 =>
11011                                                          Masked;1'b0 => Not
11012                                                          Masked */
11013       __IOM unsigned int I2S_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;          /*!< [12..12] 1'b1 =>
11014                                                         Masked;1'b0 => Not
11015                                                         Masked */
11016       __IOM unsigned int SOC_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;          /*!< [13..13] 1'b1 =>
11017                                                         Masked;1'b0 => Not
11018                                                         Masked */
11019       __IOM unsigned int MODEM_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1;        /*!< [14..14] 1'b1 =>
11020                                                           Masked;1'b0 => Not
11021                                                           Masked */
11022       __IOM unsigned int PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b1
11023                                                                  => Masked;1'b0
11024                                                                  => Not Masked
11025                                                                */
11026       __IOM unsigned int Reserved1 : 16;                                     /*!< [31..16] It is recommended to write
11027                                         these bits to 0.                      */
11028     } PLL_LOCK_INT_MASK_REG_b;
11029   };
11030 
11031   union {
11032     __IOM unsigned int PLL_LOCK_INT_CLR_REG; /*!< (@ 0x00000060) PLL Lock Interrupt
11033                                             Clear Register */
11034 
11035     struct {
11036       __IOM unsigned int LCD_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;           /*!< [0..0] 1'b0 => Not
11037                                                         Cleared 1'b1 => Cleared
11038                                                       */
11039       __IOM unsigned int DDR_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;           /*!< [1..1] 1'b0 => Not
11040                                                         Cleared 1'b1 => Cleared
11041                                                       */
11042       __IOM unsigned int AP_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;            /*!< [2..2] 1'b0 => Not
11043                                                        Cleared 1'b1 => Cleared
11044                                                      */
11045       __IOM unsigned int INTF_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;          /*!< [3..3] 1'b0 => Not
11046                                                          Cleared 1'b1 => Cleared
11047                                                        */
11048       __IOM unsigned int I2S_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;           /*!< [4..4] 1'b0 => Not
11049                                                         Cleared 1'b1 => Cleared
11050                                                       */
11051       __IOM unsigned int SOC_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;           /*!< [5..5] 1'b0 => Not
11052                                                         Cleared 1'b1 => Cleared
11053                                                       */
11054       __IOM unsigned int MODEM_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1;         /*!< [6..6] 1'b0 => Not
11055                                                           Cleared 1'b1 =>
11056                                                           Cleared */
11057       __IOM unsigned int PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_RISING_EDGE : 1;  /*!< [7..7] 1'b0
11058                                                                  => Not Cleared
11059                                                                  1'b1 => Cleared
11060                                                                */
11061       __IOM unsigned int LCD_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;          /*!< [8..8] 1'b0 => Not
11062                                                          Cleared 1'b1 => Cleared
11063                                                        */
11064       __IOM unsigned int DDR_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;          /*!< [9..9] 1'b0 => Not
11065                                                          Cleared 1'b1 => Cleared
11066                                                        */
11067       __IOM unsigned int AP_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;           /*!< [10..10] 1'b0 => Not
11068                                                         Cleared 1'b1 => Cleared
11069                                                       */
11070       __IOM unsigned int INTF_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;         /*!< [11..11] 1'b0 => Not
11071                                                           Cleared 1'b1 =>
11072                                                           Cleared             */
11073       __IOM unsigned int I2S_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;          /*!< [12..12] 1'b0 => Not
11074                                                          Cleared 1'b1 => Cleared
11075                                                        */
11076       __IOM unsigned int SOC_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;          /*!< [13..13] 1'b0 => Not
11077                                                          Cleared 1'b1 => Cleared
11078                                                        */
11079       __IOM unsigned int MODEM_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1;        /*!< [14..14] 1'b0 =>
11080                                                            Not Cleared 1'b1 =>
11081                                                            Cleared            */
11082       __IOM unsigned int PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!<
11083                                                                              [15..15]
11084                                                                              1'b0
11085                                                                              =>
11086                                                                              Not
11087                                                                              Cleared
11088                                                                              1'b1
11089                                                                              =>
11090                                                                              Cleared
11091                                                                            */
11092       __IOM unsigned int Reserved1 : 16;                                      /*!< [31..16] It is recommended to write
11093                                         these bits to 0.                      */
11094     } PLL_LOCK_INT_CLR_REG_b;
11095   };
11096 
11097   union {
11098     __IOM unsigned int PLL_LOCK_INT_DATA_REG; /*!< (@ 0x00000064) PLL Lock Interrupt
11099                                              DATA Register */
11100 
11101     struct {
11102       __IOM unsigned int LCD_PLL_LOCK : 1;   /*!< [0..0] 1'b1 => LCD PLL Lock has to be used as
11103                                trigger1'b0 => LCD PLL Lock not to be used as
11104                                trigger                                    */
11105       __IOM unsigned int DDR_PLL_LOCK : 1;   /*!< [1..1] 1'b1 => DDR PLL Lock has to be used as
11106                                trigger1'b0 => DDR PLL Lock not to be used as
11107                                trigger                                    */
11108       __IOM unsigned int AP_PLL_LOCK : 1;    /*!< [2..2] 1'b1 => AP PLL Lock has to be used as
11109                               trigger1'b0 => Ap PLL Lock not to be used as
11110                               trigger                                     */
11111       __IOM unsigned int INTF_PLL_LOCK : 1;  /*!< [3..3] 1'b1 => INTF PLL Lock has to
11112                                            be used as trigger1'b0 => INTF PLL
11113                                            Lock not to be used as trigger */
11114       __IOM unsigned int I2S_PLL_LOCK : 1;   /*!< [4..4] 1'b1 => I2S PLL Lock has to be used as
11115                                trigger1'b0 => I2S PLL Lock not to be used as
11116                                trigger                                    */
11117       __IOM unsigned int SOC_PLL_LOCK : 1;   /*!< [5..5] 1'b1 => SoC PLL Lock has to be used as
11118                                trigger1'b0 => SoC PLL Lock not to be used as
11119                                trigger                                    */
11120       __IOM unsigned int MODEM_PLL_LOCK : 1; /*!< [6..6] 1'b1 => Modem PLL Lock has
11121                                             to be used as trigger1'b0
11122                                                      => Modem PLL Lock not to be
11123                                             used as trigger */
11124       __IOM unsigned int Reserved1 : 25;     /*!< [31..7] It is recommended to write
11125                                             these bits to 0.     */
11126     } PLL_LOCK_INT_DATA_REG_b;
11127   };
11128 
11129   union {
11130     __IOM unsigned int SLEEP_CALIB_REG; /*!< (@ 0x00000068) Sleep Calib Register */
11131 
11132     struct {
11133       __IOM unsigned int SLP_CALIB_START_b : 1;     /*!< [0..0] This bit is used to start the
11134                                     calibration. 1b1 - Start calibration.
11135                                     slp_calib_duration should be loaded before
11136                                       this bit is set. This bit is
11137                                     self-clearing. When read,
11138                                       if high indicates the completion of
11139                                     calibration process.                  */
11140       __IOM unsigned int SLP_CALIB_CYCLES : 2;      /*!< [2..1] These bits are used to program the
11141                                    number of clock cycles over which clock
11142                                    calibration is to be done. */
11143       __IOM unsigned int SLP_CALIB_DURATION_b : 16; /*!< [18..3] Duration of the sleep clock in
11144                                         terms of processor clocks. This has to
11145                                         be divided with number of calibration
11146                                         cycles to get number of clock
11147                                         cycles(reference clock) in single clock
11148                                         period). 1b1 - AP PLL Lock has to be
11149                                         used as trigger1b0
11150                                           - Ap PLL Lock not to be used as
11151                                         trigger */
11152       __IOM unsigned int SLP_CALIB_DONE_b : 1;      /*!< [19..19] Indicates the end of
11153                                               calibration */
11154       __IOM unsigned int Reserved1 : 12;            /*!< [31..20] It is recommended to write
11155                                         these bits to 0.                      */
11156     } SLEEP_CALIB_REG_b;
11157   };
11158 
11159   union {
11160     __IOM unsigned int CLK_CALIB_CTRL_REG1; /*!< (@ 0x0000006C) Clock Calib Control
11161                                            Register1 */
11162 
11163     struct {
11164       __IOM unsigned int CC_SOFT_RST_b : 1;        /*!< [0..0] Soft Reset for clock
11165                                            calibrator 1b1 - reset enabled 1b0
11166                                                      - reset disabled. */
11167       __IOM unsigned int CC_START_b : 1;           /*!< [1..1] start clk calibration 1b1 - start */
11168       __IOM unsigned int CC_CHANGE_TEST_CLK_b : 1; /*!< [2..2] change test clk. Set
11169                                                   this bit to 1'b1 only when
11170                                                   test_clk is being changed,
11171                                                   else this should be 1'b0. */
11172       __IOM unsigned int CC_CLKIN_SEL_b : 4;       /*!< [6..3] select the clock to be calibrated 4d0
11173                                  - ulp_ref_clk 4d1
11174                                     - mems_ref_clk 4d2 - ulp_20mhz_ringosc_clk
11175                                  4d3 - modem_pll_clk1 4d4 - modem_pll_clk2 4d5 -
11176                                  intf_pll_clk 4d6 - soc_pll_clk 4d7 -
11177                                  i2s_pll_clk 4d8 - sleep_clk 4d9 - bus_clkby2_ap
11178                                */
11179       __IOM unsigned int Reserved1 : 25;           /*!< [31..7] It is recommended to write
11180                                         these bits to 0. */
11181     } CLK_CALIB_CTRL_REG1_b;
11182   };
11183 
11184   union {
11185     __IOM unsigned int CLK_CALIB_CTRL_REG2; /*!< (@ 0x00000070) Clock Calib Control
11186                                            Register2 */
11187 
11188     struct {
11189       __IOM unsigned int CC_NUM_REF_CLKS : 32; /*!< [31..0] number of ref_clk cycles to be
11190                                    considered for calibrating.        */
11191     } CLK_CALIB_CTRL_REG2_b;
11192   };
11193 
11194   union {
11195     __IOM unsigned int CLK_CALIB_STS_REG1; /*!< (@ 0x00000074) Clock Calib Status
11196                                           Register1 */
11197 
11198     struct {
11199       __IOM unsigned int CC_DONE_b : 1;  /*!< [0..0] indicates clock calibratioon
11200                                         done1'b1 => done1'b0 =>  none  */
11201       __IOM unsigned int CC_ERROR_b : 1; /*!< [1..1] indicates clock calibration
11202                                         error1'b1 => error1'b0 => none */
11203       __IOM unsigned int Reserved1 : 30; /*!< [31..2] It is recommended to write
11204                                         these bits to 0. */
11205     } CLK_CALIB_STS_REG1_b;
11206   };
11207 
11208   union {
11209     __IOM unsigned int CLK_CALIB_STS_REG2; /*!< (@ 0x00000078) Clock Calib Status
11210                                           Register2 */
11211 
11212     struct {
11213       __IOM unsigned int CC_NUM_TEST_CLKS : 32; /*!< [31..0] number of test clk cycles occurred
11214                                     for the specified number of ref_clk cycles
11215                                   */
11216     } CLK_CALIB_STS_REG2_b;
11217   };
11218 
11219   union {
11220     __IOM unsigned int CLK_CONFIG_REG6; /*!< (@ 0x0000007C) Clock Config Register6 */
11221 
11222     struct {
11223       __IOM unsigned int IID_KH_CLK_DIV_FAC : 3;     /*!< [2..0] Clock division factor
11224                                                 for iid_clk. */
11225       __IOM unsigned int Reserved1 : 2;              /*!< [4..3] It is recommended to write these
11226                                        bits to 0.                        */
11227       __IOM unsigned int PADCFG_PCLK_DIV_FAC : 4;    /*!< [8..5] Clock division factor
11228                                                  for pclk_pad_config_m4ss */
11229       __IOM unsigned int QSPI_2_CLK_SEL : 3;         /*!< [11..9] Selects one of the following clocks
11230                                  for ssi master 000
11231                                   - ULP Ref Clock(generated inside M4SS based on
11232                                  m4ss_ref_clk_sel from NPSS) 001 - Intf PLL
11233                                  Clock Clock (program bypass_intf_pll_clk if the
11234                                  bypass clock has to be selected) 010 - Modem
11235                                  PLL Clock2(Not Intended for the programmer)
11236                                  (program bypass_modem_pll_clk if the bypass
11237                                  clock has to be selected) 011 - SoC PLL Clock
11238                                */
11239       __IOM unsigned int QSPI_2_CLK_DIV_FAC : 6;     /*!< [17..12] Clock divison factor for QSPI.
11240                                      If qspi_clk_enable is 1b0 clock is gated.
11241                                      Else 1)when qspi_clk_swallow_sel is 1b1 and
11242                                      qspi_odd_div_sel is 1b0 output clock is a
11243                                      swallowed clock with the following
11244                                      frequency. 6h0,6h1 => clk_out = clk_in >6h1
11245                                      => clk_out = clk_in/ qspi_clk_div_fac
11246                                      2)when qspi_clk_swallow_sel is 1b0 */
11247       __IOM unsigned int QSPI_2_CLK_SWALLOW_SEL : 1; /*!< [18..18] Clock select for clock
11248                                          swallow or clock divider for QSPI 1b0
11249                                          => 50% divider is selected with
11250                                          division factor qspi_clk_div_fac 1b1 =>
11251                                          Swallowed clock is selected with
11252                                          division factor qspi_clk_div_fac Before
11253                                          Changing this ensure that the input
11254                                           clocks are gated */
11255       __IOM unsigned int QSPI_2_ODD_DIV_SEL : 1;     /*!< [19..19] Clock select for clock swallow
11256                                      or 50% even clock divider or 50% odd
11257                                      divider clock for QSPI 1b1 - 50% odd clock
11258                                      divider output is selected with division
11259                                      factor qspi_clk_div_fac 1b0 - 50% even
11260                                      clock divider output or swallowed is
11261                                      selected with division factor
11262                                      qspi_clk_div_fac based on
11263                                      qspi_clk_swallow_sel.      */
11264       __IOM unsigned int Reserved2 : 12;             /*!< [31..20] It is recommended to write
11265                                         these bits to 0. */
11266     } CLK_CONFIG_REG6_b;
11267   };
11268 
11269   union {
11270     __IOM unsigned int DYN_CLK_GATE_DISABLE_REG2; /*!< (@ 0x00000080) Dynamic Clock
11271                                                  Gate Disable Register2 */
11272 
11273     struct {
11274       __IOM unsigned int SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate
11275                                                      disable control soc pll spi
11276                                                      clk  1b1
11277                                                        - Dynamic control of the
11278                                                      clock is disbaled  1b0 -
11279                                                      Dynamic control of the
11280                                                      clock is enabled */
11281       __IOM unsigned int Reserved1 : 2;                          /*!< [2..1] It is recommended to write these
11282                                        bits to 0.                        */
11283       __IOM unsigned int CT_PCLK_DYN_CTRL_DISABLE_b : 1;         /*!< [3..3] Dynamic clock gate disable
11284                                              control SCT pclk  1b1 - Dynamic
11285                                                        control of the clock is
11286                                              disbaled  1b0 - Dynamic control
11287                                                        of the clock is enabled
11288                                            */
11289       __IOM unsigned int Reserved2 : 2;                          /*!< [5..4] It is recommended to write these
11290                                        bits to 0.                        */
11291       __IOM unsigned int EFUSE_CLK_DYN_CTRL_DISABLE_b : 1;       /*!< [6..6] Dynamic clock gate
11292                                                disable control efuse clk  1b1 -
11293                                                Dynamic control of the clock is
11294                                                disbaled  1b0 - Dynamic control
11295                                                        of the clock is enabled
11296                                              */
11297       __IOM unsigned int EFUSE_PCLK_DYN_CTRL_DISABLE_b : 1;      /*!< [7..7] Dynamic clock gate
11298                                                 disable control efuse pclk  1b1
11299                                                 - Dynamic control of the clock
11300                                                 is disbaled  1b0 - Dynamic
11301                                                        control of the clock is
11302                                                 enabled */
11303       __IOM unsigned int Reserved3 : 24;                         /*!< [31..8] It is recommended to write
11304                                         these bits to 0. */
11305     } DYN_CLK_GATE_DISABLE_REG2_b;
11306   };
11307 
11308   union {
11309     __IOM unsigned int PLL_LOCK_INT_STATUS_REG; /*!< (@ 0x00000084) PLL Lock
11310                                                Interrupt Status Register */
11311 
11312     struct {
11313       __IOM unsigned int LCD_PLL_LOCK_OF_RISING_EDGE : 1;                /*!< [0..0] 1b0 - No Interrupt; 1b1 -
11314                                               Interrupt encountered. */
11315       __IOM unsigned int DDR_PLL_LOCK_OF_RISING_EDGE : 1;                /*!< [1..1] 1'b0 => No Interrupt;1'b1
11316                                               => Interrupt encountered. */
11317       __IOM unsigned int AP_PLL_LOCK_OF_RISING_EDGE : 1;                 /*!< [2..2] 1'b0 => No Interrupt;1'b1
11318                                              => Interrupt encountered. */
11319       __IOM unsigned int INTF_PLL_LOCK_OF_RISING_EDGE : 1;               /*!< [3..3] 1'b0 => No
11320                                                Interrupt;1'b1 => Interrupt
11321                                                encountered.          */
11322       __IOM unsigned int I2S_PLL_LOCK_OF_RISING_EDGE : 1;                /*!< [4..4] 1'b0 => No Interrupt;1'b1
11323                                               => Interrupt encountered. */
11324       __IOM unsigned int SOC_PLL_LOCK_OF_RISING_EDGE : 1;                /*!< [5..5] 1'b0 => No Interrupt;1'b1
11325                                               => Interrupt encountered. */
11326       __IOM unsigned int MODEM_PLL_LOCK_OF_RISING_EDGE : 1;              /*!< [6..6] 1'b0 => No
11327                                                 Interrupt;1'b1 => Interrupt
11328                                                 encountered.         */
11329       __IOM unsigned int PLL_LOCK_DATA_TRIGGER_INTR_OF_RISING_EDGE : 1;  /*!< [7..7] 1'b0 => No
11330                                                             Interrupt;1'b1 =>
11331                                                             Interrupt
11332                                                             encountered. */
11333       __IOM unsigned int LCD_PLL_LOCK_OF_FALLING_EDGE : 1;               /*!< [8..8] 1'b0 => No
11334                                                Interrupt;1'b1 => Interrupt
11335                                                encountered.          */
11336       __IOM unsigned int DDR_PLL_LOCK_OF_FALLING_EDGE : 1;               /*!< [9..9] 1'b0 => No
11337                                                Interrupt;1'b1 => Interrupt
11338                                                encountered.          */
11339       __IOM unsigned int AP_PLL_LOCK_OF_FALLING_EDGE : 1;                /*!< [10..10] 1'b0 => No
11340                                               Interrupt;1'b1 => Interrupt
11341                                               encountered.         */
11342       __IOM unsigned int INTF_PLL_LOCK_OF_FALLING_EDGE : 1;              /*!< [11..11] 1'b0 => No
11343                                                 Interrupt;1'b1 => Interrupt
11344                                                 encountered.       */
11345       __IOM unsigned int I2S_PLL_LOCK_OF_FALLING_EDGE : 1;               /*!< [12..12] 1'b0 => No
11346                                                Interrupt;1'b1 => Interrupt
11347                                                encountered.        */
11348       __IOM unsigned int SOC_PLL_LOCK_OF_FALLING_EDGE : 1;               /*!< [13..13] 1'b0 => No
11349                                                Interrupt;1'b1 => Interrupt
11350                                                encountered.        */
11351       __IOM unsigned int MODEM_PLL_LOCK_OF_FALLING_EDGE : 1;             /*!< [14..14] 1'b0 => No
11352                                                  Interrupt;1'b1 => Interrupt
11353                                                  encountered.      */
11354       __IOM unsigned int PLL_LOCK_DATA_TRIGGER_INTR_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b0 =>
11355                                                              No Interrupt;1'b1
11356                                                              => Interrupt
11357                                                              encountered. */
11358       __IOM unsigned int Reserved1 : 16;                                 /*!< [31..16] It is recommended to write
11359                                         these bits to 0.                      */
11360     } PLL_LOCK_INT_STATUS_REG_b;
11361   };
11362 } M4CLK_Type; /*!< Size = 136 (0x88) */
11363 
11364 /* ===========================================================================================================================
11365  */
11366 /* ================                                        TIME_PERIOD
11367  * ================ */
11368 /* ===========================================================================================================================
11369  */
11370 
11371 /**
11372  * @brief In this the time periods of 32KHz RC clock, 32KHz RO clock and 32KHz
11373  * XTAL clock can be calibrated (TIME_PERIOD)
11374  */
11375 
11376 typedef struct { /*!< (@ 0x24048200) TIME_PERIOD Structure */
11377 
11378   union {
11379     __IOM unsigned int MCU_CAL_RO_TIMEPERIOD_READ; /*!< (@ 0x00000000) RO timeperiod
11380                                                   read register */
11381 
11382     struct {
11383       __IM unsigned int TIMEPERIOD_RO : 25; /*!< [24..0] Calibrated RO timeperiod      */
11384       __IM unsigned int RESERVED1 : 7;      /*!< [31..25] reser */
11385     } MCU_CAL_RO_TIMEPERIOD_READ_b;
11386   };
11387 
11388   union {
11389     __IOM unsigned int MCU_CAL_TIMER_CLOCK_PERIOD; /*!< (@ 0x00000004) MCU calender timer clock
11390                                        period register                   */
11391 
11392     struct {
11393       __IOM unsigned int RTC_TIMER_CLK_PERIOD : 25;             /*!< [24..0] RTC timer clock
11394                                                    period programmed by SOC */
11395       __IM unsigned int RESERVED1 : 6;                          /*!< [30..25] reser              */
11396       __IM unsigned int SPI_RTC_TIMER_CLK_PERIOD_APPLIED_b : 1; /*!< [31..31] Indicated SOC
11397                                                      programmed rtc_timer clock
11398                                                      period is applied at KHz
11399                                                      clock domain */
11400     } MCU_CAL_TIMER_CLOCK_PERIOD_b;
11401   };
11402 
11403   union {
11404     __IOM unsigned int MCU_CAL_TEMP_PROG_REG; /*!< (@ 0x00000008) temprature program
11405                                              register */
11406 
11407     struct {
11408       __IOM unsigned int BYPASS_CALIB_PG : 1;          /*!< [0..0] To bypass power gating and
11409                                              keep all the blocks always on */
11410       __IM unsigned int RESERVED1 : 15;                /*!< [15..1] reser       */
11411       __IOM unsigned int MAX_TEMP_CHANGE : 5;          /*!< [20..16] maximum temperature change after
11412                                   which rc calibration must be trigger */
11413       __IOM unsigned int TEMP_TRIGGER_TIME_SEL : 2;    /*!< [22..21] temperature
11414                                                       trigger time select    */
11415       __IOM unsigned int PERIODIC_TEMP_CALIB_EN : 1;   /*!< [23..23] Enable periodic
11416                                                       checking of temperature   */
11417       __IOM unsigned int RTC_TIMER_PERIOD_MUX_SEL : 1; /*!< [24..24] rtc timer
11418                                                       period mux select */
11419       __IM unsigned int RESERVED2 : 7;                 /*!< [31..25] reser                 */
11420     } MCU_CAL_TEMP_PROG_REG_b;
11421   };
11422 
11423   union {
11424     __IOM unsigned int MCU_CAL_START_REG; /*!< (@ 0x0000000C) mcu cal start register */
11425 
11426     struct {
11427       __IOM unsigned int ALPHA_RO : 3;               /*!< [2..0] alpha = 1/2^alpha_ro , averaging factor of
11428                            RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev
11429                          */
11430       __IOM unsigned int ALPHA_RC : 3;               /*!< [5..3] alpha = 1/2^alpha_rc , averaging factor of
11431                            RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev
11432                          */
11433       __IOM unsigned int NO_OF_RO_CLKS : 4;          /*!< [9..6] 2^no_of_ro_clks no of clocks
11434                                            of ro clock counts for no of rc
11435                                            clocks in that time to measure
11436                                            timeperiod */
11437       __IOM unsigned int NO_OF_RC_CLKS : 3;          /*!< [12..10] 2^no_of_rc_clocks = no of
11438                                            rc clocks used in calibration */
11439       __IOM unsigned int RC_SETTLE_TIME : 3;         /*!< [15..13] no of clocks of RO for the RC clk to
11440                                  settle when enabled         */
11441       __IOM unsigned int RO_TRIGGER_TIME_SEL : 2;    /*!< [17..16] ro trigger time select */
11442       __IOM unsigned int RC_TRIGGER_TIME_SEL : 3;    /*!< [20..18] rc trigger time select */
11443       __IOM unsigned int PERIODIC_RO_CALIB_EN : 1;   /*!< [21..21] periodically calibrate RO
11444                                        timeperiod based ro trigger time sel */
11445       __IOM unsigned int PERIODIC_RC_CALIB_EN : 1;   /*!< [22..22] periodically calibrate RC
11446                                        timeperiod based rc trigger time sel */
11447       __OM unsigned int START_CALIB_RO : 1;          /*!< [23..23] to initiate RO calibration */
11448       __OM unsigned int START_CALIB_RC : 1;          /*!< [24..24] to initiate RC calibration */
11449       __IOM unsigned int RC_XTAL_MUX_SEL : 1;        /*!< [25..25] xtal mux select */
11450       __IOM unsigned int LOW_POWER_TRIGGER_SEL : 1;  /*!< [26..26] power trigger select */
11451       __IOM unsigned int VBATT_TRIGGER_TIME_SEL : 3; /*!< [29..27] trigger to ipmu block for
11452                                          checking vbatt status periodicaly */
11453       __IM unsigned int RESERVED1 : 2;               /*!< [31..30] reser    */
11454     } MCU_CAL_START_REG_b;
11455   };
11456 
11457   union {
11458     __IOM unsigned int MCU_CAL_REF_CLK_SETTLE_REG; /*!< (@ 0x00000010) reference
11459                                                   clock settle register */
11460 
11461     struct {
11462       __IOM unsigned int XTAL_SETTLE : 7;        /*!< [6..0] no of 32khz clocks for xtal
11463                                          40mhz clk to settle */
11464       __IM unsigned int RESERVED1 : 9;           /*!< [15..7] reser    */
11465       __IM unsigned int VALID_RC_TIMEPERIOD : 1; /*!< [16..16] Valid signal for reading RC
11466                                       timeperiod calibrated                */
11467       __IM unsigned int VALID_RO_TIMEPERIOD : 1; /*!< [17..17] Valid signal for
11468                                                 reading RO timeperiod */
11469       __IM unsigned int RESERVED2 : 14;          /*!< [31..18] reser          */
11470     } MCU_CAL_REF_CLK_SETTLE_REG_b;
11471   };
11472 
11473   union {
11474     __IOM unsigned int MCU_CAL_RC_TIMEPERIOD_READ; /*!< (@ 0x00000014) rc timeperiod
11475                                                   read register */
11476 
11477     struct {
11478       __IM unsigned int TIMEPERIOD_RC : 25; /*!< [24..0] Calibrated RC timeperiod      */
11479       __IM unsigned int RESERVED1 : 7;      /*!< [31..25] reser */
11480     } MCU_CAL_RC_TIMEPERIOD_READ_b;
11481   };
11482 
11483   union {
11484     __IOM unsigned int MCU_CAL_REF_CLK_TIEMPERIOD_REG; /*!< (@ 0x00000018) reference clock
11485                                            timeperiod register */
11486 
11487     struct {
11488       __IOM unsigned int TIMEPERIOD_REF_CLK : 24; /*!< [23..0] timeperiod of reference clk with
11489                                       each bit corresponding to granularity of
11490                                       2^27 = 1us */
11491       __IM unsigned int RESERVED1 : 8;            /*!< [31..24] reser */
11492     } MCU_CAL_REF_CLK_TIEMPERIOD_REG_b;
11493   };
11494 } TIME_PERIOD_Type; /*!< Size = 28 (0x1c) */
11495 
11496 /* ===========================================================================================================================
11497  */
11498 /* ================                                          MCU_WDT
11499  * ================ */
11500 /* ===========================================================================================================================
11501  */
11502 
11503 /**
11504  * @brief A dedicated window watch dog timer for MCU applications (MCU_WDT)
11505  */
11506 
11507 typedef struct { /*!< (@ 0x24048300) MCU_WDT Structure */
11508 
11509   union {
11510     __IOM unsigned int MCU_WWD_INTERRUPT_TIMER; /*!< (@ 0x00000000) WATCHDOG
11511                                                interrupt timer register */
11512 
11513     struct {
11514       __IOM unsigned int WWD_INTERRUPT_TIMER : 5; /*!< [4..0] Watchdog Timer
11515                                                  programming values */
11516       __IM unsigned int RESERVED1 : 27;           /*!< [31..5] reser           */
11517     } MCU_WWD_INTERRUPT_TIMER_b;
11518   };
11519 
11520   union {
11521     __IOM unsigned int MCU_WWD_SYSTEM_RESET_TIMER; /*!< (@ 0x00000004) MCU watchdog
11522                                                   system reset register */
11523 
11524     struct {
11525       __IOM unsigned int WWD_SYSTEM_RESET_TIMER : 5; /*!< [4..0] Watch dog soc reset delay
11526                                          timer programming values */
11527       __IM unsigned int RESERVED1 : 27;              /*!< [31..5] reser   */
11528     } MCU_WWD_SYSTEM_RESET_TIMER_b;
11529   };
11530 
11531   union {
11532     __IOM unsigned int MCU_WWD_WINDOW_TIMER; /*!< (@ 0x00000008) watchdog window
11533                                             timer register */
11534 
11535     struct {
11536       __IOM unsigned int WINDOW_TIMER : 4; /*!< [3..0] watchdog window timer */
11537       __IM unsigned int RESERVED1 : 28;    /*!< [31..4] reser    */
11538     } MCU_WWD_WINDOW_TIMER_b;
11539   };
11540 
11541   union {
11542     __IOM unsigned int MCU_WWD_ARM_STUCK_EN; /*!< (@ 0x0000000C) watchdog arm stuck
11543                                             enable register */
11544 
11545     struct {
11546       __IM unsigned int RESERVED1 : 16;                /*!< [15..0] reser */
11547       __OM unsigned int PROCESSOR_STUCK_RESET_EN : 1;  /*!< [16..16] Enable to reset M4 core on
11548                                            seeing LOCKUP signal */
11549       __IM unsigned int RESERVED2 : 7;                 /*!< [23..17] reser      */
11550       __IM unsigned int PROCESSOR_STUCK_RESET_EN_ : 1; /*!< [24..24] Read signal for processor
11551                                             stuck reset enable */
11552       __IM unsigned int RESERVED3 : 7;                 /*!< [31..25] reser       */
11553     } MCU_WWD_ARM_STUCK_EN_b;
11554   };
11555 
11556   union {
11557     __IOM unsigned int MCU_WWD_MODE_AND_RSTART; /*!< (@ 0x00000010) WATCHDOG mode
11558                                                and restart register */
11559 
11560     struct {
11561       __IOM unsigned int WWD_MODE_RSTART : 1;    /*!< [0..0] restart pulse to restart
11562                                              watchdog timer */
11563       __IM unsigned int RESERVED1 : 15;          /*!< [15..1] reser       */
11564       __IOM unsigned int WWD_MODE_EN_STATUS : 8; /*!< [23..16] Watchdog timer mode  */
11565       __IM unsigned int RESERVED2 : 8;           /*!< [31..24] reser */
11566     } MCU_WWD_MODE_AND_RSTART_b;
11567   };
11568   __IM unsigned int RESERVED;
11569 
11570   union {
11571     __IOM unsigned int MCU_WWD_KEY_ENABLE; /*!< (@ 0x00000018) watchdog key enable
11572                                           register */
11573 
11574     struct {
11575       __OM unsigned int WWD_KEY_ENABLE : 32; /*!< [31..0] enable access to program
11576                                             Watch dog registers */
11577     } MCU_WWD_KEY_ENABLE_b;
11578   };
11579 } MCU_WDT_Type; /*!< Size = 28 (0x1c) */
11580 
11581 /* ===========================================================================================================================
11582  */
11583 /* ================                                            RTC
11584  * ================ */
11585 /* ===========================================================================================================================
11586  */
11587 
11588 /**
11589  * @brief The MCU calender acts as RTC  with time in seconds, minutes, hours,
11590  * days, months, years and centuries (RTC)
11591  */
11592 
11593 typedef struct { /*!< (@ 0x2404821C) RTC Structure */
11594 
11595   union {
11596     __IOM unsigned int MCU_CAL_ALARM_PROG_1; /*!< (@ 0x00000000) MCU calender alarm
11597                                             prog register 1 */
11598 
11599     struct {
11600       __IOM unsigned int PROG_ALARM_MSEC : 10; /*!< [9..0] milli seconds value of
11601                                               alarm time */
11602       __IOM unsigned int PROG_ALARM_SEC : 6;   /*!< [15..10] seconds value of alarm time */
11603       __IOM unsigned int PROG_ALARM_MIN : 6;   /*!< [21..16] mins value of alarm time */
11604       __IOM unsigned int PROG_ALARM_HOUR : 5;  /*!< [26..22] hours value of alarm time     */
11605       __IM unsigned int RESERVED1 : 5;         /*!< [31..27] reser */
11606     } MCU_CAL_ALARM_PROG_1_b;
11607   };
11608 
11609   union {
11610     __IOM unsigned int MCU_CAL_ALARM_PROG_2; /*!< (@ 0x00000004) MCU calender alarm
11611                                             prog register 2 */
11612 
11613     struct {
11614       __IOM unsigned int PROG_ALARM_DAY : 5;     /*!< [4..0] day count in alarm time 1-31      */
11615       __IM unsigned int RESERVED1 : 3;           /*!< [7..5] reser */
11616       __IOM unsigned int PROG_ALARM_MONTH : 4;   /*!< [11..8] month count in alarm time    */
11617       __IM unsigned int RESERVED2 : 4;           /*!< [15..12] reser */
11618       __IOM unsigned int PROG_ALARM_YEAR : 7;    /*!< [22..16] year count in alarm time
11619                                              0 - 99 */
11620       __IOM unsigned int PROG_ALARM_CENTURY : 2; /*!< [24..23] century count in alarm time  */
11621       __IM unsigned int RESERVED3 : 6;           /*!< [30..25] reser */
11622       __IOM unsigned int ALARM_EN : 1;           /*!< [31..31] alarm function enable for calendar */
11623     } MCU_CAL_ALARM_PROG_2_b;
11624   };
11625 
11626   union {
11627     __IOM unsigned int MCU_CAL_POWERGATE_REG; /*!< (@ 0x00000008) MCU calender
11628                                              powergate register */
11629 
11630     struct {
11631       __IOM unsigned int PG_EN_CALENDER : 1;               /*!< [0..0] Start calender block */
11632       __IOM unsigned int ENABLE_CALENDER_COMBI : 1;        /*!< [1..1] Enable calender
11633                                                    combitional logic block */
11634       __IOM unsigned int DISABLE_COMBI_DYN_PWRGATE_EN : 1; /*!< [2..2] Disable option for
11635                                                     dynamic combo RTC power gate      */
11636       __IOM unsigned int STATIC_COMBI_RTC_PG_EN : 1;       /*!< [3..3] Enable static combo
11637                                                     RTC power gate */
11638       __IM unsigned int RESERVED1 : 28;                    /*!< [31..4] RESERVED1              */
11639     } MCU_CAL_POWERGATE_REG_b;
11640   };
11641 
11642   union {
11643     __IOM unsigned int MCU_CAL_PROG_TIME_1; /*!< (@ 0x0000000C) MCU calendar prog
11644                                            time 1 register */
11645 
11646     struct {
11647       __IOM unsigned int PROG_MSEC : 10; /*!< [9..0] Milli seconds value to be programmed to
11648                              real time in calendar when pro_time_trig is 1 */
11649       __IOM unsigned int PROG_SEC : 6;   /*!< [15..10] seconds value to be programmed to real
11650                            time in calendar when pro_time_trig is 1 */
11651       __IOM unsigned int PROG_MIN : 6;   /*!< [21..16] minutes value to be programmed to real
11652                            time in calendar when pro_time_trig is 1 */
11653       __IOM unsigned int PROG_HOUR : 5;  /*!< [26..22] hours value to be programmed to real time
11654                             in calendar when pro_time_trig is 1 */
11655       __IM unsigned int RESERVED2 : 5;   /*!< [31..27] reser */
11656     } MCU_CAL_PROG_TIME_1_b;
11657   };
11658 
11659   union {
11660     __IOM unsigned int MCU_CAL_PROG_TIME_2; /*!< (@ 0x00000010) MCU calendar prog
11661                                            time 2 register */
11662 
11663     struct {
11664       __IOM unsigned int PROG_DAY : 5;      /*!< [4..0] day count value to be programmed to real
11665                            time in calendar when pro_time_trig is 1 */
11666       __IOM unsigned int PROG_WEEK_DAY : 3; /*!< [7..5] program which week day it is */
11667       __IOM unsigned int PROG_MONTH : 4;    /*!< [11..8] month value to be programmed to real time
11668                              in calendar when pro_time_trig is 1 */
11669       __IM unsigned int RES : 4;            /*!< [15..12] reser */
11670       __IOM unsigned int PROG_YEAR : 7;     /*!< [22..16] year value to be programmed to real time
11671                             in calendar when pro_time_trig is 1 */
11672       __IOM unsigned int PROG_CENTURY : 2;  /*!< [24..23] century value to be programmed to real
11673                                time in calendar when pro_time_trig is 1 */
11674       __IM unsigned int RESERVED1 : 6;      /*!< [30..25] reser      */
11675       __OM unsigned int PROG_TIME_TRIG : 1; /*!< [31..31] load the programmed to the
11676                                            real time in calendar block */
11677     } MCU_CAL_PROG_TIME_2_b;
11678   };
11679 
11680   union {
11681     __IM unsigned int MCU_CAL_READ_TIME_MSB; /*!< (@ 0x00000014) MCU calendar read
11682                                             time msb */
11683 
11684     struct {
11685       __IM unsigned int WEEK_DAY : 3;      /*!< [2..0] week day      */
11686       __IM unsigned int MONTHS_COUNT : 4;  /*!< [6..3] months count  */
11687       __IM unsigned int YEAR_COUNT : 7;    /*!< [13..7] years count    */
11688       __IM unsigned int CENTURY_COUNT : 2; /*!< [15..14] century count */
11689       __IM unsigned int RESERVED1 : 16;    /*!< [31..16] reser    */
11690     } MCU_CAL_READ_TIME_MSB_b;
11691   };
11692 
11693   union {
11694     __IM unsigned int MCU_CAL_READ_TIME_LSB; /*!< (@ 0x00000018) MCU calendar read
11695                                             time lsb */
11696 
11697     struct {
11698       __IM unsigned int MILLISECONDS_COUNT : 10; /*!< [9..0] milliseconds count */
11699       __IM unsigned int SECONDS_COUNT : 6;       /*!< [15..10] seconds count       */
11700       __IM unsigned int MINS_COUNT : 6;          /*!< [21..16] mins count          */
11701       __IM unsigned int HOURS_COUNT : 5;         /*!< [26..22] hours count         */
11702       __IM unsigned int DAYS_COUNT : 5;          /*!< [31..27] days count          */
11703     } MCU_CAL_READ_TIME_LSB_b;
11704   };
11705 
11706   union {
11707     __IM unsigned int MCU_CAL_READ_COUNT_TIMER; /*!< (@ 0x0000001C) MCU calendar
11708                                                read count timer */
11709 
11710     struct {
11711       __IM unsigned int READ_COUNT_TIMER : 27; /*!< [26..0] Read timer which increments by
11712                                       time period value to   reach to count
11713                                       milliseconds   */
11714       __IM unsigned int RESERVED1 : 5;         /*!< [31..27] reser */
11715     } MCU_CAL_READ_COUNT_TIMER_b;
11716   };
11717 
11718   union {
11719     __IM unsigned int MCU_CAL_SLEEP_CLK_COUNTERS; /*!< (@ 0x00000020) MCU calendar
11720                                                  sleep clock counter */
11721 
11722     struct {
11723       __IM unsigned int SLEEP_CLK_DURATION : 12;       /*!< [11..0] No of sleep clks with respect to
11724                                       APB clock so far from
11725                                            the posedge of sleep clk */
11726       __IM unsigned int RESERVED1 : 4;                 /*!< [15..12] reser */
11727       __IM unsigned int PCLK_COUNT_WRT_SLEEP_CLK : 12; /*!< [27..16] no. of APB clks in 1
11728                                             sleep clock duration */
11729       __IM unsigned int RESERVED2 : 4;                 /*!< [31..28] reser       */
11730     } MCU_CAL_SLEEP_CLK_COUNTERS_b;
11731   };
11732 
11733   union {
11734     __OM unsigned int MCU_CAL_KEY_EANBLE; /*!< (@ 0x00000024) MCU calendar key enable */
11735 
11736     struct {
11737       __OM unsigned int RTC_KEY : 32; /*!< [31..0] enable access to program Watch
11738                                      dog registers                      */
11739     } MCU_CAL_KEY_EANBLE_b;
11740   };
11741 } RTC_Type; /*!< Size = 40 (0x28) */
11742 
11743 /* ===========================================================================================================================
11744  */
11745 /* ================                                          BATT_FF
11746  * ================ */
11747 /* ===========================================================================================================================
11748  */
11749 
11750 /**
11751  * @brief The use of this is to store some information in ULP over wake-ups to
11752  * reduce wake-up time (BATT_FF)
11753  */
11754 
11755 typedef struct { /*!< (@ 0x24048400) BATT_FF Structure */
11756 
11757   union {
11758     __IOM unsigned int M4SS_BYPASS_PWRCTRL_REG1; /*!< (@ 0x00000000) M4ss bypass
11759                                                 power control register 1 */
11760 
11761     struct {
11762       __IM unsigned int RES : 3;                                    /*!< [2..0] reserved1 */
11763       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_ULP_AON_b : 1;   /*!< [3..3] Enables software
11764                                                       based control of isolation
11765                                                       and reset
11766                                                        for ULP AON M4ss */
11767       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_EFUSE_b : 1;        /*!< [4..4] Enables software based
11768                                                  control of isolation and reset
11769                                                        for ULP EFUSE */
11770       __IOM unsigned int RESERVED2 : 4;                             /*!< [8..5] reserved2           */
11771       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_RPDMA_b : 1;        /*!< [9..9] Enables software based
11772                                                  control of isolation and reset
11773                                                        for RPDMA */
11774       __IOM unsigned int RESERVED3 : 1;                             /*!< [10..10] reserved3           */
11775       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Enables
11776                                                        software based control of
11777                                                        isolation and reset for
11778                                                        HIF SDIO SPI */
11779       __IOM unsigned int RESERVED4 : 1;                             /*!< [12..12] reserved4                  */
11780       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_QSPI_ICACHE_b : 1;  /*!< [13..13] Enables
11781                                                        software based control of
11782                                                        isolation and reset for
11783                                                        ULP quad SPI and ICACHE
11784                                                      */
11785       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_IID_b : 1;          /*!< [14..14] Enables software based
11786                                                control of isolation and reset
11787                                                        for ULP IID */
11788       __IOM unsigned int RESERVED5 : 2;                             /*!< [16..15] reserved5         */
11789       __IOM
11790       unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_DEBUG_b : 1;      /*!< [17..17] Enables
11791                                                         software based control
11792                                                         of isolation and reset
11793                                                            for M4ss DEBUG */
11794       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b : 1; /*!< [18..18] Enables software
11795                                                    based control of isolation
11796                                                    and reset for M4ss CORE */
11797       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_AON_b : 1;     /*!< [19..19] Enables software based
11798                                                control of isolation and reset
11799                                                        for ULP AON */
11800       __IM unsigned int RESERVED6 : 2;                         /*!< [21..20] reserved6          */
11801       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_ROM_b : 1;     /*!< [22..22] Enables software based
11802                                                control of isolation and reset
11803                                                        for M4ss ROM */
11804       __IM unsigned int RESERVED7 : 9;                         /*!< [31..23] reserved7          */
11805     } M4SS_BYPASS_PWRCTRL_REG1_b;
11806   };
11807 
11808   union {
11809     __IOM unsigned int M4SS_BYPASS_PWRCTRL_REG2; /*!< (@ 0x00000004) M4SS bypass
11810                                                 power control register 2 */
11811 
11812     struct {
11813       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_SRAM_1 : 10; /*!< [9..0] Enables software based
11814                                                  control of isolation and reset
11815                                                        for M4ss SRAM 1 */
11816       __IM unsigned int RESERVED1 : 6;                       /*!< [15..10] reserved1            */
11817       __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_SRAM_2 : 4;  /*!< [19..16] Enables software
11818                                                 based control of isolation and
11819                                                 reset for M4ss SRAM 2 */
11820       __IM unsigned int RESERVED2 : 12;                      /*!< [31..20] reserved1          */
11821     } M4SS_BYPASS_PWRCTRL_REG2_b;
11822   };
11823 
11824   union {
11825     __IOM unsigned int M4SS_PWRCTRL_SET_REG; /*!< (@ 0x00000008) M4SS power control
11826                                             set register */
11827 
11828     struct {
11829       __IM unsigned int RES : 4;                                   /*!< [3..0] reserved1 */
11830       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1;        /*!< [4..4] Power Gate control for
11831                                                 EFUSE */
11832       __IM unsigned int RESERVED2 : 4;                             /*!< [8..5] reserved2           */
11833       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1;        /*!< [9..9] Power Gate control for
11834                                                 RPDMA */
11835       __IM unsigned int RESERVED3 : 1;                             /*!< [10..10] reserved3           */
11836       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate
11837                                                        control for HIF SDIO SPI
11838                                                      */
11839       __IM unsigned int RESERVED4 : 1;                             /*!< [12..12] reserved4                  */
11840       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1;  /*!< [13..13] Power Gate
11841                                                       control for QSPI and
11842                                                       ICACHE              */
11843       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_IID_b : 1;          /*!< [14..14] Power Gate control for
11844                                           IID Block.If set, powered ON
11845                                           Clearing this bit has no effect */
11846       __IM unsigned int RESERVED5 : 2;                             /*!< [16..15] reserved5         */
11847       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1;     /*!< [17..17] Power Gate control
11848                                                    for M4 DEBUG */
11849       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1;      /*!< [18..18] Power Gate control
11850                                                   for M4 CORE */
11851       __IM unsigned int RESERVED6 : 3;                             /*!< [21..19] reserved6             */
11852       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1;      /*!< [22..22] External power gate
11853                                                   enable signal for ROM */
11854       __IM unsigned int RESERVED7 : 9;                             /*!< [31..23] reserved7             */
11855     } M4SS_PWRCTRL_SET_REG_b;
11856   };
11857 
11858   union {
11859     __IOM unsigned int M4SS_PWRCTRL_CLEAR_REG; /*!< (@ 0x0000000C) M4SS power
11860                                               control clear register */
11861 
11862     struct {
11863       __IM unsigned int RES : 4;                                   /*!< [3..0] reserved1 */
11864       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1;        /*!< [4..4] Power Gate control for
11865                                                 EFUSE */
11866       __IM unsigned int RESERVED2 : 4;                             /*!< [8..5] reserved2           */
11867       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1;        /*!< [9..9] Power Gate control for
11868                                                 RPDMA */
11869       __IM unsigned int RESERVED3 : 1;                             /*!< [10..10] reserved3           */
11870       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate
11871                                                        control for HIF SDIO SPI
11872                                                      */
11873       __IM unsigned int RESERVED4 : 1;                             /*!< [12..12] reserved4                  */
11874       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1;  /*!< [13..13] Power Gate
11875                                                       control for QSPI and
11876                                                       ICACHE              */
11877       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_IID_b : 1;          /*!< [14..14] Power Gate control for
11878                                           IID Block.If set, powered ON
11879                                           Clearing this bit has no effect */
11880       __IM unsigned int RESERVED5 : 2;                             /*!< [16..15] reserved5         */
11881       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1;     /*!< [17..17] Power Gate control
11882                                                    for M4 DEBUG */
11883       __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1;      /*!< [18..18] Power Gate control
11884                                                   for M4 CORE */
11885       __IM unsigned int RESERVED6 : 3;                             /*!< [21..19] reserved6             */
11886       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1;      /*!< [22..22] External power gate
11887                                                   enable signal for ROM */
11888       __IM unsigned int RESERVED7 : 9;                             /*!< [31..23] reserved7             */
11889     } M4SS_PWRCTRL_CLEAR_REG_b;
11890   };
11891 
11892   union {
11893     __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG1; /*!< (@ 0x00000010) M4SS power
11894                                                 control set register 1 */
11895 
11896     struct {
11897       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control
11898                                                     signal for M4SS SRAM */
11899       __IM unsigned int RESERVED1 : 6;                          /*!< [15..10] reserved1               */
11900       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4;  /*!< [19..16] Functional Control
11901                                                    signal for TASS SRAM shared
11902                                                    with M4SS */
11903       __IOM unsigned int RESERVED2 : 12;                        /*!< [31..20] reserved1            */
11904     } M4_SRAM_PWRCTRL_SET_REG1_b;
11905   };
11906 
11907   union {
11908     __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000014) M4SS power
11909                                                   control clear register 1 */
11910 
11911     struct {
11912       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control
11913                                                     signal for M4SS SRAM */
11914       __IOM unsigned int RESERVED1 : 6;                         /*!< [15..10] reserved1              */
11915       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4;  /*!< [19..16] Functional Control
11916                                                    signal for TASS SRAM shared
11917                                                    with M4SS */
11918       __IOM unsigned int RESERVED2 : 12;                        /*!< [31..20] reserved1            */
11919     } M4_SRAM_PWRCTRL_CLEAR_REG1_b;
11920   };
11921 
11922   union {
11923     __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000018) M4SS power
11924                                                 control set register 2 */
11925 
11926     struct {
11927       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional
11928                                                          Control signal for M4SS
11929                                                          SRAM Dual Rail pins */
11930       __IOM unsigned int RESERVED1 : 6;                              /*!< [15..10] reserved1                   */
11931       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4;  /*!< [19..16] Functional
11932                                                        Control signal for TASS
11933                                                        SRAM Dual Rail pins
11934                                                        shared with M4SS */
11935       __IOM unsigned int RESERVED2 : 12;                             /*!< [31..20] reserved1                 */
11936     } M4_SRAM_PWRCTRL_SET_REG2_b;
11937   };
11938 
11939   union {
11940     __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x0000001C) M4SS power
11941                                                   control clear register 2 */
11942 
11943     struct {
11944       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional
11945                                                          Control signal for M4SS
11946                                                          SRAM Dual Rail pins */
11947       __IOM unsigned int RESERVED1 : 6;                              /*!< [15..10] reserved1                   */
11948       __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4;  /*!< [19..16] Functional
11949                                                        Control signal for TASS
11950                                                        SRAM Dual Rail pins
11951                                                        shared with M4SS */
11952       __IOM unsigned int RESERVED2 : 12;                             /*!< [31..20] reserved1                 */
11953     } M4_SRAM_PWRCTRL_CLEAR_REG2_b;
11954   };
11955 
11956   union {
11957     __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG3; /*!< (@ 0x00000020) M4SS power
11958                                                 control set register 3 */
11959 
11960     struct {
11961       __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input
11962                                                            isolation control for
11963                                                            M4SS SRAM */
11964       __IOM unsigned int RESERVED1 : 6;                                /*!< [15..10] reserved1 */
11965       __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4;  /*!< [19..16] Input
11966                                                           isolation control for
11967                                                           TASS SRAM shared with
11968                                                           M4SS */
11969       __IOM unsigned int RESERVED2 : 12;                               /*!< [31..20] reserved1 */
11970     } M4_SRAM_PWRCTRL_SET_REG3_b;
11971   };
11972 
11973   union {
11974     __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000024) M4SS power
11975                                                   control clear register 3 */
11976 
11977     struct {
11978       __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input
11979                                                            isolation control for
11980                                                            M4SS SRAM */
11981       __IOM unsigned int RESERVED1 : 6;                                /*!< [15..10] reserved1 */
11982       __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4;  /*!< [19..16] Input
11983                                                           isolation control for
11984                                                           TASS SRAM shared with
11985                                                           M4SS */
11986       __IOM unsigned int RESERVED2 : 12;                               /*!< [31..20] reserved1 */
11987     } M4_SRAM_PWRCTRL_CLEAR_REG3_b;
11988   };
11989 
11990   union {
11991     __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG4; /*!< (@ 0x00000028) M4SS power
11992                                                 control set register 4 */
11993 
11994     struct {
11995       __IOM unsigned int M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for
11996                                              M4SS SRAM */
11997       __IOM unsigned int RESERVED1 : 8;       /*!< [31..24] reserved1       */
11998     } M4_SRAM_PWRCTRL_SET_REG4_b;
11999   };
12000 
12001   union {
12002     __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG4; /*!< (@ 0x0000002C) M4SS power
12003                                                   control clear register 4 */
12004 
12005     struct {
12006       __IOM unsigned int M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for
12007                                              M4SS SRAM */
12008       __IOM unsigned int RESERVED1 : 8;       /*!< [31..24] reserved1       */
12009     } M4_SRAM_PWRCTRL_CLEAR_REG4_b;
12010   };
12011   __IM unsigned int RESERVED;
12012 
12013   union {
12014     __IOM unsigned int M4SS_TASS_CTRL_SET_REG; /*!< (@ 0x00000034) M4SS_TASS control
12015                                               set register */
12016 
12017     struct {
12018       __IOM unsigned int M4SS_CTRL_TASS_AON_PWRGATE_EN : 1;               /*!< [0..0] M4SS controlling Power
12019                                                 supply for TASS AON domain */
12020       __IOM unsigned int M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS
12021                                                        controlling Power supply
12022                                                        for TASS AON domains
12023                                                        isolation enable in
12024                                                        bypass mode */
12025       __IOM unsigned int M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1;       /*!< [2..2] M4SS
12026                                                        controlling Power supply
12027                                                        for TASS AON domains
12028                                                        reset
12029                                                        pin in bypass mode */
12030       __IOM unsigned int RESERVED1 : 29;                                  /*!< [31..3] reserved1                 */
12031     } M4SS_TASS_CTRL_SET_REG_b;
12032   };
12033 
12034   union {
12035     __IOM unsigned int M4SS_TASS_CTRL_CLEAR_REG; /*!< (@ 0x00000038) M4SS_TASS
12036                                                 control CLEAR register */
12037 
12038     struct {
12039       __IOM unsigned int M4SS_CTRL_TASS_AON_PWRGATE_EN : 1;               /*!< [0..0] M4SS controlling Power
12040                                                 supply for TASS AON domain */
12041       __IOM unsigned int M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS
12042                                                        controlling Power supply
12043                                                        for TASS AON domains
12044                                                        isolation enable in
12045                                                        bypass mode */
12046       __IOM unsigned int M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1;       /*!< [2..2] M4SS
12047                                                        controlling Power supply
12048                                                        for TASS AON domains
12049                                                        reset
12050                                                        pin in bypass mode */
12051       __IOM unsigned int RESERVED1 : 29;                                  /*!< [31..3] reserved1                 */
12052     } M4SS_TASS_CTRL_CLEAR_REG_b;
12053   };
12054 
12055   union {
12056     __IOM unsigned int M4_ULP_MODE_CONFIG; /*!< (@ 0x0000003C) m4 ulp mode config register */
12057 
12058     struct {
12059       __IOM unsigned int ULPMODE_ISOLATION_CTRL_ULPSS : 1;        /*!< [0..0] Isolation Control for
12060                                                ULP-Mode non-functional paths for
12061                                                        ULPSS */
12062       __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4SS_AON : 1;     /*!< [1..1] Isolation Control for
12063                                                   ULP-Mode non-functional paths
12064                                                   for M4SS-AON */
12065       __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_ULP : 1;       /*!< [2..2] Isolation Control for
12066                                                 ULP-Mode non-functional paths
12067                                                 for M4ULP_AON */
12068       __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_CORE : 1;      /*!< [3..3] Isolation Control for
12069                                                  ULP-Mode non-functional paths
12070                                                  for M4_CORE */
12071       __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_DEBUG_FPU : 1; /*!< [4..4] Isolation Control
12072                                                       for ULP-Mode
12073                                                       non-functional paths for
12074                                                        M4_DEBUG */
12075       __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_ROM : 1;       /*!< [5..5] Isolation Control for
12076                                                 ULP-Mode non-functional paths
12077                                                 for ROM */
12078       __IOM unsigned int RES : 26;                                /*!< [31..6] reserved1               */
12079     } M4_ULP_MODE_CONFIG_b;
12080   };
12081 
12082   union {
12083     __IOM unsigned int ULPSS_BYPASS_PWRCTRL_REG; /*!< (@ 0x00000040) ULPSS bypass
12084                                                 power control register */
12085 
12086     struct {
12087       __IOM unsigned int RES : 2;                           /*!< [1..0] reserved1 */
12088       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_AON : 1; /*!< [2..2] Enables software based
12089                                                 control of output isolation for
12090                                                        ULPTASS AON */
12091       __IOM
12092       unsigned int BYPASS_ULPSDCSS_PWRCTRL_ULP_AON : 1;      /*!< [3..3] Enables software
12093                                                       based control of output
12094                                                       isolation for
12095                                                            ULPSDCSS AON */
12096       __IOM unsigned int RESERVED2 : 1;                      /*!< [4..4] reser                */
12097       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_MISC : 1; /*!< [5..5] Enables software based
12098                                                  control of output isolation for
12099                                                        ULP MISC */
12100       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_CAP : 1;  /*!< [6..6] Enables software based
12101                                                 control of output isolation for
12102                                                        ULP CAP */
12103       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_VAD : 1;  /*!< [7..7] Enables software based
12104                                                 control of output isolation for
12105                                                        ULP VAD */
12106       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_UART : 1; /*!< [8..8] Enables software based
12107                                                  control of output isolation for
12108                                                        ULP UART */
12109       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_SSI : 1;  /*!< [9..9] Enables software based
12110                                                 control of output isolation for
12111                                                        ULP SSI */
12112       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_I2S : 1;  /*!< [10..10] Enables software
12113                                                 based control of output
12114                                                 isolation for ULP I2S */
12115       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_I2C : 1;  /*!< [11..11] Enables software
12116                                                 based control of output
12117                                                 isolation for ULP I2C */
12118       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_AUX : 1;  /*!< [12..12] Enables software
12119                                            based control of output isolation
12120                                            for ULP AUX */
12121       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_IR : 1;   /*!< [13..13] Enables software based
12122                                           control of output isolation
12123                                           for ULP IR */
12124       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_UDMA : 1; /*!< [14..14] Enables software
12125                                                  based control of output
12126                                                  isolation for ULP UDMA */
12127       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_FIM : 1;  /*!< [15..15] Enables software
12128                                                 based control of output
12129                                                 isolation for ULP FIM */
12130       __IOM unsigned int RESERVED3 : 3;                      /*!< [18..16] reserved1          */
12131       __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_SRAM : 4; /*!< [22..19] Enables software
12132                                                  based control of output
12133                                                  isolation for ULPTASS SRAM */
12134       __IOM unsigned int RESERVED4 : 9;                      /*!< [31..23] reserved1           */
12135     } ULPSS_BYPASS_PWRCTRL_REG_b;
12136   };
12137 
12138   union {
12139     __IOM unsigned int ULPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000044) ULPSS power
12140                                              control set register */
12141 
12142     struct {
12143       __IOM unsigned int RES : 18;                              /*!< [17..0] reserved1 */
12144       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional
12145                                                     Control signal for ULPTASS
12146                                                     MISC            */
12147       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1;  /*!< [19..19] Functional Control
12148                                                    signal for ULPTASS CAP */
12149       __IOM unsigned int RESERVED2 : 1;                         /*!< [20..20] reserved2             */
12150       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional
12151                                                     Control signal for ULPTASS
12152                                                     UART            */
12153       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1;  /*!< [22..22] Functional Control
12154                                                    signal for ULPTASS SSI */
12155       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1;  /*!< [23..23] Functional Control
12156                                                    signal for ULPTASS I2S */
12157       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1;  /*!< [24..24] Functional Control
12158                                                    signal for ULPTASS I2C */
12159       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1;  /*!< [25..25] Functional Control
12160                                                    signal for ULPTASS AUX */
12161       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1;   /*!< [26..26] Functional Control
12162                                                   signal for ULPTASS IR */
12163       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional
12164                                                     Control signal for ULPTASS
12165                                                     UDMA            */
12166       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1;  /*!< [28..28] Functional Control
12167                                                    signal for ULPTASS FIM */
12168       __IOM unsigned int RESERVED3 : 3;                         /*!< [31..29] RESERVED3             */
12169     } ULPSS_PWRCTRL_SET_REG_b;
12170   };
12171 
12172   union {
12173     __IOM unsigned int ULPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000048) ULPSS power
12174                                                control clear register */
12175 
12176     struct {
12177       __IOM unsigned int RESERVED1 : 18;                        /*!< [17..0] reserved1 */
12178       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional
12179                                                     Control signal for ULPTASS
12180                                                     MISC            */
12181       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1;  /*!< [19..19] Functional Control
12182                                                    signal for ULPTASS CAP */
12183       __IOM unsigned int RESERVED2 : 1;                         /*!< [20..20] reserved2             */
12184       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional
12185                                                     Control signal for ULPTASS
12186                                                     UART            */
12187       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1;  /*!< [22..22] Functional Control
12188                                                    signal for ULPTASS SSI */
12189       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1;  /*!< [23..23] Functional Control
12190                                                    signal for ULPTASS I2S */
12191       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1;  /*!< [24..24] Functional Control
12192                                                    signal for ULPTASS I2C */
12193       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1;  /*!< [25..25] Functional Control
12194                                                    signal for ULPTASS AUX */
12195       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1;   /*!< [26..26] Functional Control
12196                                                   signal for ULPTASS IR */
12197       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional
12198                                                     Control signal for ULPTASS
12199                                                     UDMA            */
12200       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1;  /*!< [28..28] Functional Control
12201                                                    signal for ULPTASS FIM */
12202       __IOM unsigned int RESERVED3 : 3;                         /*!< [31..29] RESERVED3             */
12203     } ULPSS_PWRCTRL_CLEAR_REG_b;
12204   };
12205 
12206   union {
12207     __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG1; /*!< (@ 0x0000004C) ULPSS ram power control
12208                                        set register1                      */
12209 
12210     struct {
12211       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control
12212                                                     signal for ULPSS SRAM pins
12213                                                   */
12214       __IOM unsigned int RESERVED1 : 28;                        /*!< [31..4] reserved1             */
12215     } ULPSS_RAM_PWRCTRL_SET_REG1_b;
12216   };
12217 
12218   union {
12219     __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000050) ULPSS ram power
12220                                          control clear register1 */
12221 
12222     struct {
12223       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control
12224                                                     signal for ULPSS SRAM pins
12225                                                   */
12226       __IOM unsigned int RESERVED1 : 28;                        /*!< [31..4] reserved1             */
12227     } ULPSS_RAM_PWRCTRL_CLEAR_REG1_b;
12228   };
12229 
12230   union {
12231     __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000054) ULPSS ram power control
12232                                        set register2                      */
12233 
12234     struct {
12235       __IOM unsigned int ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input
12236                                                            isolation control for
12237                                                            ULPTASS SRAM */
12238       __IOM unsigned int RESERVED1 : 12;                               /*!< [15..4] reserved1         */
12239       __IOM unsigned int SRAM_DS_ULP_PROC_1 : 4;                       /*!< [19..16] Deep-Sleep control
12240                                                 for ULPTASS SRAM */
12241       __IOM unsigned int RESERVED2 : 12;                               /*!< [31..20] reserved1         */
12242     } ULPSS_RAM_PWRCTRL_SET_REG2_b;
12243   };
12244 
12245   union {
12246     __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x00000058) ULPSS ram power
12247                                          control clear register2 */
12248 
12249     struct {
12250       __IOM unsigned int ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input
12251                                                            isolation control for
12252                                                            ULPTASS SRAM */
12253       __IOM unsigned int RESERVED1 : 12;                               /*!< [15..4] reserved1         */
12254       __IOM unsigned int SRAM_DS_ULP_PROC_1 : 4;                       /*!< [19..16] Deep-Sleep control
12255                                                 for ULPTASS SRAM */
12256       __IOM unsigned int RESERVED2 : 12;                               /*!< [31..20] reserved1         */
12257     } ULPSS_RAM_PWRCTRL_CLEAR_REG2_b;
12258   };
12259 
12260   union {
12261     __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG3; /*!< (@ 0x0000005C) ULPSS ram power control
12262                                        set register3                      */
12263 
12264     struct {
12265       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional
12266                                                        Control signal for
12267                                                        ULPTASS SRAM Dual Rail
12268                                                        pins */
12269       __IOM unsigned int RES : 28;                                     /*!< [31..4] reserved1 */
12270     } ULPSS_RAM_PWRCTRL_SET_REG3_b;
12271   };
12272 
12273   union {
12274     __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000060) ULPSS ram power
12275                                          control clear register3 */
12276 
12277     struct {
12278       __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional
12279                                                        Control signal for
12280                                                        ULPTASS SRAM Dual Rail
12281                                                        pins */
12282       __IOM unsigned int RES : 28;                                     /*!< [31..4] reserved1 */
12283     } ULPSS_RAM_PWRCTRL_CLEAR_REG3_b;
12284   };
12285 
12286   union {
12287     __IOM unsigned int MCU_FSM_CTRL_BYPASS; /*!< (@ 0x00000064) MCU FSM control
12288                                            bypass register */
12289 
12290     struct {
12291       __IOM unsigned int MCU_XTAL_EN_40MHZ_BYPASS_CTRL : 1;     /*!< [0..0] Xtal 40mhz enable
12292                                                       bypass from MCU       */
12293       __IOM unsigned int MCU_XTAL_EN_40MHZ_BYPASS : 1;          /*!< [1..1] Value of Xtal
12294                                                       Enable in bypass mode */
12295       __IOM unsigned int MCU_PMU_SHUT_DOWN_BYPASS_CTRL : 1;     /*!< [2..2] Enable bypass mode to
12296                                                 Control pmu shut down */
12297       __IOM unsigned int MCU_PMU_SHUT_DOWN_BYPASS : 1;          /*!< [3..3] Value of pmu shutdown in
12298                                            bypass mode */
12299       __IOM unsigned int MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL : 1; /*!< [4..4] Enable software
12300                                                     control for buck boost
12301                                                     enable           */
12302       __IOM unsigned int MCU_BUCK_BOOST_ENABLE_BYPASS : 1;      /*!< [5..5] Value for MCU BuckBoost
12303                                                Enable in bypass mode */
12304       __IOM unsigned int RES : 26;                              /*!< [31..6] reserved1              */
12305     } MCU_FSM_CTRL_BYPASS_b;
12306   };
12307 
12308   union {
12309     __IOM unsigned int MCU_PMU_LDO_CTRL_SET; /*!< (@ 0x00000068) MCU PMU LD0 control
12310                                             set register */
12311 
12312     struct {
12313       __IOM unsigned int MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */
12314       __IOM unsigned int MCU_SCO_LDO_EN : 1;   /*!< [1..1] Enable SoC LDO from M4SS         */
12315       __IOM unsigned int MCU_DCDC_EN : 1;      /*!< [2..2] Enable PMU DCDC from M4SS */
12316       __IOM unsigned int RESER : 14;           /*!< [16..3] reserved1      */
12317       __IOM unsigned int MCU_SOC_LDO_LVL : 1;  /*!< [17..17] PMU SOC LDO High and Low
12318                                              Voltage selection */
12319       __IOM unsigned int MCU_DCDC_LVL : 1;     /*!< [18..18] PMU DCDC High and Low
12320                                              Voltage selection    */
12321       __IOM unsigned int RES : 13;             /*!< [31..19] reserved1            */
12322     } MCU_PMU_LDO_CTRL_SET_b;
12323   };
12324 
12325   union {
12326     __IOM unsigned int MCU_PMU_LDO_CTRL_CLEAR; /*!< (@ 0x0000006C) MCU PMU LD0
12327                                               control clear register */
12328 
12329     struct {
12330       __IOM unsigned int MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */
12331       __IOM unsigned int MCU_SOC_LDO_EN : 1;   /*!< [1..1] Enable SoC LDO from M4SS         */
12332       __IOM unsigned int MCU_DCDC_EN : 1;      /*!< [2..2] Enable PMU DCDC from M4SS */
12333       __IOM unsigned int RESER : 14;           /*!< [16..3] reserved1      */
12334       __IOM unsigned int MCU_SOC_LDO_LVL : 1;  /*!< [17..17] PMU SOC LDO High and Low
12335                                              Voltage selection */
12336       __IOM unsigned int MCU_DCDC_LVL : 1;     /*!< [18..18] PMU DCDC High and Low
12337                                              Voltage selection    */
12338       __IOM unsigned int RES : 13;             /*!< [31..19] reserved1            */
12339     } MCU_PMU_LDO_CTRL_CLEAR_b;
12340   };
12341   __IM unsigned int RESERVED1[4];
12342 
12343   union {
12344     __IOM unsigned int PLLCCI_PWRCTRL_REG; /*!< (@ 0x00000080) PLL CCI power control
12345                                           register */
12346 
12347     struct {
12348       __IOM unsigned int I2SPLL_ISO_EN : 1;          /*!< [0..0] Enables software based control of
12349                                 isolation and reset for I2SPLL */
12350       __IOM unsigned int I2SPLL_BYPASS_ISO_GEN : 1;  /*!< [1..1] Isolation value */
12351       __IOM unsigned int INTFPLL_ISO_EN : 1;         /*!< [2..2] Enables software based control of
12352                                  isolation and reset for INTF PLL */
12353       __IOM unsigned int INTFPLL_BYPASS_ISO_GEN : 1; /*!< [3..3] Isolation value */
12354       __IOM unsigned int SOCPLL_ISO_ENABLE : 1;      /*!< [4..4] Enables software based control of
12355                                     isolation and reset for SOCPLL */
12356       __IOM unsigned int SOCPLL_BYPASS_ISO_GEN : 1;  /*!< [5..5] Isolation value */
12357       __IOM unsigned int SOCPLL_SPI_PG_EN : 1;       /*!< [6..6] SOCPLL SPI Power Control */
12358       __IOM unsigned int SOCPLL_VDD13_ISO_EN : 1;    /*!< [7..7] SOCPLL MACRO POC Control */
12359       __IOM unsigned int RES : 24;                   /*!< [31..8] reserved1     */
12360     } PLLCCI_PWRCTRL_REG_b;
12361   };
12362 
12363   union {
12364     __IOM unsigned int DLL_PWRCTRL_REG; /*!< (@ 0x00000084) DLL power control register */
12365 
12366     struct {
12367       __IOM unsigned int QSPI_DLL_RX_ISO_ENABLE : 1;     /*!< [0..0] Enables software based control
12368                                          of isolation and reset
12369                                           for QSPI_DLL_TX */
12370       __IOM unsigned int QSPI_DLL_RX_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */
12371       __IOM unsigned int QSPI_DLL_RX_PG_EN_N : 1;        /*!< [2..2] QPSI DLL RX Power Control */
12372       __IOM unsigned int RESER : 1;                      /*!< [3..3] reserved1    */
12373       __IOM unsigned int QSPI_DLL_TX_ISO_ENABLE : 1;     /*!< [4..4] Enables software based control
12374                                          of isolation and reset
12375                                           for QSPI_DLL_TX */
12376       __IOM unsigned int QSPI_DLL_TX_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */
12377       __IOM unsigned int QSPI_DLL_TX_PG_EN_N : 1;        /*!< [6..6] QPSI DLL TX Power Control   */
12378       __IOM unsigned int RESERVED1 : 25;                 /*!< [31..7] reserved1 */
12379     } DLL_PWRCTRL_REG_b;
12380   };
12381 } BATT_FF_Type; /*!< Size = 136 (0x88) */
12382 
12383 /* ===========================================================================================================================
12384  */
12385 /* ================                                          MCU_FSM
12386  * ================ */
12387 /* ===========================================================================================================================
12388  */
12389 
12390 /**
12391  * @brief This is explain the Sleep FSM registers. (MCU_FSM)
12392  */
12393 
12394 typedef struct { /*!< (@ 0x24048100) MCU_FSM Structure */
12395 
12396   union {
12397     __IOM unsigned int MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; /*!< (@ 0x00000000) Sleep Control
12398                                                 Signals and Wakeup source
12399                                                 selection   */
12400 
12401     struct {
12402       __IOM unsigned int MCUFSM_SHUTDOWN_ENABLE : 1;         /*!< [0..0] shutdown enable pulse. */
12403       __IOM unsigned int Reserved1 : 1;                      /*!< [1..1] It is recommended to write these
12404                                        bits to 0.                        */
12405       __IOM unsigned int LP_SLEEP_MODE_b : 1;                /*!< [2..2] setting this bit enables retention of
12406                                   TASS-RAM, M4SS-RAM in PS2 Active/Sleep state
12407                                 */
12408       __IOM unsigned int M4SS_RAM_RETENTION_MODE_EN : 1;     /*!< [3..3] shutdown enable
12409                                                         pulse. */
12410       __IOM unsigned int M4ULP_RAM_RETENTION_MODE_EN_b : 1;  /*!< [4..4] RAM retention enable
12411                                                 for ULP M4 ram during deep sleep
12412                                               */
12413       __IOM unsigned int TA_RAM_RETENTION_MODE_EN : 1;       /*!< [5..5] RAM retention enable for NWP
12414                                            ram during deep sleep */
12415       __IOM unsigned int ULPSS_RAM_RETENTION_MODE_EN : 1;    /*!< [6..6] RAM retention enable for
12416                                               ulpss ram during deep sleep */
12417       __IOM unsigned int M4ULP_RAM16K_RETENTION_MODE_EN : 1; /*!< [7..7] To enable retention
12418                                                  mode for m4ulp 16k RAM */
12419       __IOM unsigned int LDO_SOC_ON_b : 1;                   /*!< [8..8] ON ldo soc during deep sleep */
12420       __IOM unsigned int LDO_FLASH_ON_b : 1;                 /*!< [9..9] ON flash ldo during deep sleep */
12421       __IOM unsigned int PMU_DCDC_ON_b : 1;                  /*!< [10..10] 1: PMU DCDC(BUCK) ON,0:
12422                                            PMU DCDC(BUCK) OFF. */
12423       __IOM unsigned int SKIP_XTAL_WAIT_TIME : 1;            /*!< [11..11] 1 : Skips Xtal Good
12424                                                  Delay wait time. */
12425       __IOM unsigned int Reserved2 : 2;                      /*!< [13..12] It is recommended to write
12426                                        these bits to 0.                      */
12427       __IOM unsigned int MCUFSM_WAKEUP_NWPFSM : 1;           /*!< [14..14] When Set, mcufsm wakeup enable
12428                                        will wakeup both NWP FSM and MCU
12429                                        FSM.Clear this BIT if this feature is not
12430                                        required..          */
12431       __IOM unsigned int SLEEP_WAKEUP : 1;                   /*!< [15..15] Wakeup indication from Processor */
12432       __IOM unsigned int TIMER_BASED_WAKEUP_b : 1;           /*!< [16..16] wakeup enable after deep sleep
12433                                        counter elapses                   */
12434       __IOM unsigned int HOST_BASED_WAKEUP_b : 1;            /*!< [17..17] host based wakeup enable */
12435       __IOM unsigned int WIRELESS_BASED_WAKEUP_b : 1;        /*!< [18..18] wireless based
12436                                                      wakeup enable */
12437       __IOM unsigned int M4_PROC_BASED_WAKEUP_b : 1;         /*!< [19..19] wakeup based on
12438                                                      m4 processor enable  */
12439       __IOM unsigned int GPIO_BASED_WAKEUP_b : 1;            /*!< [20..20] wakeup on gpio interrupt enable
12440                                       based in configuration in GPIO WAKEUP
12441                                       REGISTER */
12442       __IOM unsigned int COMPR_BASED_WAKEUP_b : 1;           /*!< [21..21] compartor based
12443                                                   wakeup enable, either of any 6
12444                                                   comparator interrupts */
12445 #if defined(SLI_SI917B0) || defined(SLI_SI915)
12446       __IOM unsigned int SYSRTC_BASED_WAKEUP_b : 1; /*!< [22..22] SYSRTC Based Wakeup */
12447 #else
12448       __IOM unsigned int Reserved3 : 1;                /*!< [22..22] It is recommended to write
12449                                        these bits to 0.                      */
12450 #endif
12451       __IOM unsigned int WIC_BASED_WAKEUP_b : 1;      /*!< [23..23] WIC based wakeup mask */
12452       __IOM unsigned int ULPSS_BASED_WAKEUP_b : 1;    /*!< [24..24] ULPSS peripheral
12453                                                   based wakeup */
12454       __IOM unsigned int SDCSS_BASED_WAKEUP_b : 1;    /*!< [25..25] Sensor Data
12455                                                   collector based wakeup */
12456       __IOM unsigned int ALARM_BASED_WAKEUP_b : 1;    /*!< [26..26] Alarm Based wakeup */
12457       __IOM unsigned int SEC_BASED_WAKEUP_b : 1;      /*!< [27..27] Second Pulse Based wakeup */
12458       __IOM unsigned int MSEC_BASED_WAKEUP_b : 1;     /*!< [28..28] Millisecond Pulse
12459                                                  Based wakeup */
12460       __IOM unsigned int WDT_INTR_BASED_WAKEUP_b : 1; /*!< [29..29] Millisecond
12461                                                      Pulse Based wakeup */
12462       __IOM unsigned int ULPSS_BASED_SLEEP : 1;       /*!< [30..30] ULPSS initiated DeepSleep. */
12463       __IOM unsigned int SDCSS_BASED_SLEEP : 1;       /*!< [31..31] SDCSS initiated DeepSleep. */
12464     } MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b;
12465   };
12466 
12467   union {
12468     __IOM unsigned int MCU_FSM_PERI_CONFIG_REG; /*!< (@ 0x00000004) Configuration
12469                                                for Ultra Low-Power Mode of the
12470                                                                     processor
12471                                                (PS2 State) */
12472 
12473     struct {
12474       __IOM unsigned int ULP_MCU_MODE_EN : 1;                  /*!< [0..0] Enables voltage switching
12475                                              for PS2-PS4/PS3 and PS4/PS3-PS2
12476                                                      state transitions. */
12477       __IOM unsigned int M4SS_CONTEXT_SWITCH_TOP_ULP_MODE : 2; /*!< [2..1] Enable functional
12478                                                    switching for PS2-PS4/PS3 and
12479                                                    PS4/PS3-PS2
12480                                                        state transitions */
12481       __IOM unsigned int WICENREQ : 1;                         /*!< [3..3] Its enable or disable maximum of 32KB of
12482                            LP-SRAM for operation in PS2 state */
12483       __IOM unsigned int Reserved1 : 12;                       /*!< [15..4] It is recommended to write
12484                                         these bits to 0. */
12485       __IOM unsigned int BGPMU_SAMPLING_EN_R : 1;              /*!< [16..16] Controls the mode of Band-Gap
12486                                         for DC-DC 1.35 during   PS2 state.   */
12487       __IOM unsigned int Reserved2 : 15;                       /*!< [31..17] It is recommended to write
12488                                         these bits to 0.                      */
12489     } MCU_FSM_PERI_CONFIG_REG_b;
12490   };
12491 
12492   union {
12493     __IOM unsigned int GPIO_WAKEUP_REGISTER; /*!< (@ 0x00000008) GPIO Wakeup Register */
12494 
12495     struct {
12496       __IOM unsigned int GPIO_0_WAKEUP : 1;           /*!< [0..0] Enable gpio 0 based wakeup. */
12497       __IOM unsigned int GPIO_1_WAKEUP : 1;           /*!< [1..1] Enable gpio 1 based wakeup */
12498       __IOM unsigned int GPIO_2_WAKEUP : 1;           /*!< [2..2] Enable gpio 2 based wakeup */
12499       __IOM unsigned int GPIO_3_WAKEUP : 1;           /*!< [3..3] Enable gpio 3 based wakeup */
12500       __IOM unsigned int GPIO_4_WAKEUP : 1;           /*!< [4..4] Enable gpio 3 based wakeup         */
12501       __IOM unsigned int Reserved1 : 11;              /*!< [15..5] It is recommended to write
12502                                         these bits to 0. */
12503       __IOM unsigned int CONTINIOUS_START : 1;        /*!< [16..16] Trigger Deep sleep
12504                                               timer to start counting. */
12505       __IOM unsigned int CONTINIOUS_TIMER_ENABLE : 1; /*!< [17..17] Enable Deep sleep timer
12506                                           mode continuous. */
12507       __IOM unsigned int DS_TIMER_SOFT_RESET : 1;     /*!< [18..18] Enable Deep sleep
12508                                                  timer mode continuous. */
12509       __IOM unsigned int Reserved2 : 13;              /*!< [31..19] It is recommended to write
12510                                         these bits to 0.                      */
12511     } GPIO_WAKEUP_REGISTER_b;
12512   };
12513 
12514   union {
12515     __IOM unsigned int MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG; /*!< (@ 0x0000000C) MCU FSM DEEP
12516                                                 SLEEP DURATION LSB Register */
12517 
12518     struct {
12519       __IOM
12520       unsigned int MCUFSM_DEEPSLEEP_DURATION_COUNT : 32; /*!< [31..0] LSB bits of
12521                                                        deep sleep duration
12522                                                        counter after which
12523                                                            system wakes up is
12524                                                        timeout wakeup is
12525                                                        enabled. */
12526     } MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG_b;
12527   };
12528 
12529   union {
12530     __IOM unsigned int MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG; /*!< (@ 0x00000010) MCU FSM XTAL
12531                                                 AND PMU GOOD COUNT Register */
12532 
12533     struct {
12534       __IOM unsigned int MCUFSM_PMU_POWERGOOD_DURATION_COUNT : 7; /*!< [6..0] Wait Delay for
12535                                                       PMU POWER GOOD 0 - 5us 1 -
12536                                                       10us 2 - 12.5us
12537                                                        3 - 25us 4 - 50us 5 -
12538                                                       75us. */
12539       __IOM unsigned int Reserved1 : 9;                           /*!< [15..7] It is recommended to write
12540                                         these bits to 0. */
12541       __IOM unsigned int MCUFSM_XTAL_GOODTIME_DURATION_COUNT : 7; /*!< [22..16] Wait Delay for
12542                                                       XTAL GOOD Time 0 - 5us 1 -
12543                                                       10us.     */
12544       __IOM unsigned int Reserved2 : 9;                           /*!< [31..23] It is recommended to write
12545                                         these bits to 0.                      */
12546     } MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b;
12547   };
12548 
12549   union {
12550     __IOM unsigned int MCU_FSM_POWER_CTRL_AND_DELAY; /*!< (@ 0x00000014) Power Control and
12551                                          Delay Configuration for Ultra
12552                                                          Low-Power Mode of the
12553                                          processor (PS2 State)                */
12554 
12555     struct {
12556       __IOM unsigned int PS2_PMU_LDO_OFF_DELAY : 5;        /*!< [4..0] PMU BUCK And LDO
12557                                                    Turn-OFF Delay. */
12558       __IOM unsigned int Reserved1 : 3;                    /*!< [7..5] It is recommended to write these
12559                                        bits to 0.                        */
12560       __IOM unsigned int PS4_SOCLDO_ON_DELAY : 4;          /*!< [11..8] PMU SOCLDO Turn-ON Delay. */
12561       __IOM unsigned int PG4_BUCK_ON_DELAY : 4;            /*!< [15..12] PMU Buck Turn-ON Delay. */
12562       __IOM unsigned int FSM_PERI_SOC_LDO_EN : 1;          /*!< [16..16] Enable SOCLDO in
12563                                                  Peri mode. */
12564       __IOM unsigned int FSM_PERI_DCDC_EN : 1;             /*!< [17..17] Enable DCDC in Peri mode.     */
12565       __IOM unsigned int Reserved2 : 1;                    /*!< [18..18] It is recommended to write
12566                                        these bits to 0.                      */
12567       __IOM unsigned int POWER_MUX_SEL_ULPSS : 1;          /*!< [19..19] Select value for
12568                                                   ULPSS(Peripherals) Power Mux             */
12569       __IOM unsigned int POWER_MUX_SEL_M4_ULP : 2;         /*!< [21..20] Select value for M4
12570                                                   ULP (Peripherals + Cortex Core
12571                                                      )Power Mux. */
12572       __IOM unsigned int POWER_MUX_SEL_M4_ULP_RAM_16K : 2; /*!< [23..22] Select value for M4
12573                                                ULP RAM 16K Power Mux */
12574       __IOM unsigned int POWER_MUX_SEL_M4_ULP_RAM : 2;     /*!< [25..24] Select value for M4 ULP
12575                                            RAM Power Mux. */
12576       __IOM unsigned int POWER_MUX_SEL_ULPSS_RAM : 2;      /*!< [27..26] Select value for
12577                                                      ULPSS RAM Power Mux. */
12578       __IOM unsigned int Reserved3 : 4;                    /*!< [31..28] It is recommended to write
12579                                        these bits to 0.                      */
12580     } MCU_FSM_POWER_CTRL_AND_DELAY_b;
12581   };
12582 
12583   union {
12584     __IOM unsigned int MCU_FSM_CLKS_REG; /*!< (@ 0x00000018) MCU FSM Clocks Register */
12585 
12586     struct {
12587       __IOM unsigned int Reserved1 : 2;                /*!< [1..0] It is recommended to write these
12588                                        bits to 0.                        */
12589       __IOM unsigned int HF_FSM_CLK_SELECT : 3;        /*!< [4..2] Disable signal for m4ss
12590                                                reference clock. */
12591       __IOM unsigned int Reserved2 : 10;               /*!< [14..5] It is recommended to write
12592                                         these bits to 0. */
12593       __IOM unsigned int HF_FSM_CLK_SWITCHED_SYNC : 1; /*!< [15..15] If high freq fsm clock
12594                                              select is modified.   */
12595       __IOM unsigned int HF_FSM_CLK_FREQ : 6;          /*!< [21..16] High Frequency Source
12596                                              Clock value in MHz. */
12597       __IOM unsigned int US_DIV_COUNT : 2;             /*!< [23..22] One Micro second division factor.
12598                                Program value to
12599                                           3. If hf_fsm_gen_2mhz is 0 Program
12600                                value to 1. If hf_fsm_gen_2mhz is 1. */
12601       __IOM unsigned int HF_FSM_GEN_2MHZ : 1;          /*!< [24..24] Enable 2Mhz clock for FSM 1 -Enable
12602                                   2Mhz option 0- Enable 4MHz option. */
12603       __IOM unsigned int HF_FSM_CLK_EN : 1;            /*!< [25..25] high frequency mcu fsm
12604                                            clock enable. */
12605       __IOM unsigned int Reserved3 : 6;                /*!< [31..26] It is recommended to write
12606                                            these bits to 0.                      */
12607     } MCU_FSM_CLKS_REG_b;
12608   };
12609 
12610   union {
12611     __IOM unsigned int MCU_FSM_REF_CLK_REG; /*!< (@ 0x0000001C) MCU FSM Clocks Register */
12612 
12613     struct {
12614       __IOM unsigned int M4SS_REF_CLK_SEL : 3;            /*!< [2..0] Dynamic Reference Clock Mux select
12615                                    of M4SS 0 - Clock will be gated at dynamic
12616                                    mux output of M4SS 1 - ulp_mhz_rc_byp_clk
12617                                           2 - ulp_mhz_rc_clk 3 - rf_ref_clk 4
12618                                    - mems_ref_clk 5
12619                                           - ulp_20mhz_ringosc_clk 6 -
12620                                    ulp_doubler_clk 7 - ref_byp_clk to TASS. */
12621       __IOM unsigned int Reserved1 : 4;                   /*!< [6..3] It is recommended to write these
12622                                        bits to 0.                        */
12623       __IOM unsigned int M4SS_REF_CLK_CLEANER_OFF_b : 1;  /*!< [7..7] Disable signal for m4ss
12624                                              reference clock. */
12625       __IOM unsigned int M4SS_REF_CLK_CLEANER_ON_b : 1;   /*!< [8..8] Enable clk cleaner for m4ss
12626                                             reference clock. */
12627       __IOM unsigned int Reserved2 : 3;                   /*!< [11..9] It is recommended to write
12628                                             these bits to 0.                       */
12629       __IOM unsigned int TASS_REF_CLK_SEL : 3;            /*!< [14..12] Dynamic Reference Clock Mux select
12630                                    of TASS controlled by M4. 0 : Clock will be
12631                                    gated at dynamic mux output of TASS 1 :
12632                                    ulp_mhz_rc_byp_clk 2 : ulp_mhz_rc_clk 3 :
12633                                           rf_ref_clk 4 : mems_ref_clk 5 :
12634                                    ulp_20mhz_ringosc_clk 6 : ref_byp_clk to
12635                                    TASS. */
12636       __IOM unsigned int Reserved3 : 1;                   /*!< [15..15] It is recommended to write
12637                                        these bits to 0.                      */
12638       __IOM unsigned int ULPSS_REF_CLK_SEL_b : 3;         /*!< [18..16] Dynamic Reference Clock Mux
12639                                        select of TASS controlled  by M4. 0 : Clock
12640                                        will be gated at dynamic mux output of
12641                                            TASS 1 : ulp_mhz_rc_byp_clk 2 :
12642                                        ulp_mhz_rc_clk 3 :  rf_ref_clk 4 :
12643                                        mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6
12644                                            : ref_byp_clk to TASS.  */
12645       __IOM unsigned int Reserved4 : 4;                   /*!< [22..19] It is recommended to write
12646                                        these bits to 0.                      */
12647       __IOM unsigned int ULPSS_REF_CLK_CLEANER_OFF_b : 1; /*!< [23..23] Clock cleaner Off
12648                                               signal for ulpss ref clock. */
12649       __IOM unsigned int ULPSS_REF_CLK_CLEANER_ON_b : 1;  /*!< [24..24] Clock cleaner Off signal
12650                                              for ulpss ref clock. */
12651       __IOM unsigned int Reserved5 : 3;                   /*!< [27..25] It is recommended to write
12652                                        these bits to 0.                      */
12653       __IOM unsigned int SDCSS_CLK_SEL_b : 2;             /*!< [29..28] select between RC / RO
12654                                              32KHz clk in sdcss 01 - MHz RC
12655                                              Clock 10- 20MHz RO Clock. */
12656       __IOM unsigned int SDCSS_CLK_EN_b : 1;              /*!< [30..30] To enable dynamic clock
12657                                              for sdcss  */
12658       __IOM unsigned int SDCSS_STATIC_CLK_EN_b : 1;       /*!< [31..31] To enable static clk for
12659                                         sensor data collector subsystem */
12660     } MCU_FSM_REF_CLK_REG_b;
12661   };
12662 
12663   union {
12664     __IOM unsigned int MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; /*!< (@ 0x00000020) MCU FSM
12665                                                         And First Bootup */
12666 
12667     struct {
12668       __IOM unsigned int FIRST_BOOTUP_MCU_N_b : 1;       /*!< [0..0] Indication for S/W to
12669                                        distinguish b/w First Power or ULP
12670                                        wakeup.S/W need to set this Bit after
12671                                        first power ..                  */
12672       __IM unsigned int RAM_RETENTION_STATUS_M4SS_b : 1; /*!< [1..1] Indicates to S/W that
12673                                               RAM's were in retention mode
12674                                               during Sleep time. 1 - RAM are in
12675                                               retention mode during sleep. 0 -
12676                                               RAM are not in retention mode
12677                                               during sleep.Domain is OFF.. */
12678       __IOM unsigned int RETENTION_DOMAIN_ON_b : 1;      /*!< [2..2] Indicates to S/W that Retention
12679                                         domain is ON. 1 - Domain is ON. 0 -
12680                                         Domain is OFF.. */
12681       __IOM unsigned int CHIP_MODE_VALID_b : 1;          /*!< [3..3] Indicates to S/W that ChipMode
12682                                     programming are valid and need not read
12683                                     EFUSE. 1 - ChipMode are Valid. 0 - ChipModes
12684                                       are invalid. */
12685       __IOM unsigned int STORAGE_DOMAIN_ON_b : 1;        /*!< [4..4] Indicates to S/W that
12686                                                  MCU Data Storage 1 domain is
12687                                                  ON. 1 - Domain is ON. 0 -
12688                                                  Domain is OFF.. */
12689 #if !defined(SLI_SI917B0) && !defined(SLI_SI915)
12690       __IOM unsigned int Reserved1 : 10; /*!< [14..5] It is recommended to write
12691                                         these bits to 0. */
12692 #else
12693       __IOM unsigned int Reserved1 : 9;                /*!< [13..5] It is recommended to write
12694                                        these bits to 0.                       */
12695       __IOM unsigned int MCU_ULP_1KHZ_RC_CLK_EN_b : 1; /*!< [14..14] Enables ULP 1KHz Rc Clock
12696                                            (For SYSRTC and MCU WWD). */
12697 #endif
12698       __IOM unsigned int MCU_FSM_RESET_N_SYNC_b : 1;          /*!< [15..15] Indicated MCU FSM is out of
12699                                          reset. 1 : Indicated MCU
12700                                           FSM is out of reset 0 : Indicated MCU
12701                                          FSM is in reset.                    */
12702       __IOM unsigned int MCU_ULP_32KHZ_RC_CLK_EN_b : 1;       /*!< [16..16] Enables ULP
12703                                                          32KHz Rc Clock.   */
12704       __IOM unsigned int MCU_ULP_32KHZ_RO_CLK_EN_b : 1;       /*!< [17..17] Enables ULP
12705                                                          32KHz RO Clock.   */
12706       __IOM unsigned int MCU_ULP_32KHZ_XTAL_CLK_EN_b : 1;     /*!< [18..18] Enables ULP
12707                                                          32KHz Xtal Clock. */
12708       __IOM unsigned int MCU_ULP_MHZ_RC_CLK_EN_b : 1;         /*!< [19..19] Enables ULP
12709                                                          MHz RC Clock.   */
12710       __IOM unsigned int MCU_ULP_20MHZ_RING_OSC_CLK_EN_b : 1; /*!< [20..20] Enables ULP 20mhz
12711                                                   RO Clock. */
12712       __IOM unsigned int MCU_ULP_DOUBLER_CLK_EN_b : 1;        /*!< [21..21] Enables ULP
12713                                                       Doubler Clock. */
12714       __IOM unsigned int MCU_ULP_40MHZ_CLK_EN_b : 1;          /*!< [22..22] Enables 40MHz
12715                                                       XTAL clock.   */
12716       __IOM unsigned int Reserved2 : 9;                       /*!< [31..23] It is recommended to write
12717                                        these bits to 0.                      */
12718     } MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b;
12719   };
12720 
12721   union {
12722     __IOM unsigned int MCU_FSM_CRTL_PDM_AND_ENABLES; /*!< (@ 0x00000024) Power Domains
12723                                          Controlled by Sleep FSM. */
12724 
12725     struct {
12726       __IOM unsigned int ENABLE_WDT_IN_SLEEP_b : 1;          /*!< [0..0] Its enable or disable WDT
12727                                         during Sleep/Shutdown states. */
12728       __IOM unsigned int ENABLE_WURX_DETECTION_b : 1;        /*!< [1..1] Its enable or disable
12729                                           detection of On-Air Pattern using
12730                                           Wake-Fi Rx. */
12731       __IOM unsigned int RESET_MCU_BBF_DM_EN_b : 1;          /*!< [2..2] Its enable or disable reset of
12732                                         Power Domain Control Battery FF's on
12733                                         wakeup. */
12734       __IOM unsigned int DISABLE_TURNOFF_SRAM_PERI_b : 1;    /*!< [3..3] Enable MCU SRAM periphery
12735                                           during Deepsleep 1 - Enable SRAM
12736                                           periphery during Deepsleep 0 - Disable
12737                                           SRAM periphery during Deepsleep. */
12738       __IOM unsigned int ENABLE_SRAM_DS_CRTL_b : 1;          /*!< [4..4] Enable signal for controlling
12739                                     Deepsleep signal of all SRAM used by M4 1-
12740                                     Enable SRAM Deepsleep Signal 0- Disable
12741                                     SRAM Deepsleep Signal. */
12742       __IOM unsigned int Reserved1 : 11;                     /*!< [15..5] It is recommended to write
12743                                         these bits to 0. */
12744       __IOM unsigned int POWER_ENABLE_FSM_PERI_b : 1;        /*!< [16..16] Its enable or disable Power
12745                                           to Low-Power FSM.                   */
12746       __IOM unsigned int POWER_ENABLE_TIMESTAMPING_b : 1;    /*!< [17..17] Its enable or disable
12747                                               Power to TIMESTAMP. */
12748       __IOM unsigned int POWER_ENABLE_DEEPSLEEP_TIMER_b : 1; /*!< [18..18] Its enable or
12749                                                  disable Power to DEEP SLEEP
12750                                                  Timer.         */
12751       __IOM unsigned int POWER_ENABLE_RETENTION_DM_b : 1;    /*!< [19..19] Its enable or disable
12752                                               Power to Retention Flops during
12753                                                        SHIP state.These Flops
12754                                               are used for storing Chip
12755                                               Configuration.           */
12756       __IOM unsigned int Reserved2 : 12;                     /*!< [31..20] It is recommended to write
12757                                         these bits to 0.                      */
12758     } MCU_FSM_CRTL_PDM_AND_ENABLES_b;
12759   };
12760 
12761   union {
12762     __IOM unsigned int MCU_GPIO_TIMESTAMPING_CONFIG; /*!< (@ 0x00000028) MCU GPIO
12763                                                     TIMESTAMPING CONFIG. */
12764 
12765     struct {
12766       __IOM unsigned int ENABLE_GPIO_TIMESTAMPING_b : 1; /*!< [0..0] Enable GPIO time stamping
12767                                              Feature.. */
12768       __IOM unsigned int TIMESTAMPING_ON_GPIO0_b : 1;    /*!< [1..1] Enable GPIO time
12769                                                      stamping on GPIO0. */
12770       __IOM unsigned int TIMESTAMPING_ON_GPIO1_b : 1;    /*!< [2..2] Enable GPIO time
12771                                                      stamping on GPIO1. */
12772       __IOM unsigned int TIMESTAMPING_ON_GPIO2_b : 1;    /*!< [3..3] Enable GPIO time
12773                                                      stamping on GPIO2. */
12774       __IOM unsigned int TIMESTAMPING_ON_GPIO3_b : 1;    /*!< [4..4] Enable GPIO time
12775                                                      stamping on GPIO3. */
12776       __IOM unsigned int TIMESTAMPING_ON_GPIO4_b : 1;    /*!< [5..5] Enable GPIO time
12777                                                      stamping on GPIO4. */
12778       __IOM unsigned int Reserved1 : 26;                 /*!< [31..6] It is recommended to write
12779                                         these bits to 0. */
12780     } MCU_GPIO_TIMESTAMPING_CONFIG_b;
12781   };
12782 
12783   union {
12784     __IM unsigned int MCU_GPIO_TIMESTAMP_READ; /*!< (@ 0x0000002C) MCU GPIO
12785                                               TIMESTAMPING READ. */
12786 
12787     struct {
12788       __IM unsigned int GPIO_EVENT_COUNT_PARTIAL : 11; /*!< [10..0] Counter value indicating
12789                                            the duration from GPIO going high to
12790                                            first Sleep clock( MCU FSM Clock)
12791                                            posedge from GPIO going high with
12792                                            respect to MHz RC clock. */
12793       __IM unsigned int Reserved1 : 5;                 /*!< [15..11] It is recommended to write
12794                                       these bits to 0.                      */
12795       __IM unsigned int GPIO_EVENT_COUNT_FULL : 11;    /*!< [26..16] Counter value indicating
12796                                          number for RC MHz clock present in 1
12797                                          Sleep clock (MCU FSM Clock). */
12798       __IM unsigned int Reserved2 : 5;                 /*!< [31..27] It is recommended to write
12799                                          these bits to 0.                      */
12800     } MCU_GPIO_TIMESTAMP_READ_b;
12801   };
12802 
12803   union {
12804     __IOM unsigned int MCU_SLEEPHOLD_REQ; /*!< (@ 0x00000030) MCU SLEEP HOLD REQ. */
12805 
12806     struct {
12807       __IOM unsigned int SLEEPHOLDREQn : 1;   /*!< [0..0] Sleepholdreq when enable
12808                                            will gate the clock to M4. 1
12809                                                      - Sleepholdreq is Disabled.
12810                                            0 - Sleepholdreq is Enabled. */
12811       __IM unsigned int SLEEPHOLDACKn : 1;    /*!< [1..1] SLEEPHOLDACK response to
12812                                            SLEEPHOLDREQ.  */
12813       __IOM unsigned int Reserved1 : 14;      /*!< [15..2] It is recommended to write
12814                                            these bits to 0.    */
12815       __IOM unsigned int SELECT_FSM_MODE : 1; /*!< [16..16] Enable for selecting secondary FSM.
12816                                   1 - Select Secondary FSM 0 - Select Primary
12817                                   FSM. */
12818       __IOM unsigned int Reserved2 : 15;      /*!< [31..17] It is recommended to write
12819                                         these bits to 0.                      */
12820     } MCU_SLEEPHOLD_REQ_b;
12821   };
12822   __IM unsigned int RESERVED;
12823 
12824   union {
12825     __IOM unsigned int MCU_FSM_WAKEUP_STATUS_REG; /*!< (@ 0x00000038) MCU FSM Wakeup
12826                                                  Status Register. */
12827 
12828     struct {
12829       __IOM unsigned int WAKEUP_STATUS : 11;            /*!< [10..0] To know the wakeup source.       */
12830       __IOM unsigned int Reserved1 : 5;                 /*!< [15..11] It is recommended to write
12831                                        these bits to 0.                      */
12832       __IOM unsigned int MCU_FIRST_POWERUP_POR : 1;     /*!< [16..16] Indication to Processor that
12833                                         system came out first power up. */
12834       __IOM unsigned int MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Indication to Processor
12835                                             that system came out of Reset. */
12836       __IOM unsigned int Reserve2 : 14;                 /*!< [31..18] It is recommended to write
12837                                        these bits to 0.                      */
12838     } MCU_FSM_WAKEUP_STATUS_REG_b;
12839   };
12840 
12841   union {
12842     __IOM unsigned int MCU_FSM_WAKEUP_STATUS_CLEAR; /*!< (@ 0x0000003C) MCU FSM
12843                                                    Wakeup Status Clear. */
12844 
12845     struct {
12846       __IOM unsigned int WWD_INTERRUPT_STATUS_CLEAR_b : 1;          /*!< [0..0] To Clear WatchDog
12847                                                Interrupt status indication. */
12848       __IOM unsigned int MILLI_SEC_BASED_STATUS_CLEAR_b : 1;        /*!< [1..1] To Clear Milli-Second
12849                                                  Wakeup status indication. */
12850       __IOM unsigned int RTC_SEC_BASED_STATUS_CLEAR_b : 1;          /*!< [2..2] To Clear Second Tick
12851                                                wakeup status indication. */
12852       __IOM unsigned int RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [3..3] To Clear RTC
12853                                                         Alarm wakeup status
12854                                                         indicaition.       */
12855       __IOM unsigned int COMP1_BASED_WAKEUP_STATUS_CLEAR_b : 1;     /*!< [4..4] To Clear comp1
12856                                                     wakeup (Analog IP1 and
12857                                                     Analog IP2) status
12858                                                        indication. */
12859       __IOM unsigned int COMP2_BASED_WAKEUP_STATUS_CLEAR_b : 1;     /*!< [5..5] To Clear comp2
12860                                                     wakeup (Analog IP1 and
12861                                                     BandGap Scale) status
12862                                                     indication. */
12863       __IOM
12864       unsigned int COMP3_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [6..6] To Clear comp3
12865                                                         wakeup (Analog IP1 and
12866                                                         VBatt Scale) status
12867                                                            indication. */
12868       __IOM
12869       unsigned int COMP4_BASED_WAKEUP_STATUS_CLEAR_b : 1;       /*!< [7..7] To Clear Comp4
12870                                                         wakeup (Bandgap En and
12871                                                         VBatt Scale) status
12872                                                            indication. */
12873       __IOM unsigned int COMP5_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [8..8] To Clear BOD Wakeup
12874                                                     status indication. */
12875       __IOM unsigned int COMP6_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [9..9] To Clear
12876                                                     Button-wake status
12877                                                     indication. */
12878 #if !defined(SLI_SI917B0) && !defined(SLI_SI915)
12879       __IOM unsigned int RF_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear WuRX status
12880                                                indication. */
12881 #else
12882       __IOM unsigned int SYSRTC_WAKEUP_CLEAR_b : 1;    /*!< [10..10] To Clear SYSRTC Wakeup status
12883                                         indication. */
12884 #endif
12885       __IOM unsigned int Reserved1 : 21; /*!< [31..11] It is recommended to write
12886                                         these bits to 0.                      */
12887     } MCU_FSM_WAKEUP_STATUS_CLEAR_b;
12888   };
12889 
12890   union {
12891     __IOM unsigned int MCU_FSM_PMU_STATUS_REG; /*!< (@ 0x00000040) MCU FSM PMU
12892                                               Status Register. */
12893 
12894     struct {
12895       __IOM unsigned int SCDCDC_LP_MODE_EN : 1;  /*!< [0..0] SCDC in LP mode. */
12896       __IOM unsigned int BGPMU_SLEEP_EN_R_b : 1; /*!< [1..1] Sleep en for BG PMU.    */
12897       __IOM unsigned int Reserved1 : 15;         /*!< [16..2] It is recommended to write
12898                                         these bits to 0. */
12899       __IOM unsigned int STANDBY_LDORF_R : 1;    /*!< [17..17] Standby state for LDO RF. */
12900       __IOM unsigned int STANDBY_LDOSOC_R : 1;   /*!< [18..18] Standby state for LDO soc. */
12901       __IOM unsigned int STANDBY_DC1P3_R : 1;    /*!< [19..19] Standby state for DC1p3. */
12902       __IM unsigned int POWERGOOD_LDOSOC : 1;    /*!< [20..20] Powergood signal from ldosoc. */
12903       __IM unsigned int LEVEL_OK_DC1P3 : 1;      /*!< [21..21] Powergood signal from LDORF. */
12904       __IM unsigned int CL_FLAG_DC1P3 : 1;       /*!< [22..22] Powergood signal read for
12905                                           DC 1.3V. */
12906       __IOM unsigned int Reserved2 : 9;          /*!< [31..23] It is recommended to write
12907                                           these bits to 0.                      */
12908     } MCU_FSM_PMU_STATUS_REG_b;
12909   };
12910 
12911   union {
12912     __IOM unsigned int MCU_FSM_PMUX_CTRLS_RET; /*!< (@ 0x00000044) MCU FSM PMUX
12913                                               Controls Retention. */
12914 
12915     struct {
12916       __IOM unsigned int POWER_SW_CTRL_TASS_RAM_IN_RETAIN : 1;     /*!< [0..0] Select value for
12917                                                    TASS RAM Power Mux In
12918                                                    Retention mode    */
12919       __IOM unsigned int POWER_SW_CTRL_M4SS_RAM_IN_RETAIN : 1;     /*!< [1..1] Select value for
12920                                                    M4SS RAM Power Mux In
12921                                                    Retention mode    */
12922       __IOM unsigned int POWER_SW_CTRL_M4ULP_RAM_IN_RETAIN : 2;    /*!< [3..2] Select value for
12923                                                     M4ULP RAM Power Mux In
12924                                                     Retention mode  */
12925       __IOM unsigned int POWER_SW_CTRL_M4ULP_RAM16K_IN_RETAIN : 2; /*!< [5..4] Select value for
12926                                                        M4ULP 16K RAM Power Mux
12927                                                        In Retention mode */
12928       __IOM unsigned int POWER_SW_CTRL_ULPSS_RAM_IN_RETAIN : 2;    /*!< [7..6] Select value for
12929                                                     ULPSS RAM Power Mux In
12930                                                     Retention mode  */
12931       __IOM unsigned int Reserved1 : 24;                           /*!< [31..8] It is recommended to write
12932                                         these bits to 0. */
12933     } MCU_FSM_PMUX_CTRLS_RET_b;
12934   };
12935 
12936   union {
12937     __IOM unsigned int MCU_FSM_TOGGLE_COUNT; /*!< (@ 0x00000048) MCU FSM Toggle Count. */
12938 
12939     struct {
12940       __OM unsigned int TOGGLE_COUNT_RSTART : 1; /*!< [0..0] Start counting GIPO Toggles.   */
12941       __IOM unsigned int Reserved1 : 14;         /*!< [14..1] It is recommended to write
12942                                         these bits to 0. */
12943       __OM unsigned int LATCH_TOGGLE_DATA : 1;   /*!< [15..15] Trigger indication to
12944                                               read GPIO toggle data. */
12945       __IM unsigned int GPIO_TOGGLE_COUNT : 12;  /*!< [27..16] GPIO toogle data count.   */
12946       __IOM unsigned int Reserved2 : 3;          /*!< [30..28] It is recommended to write
12947                                        these bits to 0.                      */
12948       __IM unsigned int TOGGLE_DATA_READY : 1;   /*!< [31..31] GPIO toogle data count. */
12949     } MCU_FSM_TOGGLE_COUNT_b;
12950   };
12951 } MCU_FSM_Type; /*!< Size = 76 (0x4c) */
12952 
12953 /* ===========================================================================================================================
12954  */
12955 /* ================                                     MCU_ProcessSensor
12956  * ================ */
12957 /* ===========================================================================================================================
12958  */
12959 
12960 /**
12961   * @brief The process sensor module, count the process clock (high frequency
12962   ring clock) over one MCU FSM clock and divide this clock by programmable
12963   value. (MCU_ProcessSensor)
12964   */
12965 
12966 typedef struct { /*!< (@ 0x24048540) MCU_ProcessSensor Structure */
12967 
12968   union {
12969     __IOM unsigned int PROCESS_SENSOR_ENABLE_AND_READ; /*!< (@ 0x00000000) Process sensor
12970                                            enable and read for operation */
12971 
12972     struct {
12973       __IOM unsigned int PROCESS_SENSOR_EN : 1; /*!< [0..0] enable or on the process sensor,if
12974                                     this bit is set the sensor enable else
12975                                     sensor is disable. */
12976       __IOM unsigned int PS_RING_CLK_START : 1; /*!< [1..1] Start Ring-Oscillator clock for
12977                                     estimating process corner.         */
12978       __IOM unsigned int PS_CLK_SW_ON : 1;      /*!< [2..2] Clock cleaner on signal to clock cleaner
12979                                block on clock generated by delay chain. */
12980       __IOM unsigned int PS_CLK_SW_OFF : 1;     /*!< [3..3] Clock cleaner off signal to clock
12981                                 cleaner block on clock
12982                                           generated by delay chain. */
12983       __IOM unsigned int NUM_CYCLES : 2;        /*!< [5..4] Number of MCU FSM clock(32KHz)for which
12984                              measurement need to be done.if bits is 1 then 1
12985                              clock, 2 then 2 clocks,3 then 3 clocks,4 then 4
12986                              clocks. */
12987       __IM unsigned int PS_MEAS_DONE_SYNC : 1;  /*!< [6..6] Processor sensor
12988                                               measurement done. */
12989       __IOM unsigned int RESERVED1 : 9;         /*!< [15..7] Reserved1        */
12990       __IM unsigned int PS_COUNT : 16;          /*!< [31..16] Processor sensor read back */
12991     } PROCESS_SENSOR_ENABLE_AND_READ_b;
12992   };
12993 } MCU_ProcessSensor_Type; /*!< Size = 4 (0x4) */
12994 
12995 /* ===========================================================================================================================
12996  */
12997 /* ================                                          MCU_RET
12998  * ================ */
12999 /* ===========================================================================================================================
13000  */
13001 
13002 /**
13003   * @brief NPSS has Retention domain logic which is a power  domain .
13004                This domain consisted all logic which will turned off if none of
13005   the  M4 memories are retained. (MCU_RET)
13006   */
13007 
13008 typedef struct { /*!< (@ 0x24048600) MCU_RET Structure */
13009 
13010   union {
13011     __IOM unsigned int MCURET_QSPI_WR_OP_DIS; /*!< (@ 0x00000000) MCURET QSPI WR OP DIS */
13012 
13013     struct {
13014       __IOM unsigned int M4SS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [0..0] M4SS Write operation
13015                                                disable to Flash. 1 - Write
13016                                                Operation to Flash is not
13017                                                allowed. 0 - Write Operation to
13018                                                Flash is allowed. */
13019       __IM unsigned int TASS_QSPI_WRSR_WR_OP_DISABLE : 1;  /*!< [1..1] TASS Write operation
13020                                                disable to Flash. 1 - Write
13021                                                Operation to Flash is not
13022                                                allowed. 0 - Write Operation to
13023                                                Flash is allowed. */
13024       __IOM unsigned int RESERVED1 : 30;                   /*!< [31..2] Reserved1        */
13025     } MCURET_QSPI_WR_OP_DIS_b;
13026   };
13027 
13028   union {
13029     __IM unsigned int MCURET_BOOTSTATUS; /*!< (@ 0x00000004) MCURET BOOT Status */
13030 
13031     struct {
13032       __IM unsigned int BOOT_STATUS : 1; /*!< [0..0] Boot Status/Configuration
13033                                         information to MCU */
13034       __IM unsigned int RESERVED1 : 31;  /*!< [31..1] Reserved1  */
13035     } MCURET_BOOTSTATUS_b;
13036   };
13037   __IM unsigned int RESERVED;
13038 
13039   union {
13040     __IM unsigned int CHIP_CONFIG_MCU_READ; /*!< (@ 0x0000000C) MCURET BOOT Status */
13041 
13042     struct {
13043       __IM unsigned int DISABLE_M4 : 1;                       /*!< [0..0] When set, disables the M4 by
13044                                        clock gating and putting M4 in reset */
13045       __IM unsigned int LIMIT_M4_FREQ_110MHZ_b : 1;           /*!< [1..1] When set, limits the M4SS SoC
13046                                          clock to Max clock/2                 */
13047       __IM unsigned int DISABLE_M4_ULP_MODE : 1;              /*!< [2..2] When set, limits the M4SS SoC
13048                                       clock to Max clock/2                 */
13049       __IM unsigned int RESERVED1 : 7;                        /*!< [9..3] Reserved1 */
13050       __IM unsigned int M4_FLASH_SIZE : 3;                    /*!< [12..10] 0xx - Unrestricted 100 - Auto mode
13051                                 accesses to flash are restricted to 4 MBit 101 -
13052                                 Auto mode accesses to flash are restricted to 8
13053                                 MBit 110 - Auto mode accesses to flash are
13054                                 restricted to 16 MBit 111 - Auto mode accesses
13055                                 to flash are restricted to 32 MBit */
13056       __IM unsigned int DISABLE_FIM_COP : 1;                  /*!< [13..13] When set, disable FIMV         */
13057       __IM unsigned int DISABLE_VAP : 1;                      /*!< [14..14] When set, disables VAD   */
13058       __IM unsigned int DISABLE_TOUCH : 1;                    /*!< [15..15] When set, disables touch
13059                                           interface */
13060       __IM unsigned int RESERVED2 : 1;                        /*!< [16..16] Reserved2     */
13061       __IM unsigned int DISABLE_ANALOG_PERIPH : 1;            /*!< [17..17] When set, disables
13062                                                   analog peripherals */
13063       __IM unsigned int DISABLE_JTAG : 1;                     /*!< [18..18] When set, disable JTAG
13064                                          interface(both M4 and NWP) */
13065       __IM unsigned int DISABLE_M4SS_KH_ACCESS : 1;           /*!< [19..19] When set, disables
13066                                                    access to key in the key
13067                                                    holder from M4SS QSPI */
13068       __IM unsigned int DISABLE_M4SS_ACCESS_FRM_TASS_SEC : 1; /*!< [20..20] When set, M4 can
13069                                                    not access TASS memory or
13070                                                    registers except for host
13071                                                    communication registers */
13072       __IM unsigned int RESERVED3 : 11;                       /*!< [31..21] Reserved3             */
13073     } CHIP_CONFIG_MCU_READ_b;
13074   };
13075 
13076   union {
13077     __IOM unsigned int MCUAON_CTRL_REG4; /*!< (@ 0x00000010) MCURET Control Register4 */
13078 
13079     struct {
13080       __IOM unsigned int RESERVED1 : 16;                   /*!< [15..0] Reserved1 */
13081       __IOM unsigned int ULP_GPIO_2_TEST_MODE_OUT_SEL : 4; /*!< [19..16] NPSS Test modes */
13082       __IOM unsigned int ULP_GPIO_1_TEST_MODE_OUT_SEL : 4; /*!< [23..20] NPSS Test modes */
13083       __IOM unsigned int ULP_GPIO_0_TEST_MODE_OUT_SEL : 4; /*!< [27..24] NPSS Test modes */
13084       __IOM unsigned int ULP_GPIOS_IN_TEST_MODE : 1;       /*!< [28..28] NPSS Test modes */
13085       __IOM unsigned int RESERVED2 : 3;                    /*!< [31..29] Reserved2   */
13086     } MCUAON_CTRL_REG4_b;
13087   };
13088   __IM unsigned int RESERVED1[2];
13089   __IOM MCU_RET_NPSS_GPIO_CNTRL_Type NPSS_GPIO_CNTRL[5]; /*!< (@ 0x0000001C) [0..4] */
13090 } MCU_RET_Type;                                          /*!< Size = 48 (0x30)           */
13091 
13092 /* ===========================================================================================================================
13093  */
13094 /* ================                                         MCU_TEMP
13095  * ================ */
13096 /* ===========================================================================================================================
13097  */
13098 
13099 /**
13100   * @brief The temperature sensor is used to read the temperature by using APB
13101   registers, which is access through direct to ULPSS system. (MCU_TEMP)
13102   */
13103 
13104 typedef struct { /*!< (@ 0x24048500) MCU_TEMP Structure */
13105 
13106   union {
13107     __IOM unsigned int TS_ENABLE_AND_TEMPERATURE_DONE; /*!< (@ 0x00000000) Temperature sensor
13108                                            enable and measurement calculation
13109                                                                       done
13110                                            indication register */
13111 
13112     struct {
13113       __OM unsigned int TEMP_SENS_EN : 1;          /*!< [0..0] Temperature sensing
13114                                          enable,self clearing register */
13115       __IOM unsigned int REF_CLK_SEL : 1;          /*!< [1..1] if this bit is zero then reference RO
13116                               clock from analog,else this bit is one then MCU
13117                               FSM clock */
13118       __IOM unsigned int CONT_COUNT_FREEZE : 10;   /*!< [11..2] Count of reference clock on which
13119                                      ptat clock counts               */
13120       __IM unsigned int TEMP_MEASUREMENT_DONE : 1; /*!< [12..12] temperature measurement done
13121                                         indication.                         */
13122       __IOM unsigned int RESERVED1 : 19;           /*!< [31..13] reserved1 */
13123     } TS_ENABLE_AND_TEMPERATURE_DONE_b;
13124   };
13125 
13126   union {
13127     __IOM unsigned int TS_SLOPE_SET; /*!< (@ 0x00000004) temperature sensor slope set(slope
13128                          will be change with respect to temperature change) */
13129 
13130     struct {
13131       __IOM unsigned int SLOPE : 10;           /*!< [9..0] This is one time measurement for one package
13132                          after chip arrives from fab,this is signed bit. */
13133       __IOM unsigned int RESERVED1 : 6;        /*!< [15..10] Reserved1        */
13134       __IOM unsigned int TEMPERATURE_SPI : 11; /*!< [26..16] temperature known */
13135       __OM unsigned int TEMP_UPDATED : 1;      /*!< [27..27] temperature updated signal for the reg
13136                                to capture this temperature. */
13137       __IOM unsigned int BJT_BASED_TEMP : 1;   /*!< [28..28] Temperature is updated through which
13138                                  is calculated using bjt based if bit is high(1)
13139                                  through spi and bit is low(0) then through
13140                                  calculation RO based */
13141       __IOM unsigned int RESERVED2 : 3;        /*!< [31..29] Reserved2 */
13142     } TS_SLOPE_SET_b;
13143   };
13144 
13145   union {
13146     __IOM unsigned int TS_FE_COUNTS_NOMINAL_SETTINGS; /*!< (@ 0x00000008) determine
13147                                                      calibrated temperature */
13148 
13149     struct {
13150       __IOM unsigned int F2_NOMINAL : 10;         /*!< [9..0] ptat clock count during calibration,This
13151                               will vary with chip to chip. */
13152       __IOM unsigned int RESERVED1 : 6;           /*!< [15..10] Reserved1 */
13153       __IOM unsigned int NOMINAL_TEMPERATURE : 7; /*!< [22..16] calibrated temperature  */
13154       __IOM unsigned int RESERVED2 : 9;           /*!< [31..23] Reserved2 */
13155     } TS_FE_COUNTS_NOMINAL_SETTINGS_b;
13156   };
13157 
13158   union {
13159     __IM unsigned int TS_COUNTS_READ; /*!< (@ 0x0000000C) temperature sensor count read. */
13160 
13161     struct {
13162       __IM unsigned int COUNT_F2 : 10; /*!< [9..0] COUNT_F2 */
13163       __IM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */
13164       __IM unsigned int COUNT_F1 : 10; /*!< [25..16] COUNT_F1 */
13165       __IM unsigned int RESERVED2 : 6; /*!< [31..26] Reserved2 */
13166     } TS_COUNTS_READ_b;
13167   };
13168 
13169   union {
13170     __IOM unsigned int TEMPERATURE_READ; /*!< (@ 0x00000010) read the temperature */
13171 
13172     struct {
13173       __IM unsigned int TEMPERATURE_RD : 11; /*!< [10..0] Temperature value for read
13174                                             in signed format */
13175       __IOM unsigned int RES10 : 21;         /*!< [31..11] reserved10         */
13176     } TEMPERATURE_READ_b;
13177   };
13178 } MCU_TEMP_Type; /*!< Size = 20 (0x14) */
13179 
13180 /* ===========================================================================================================================
13181  */
13182 /* ================                                          MCU_AON
13183  * ================ */
13184 /* ===========================================================================================================================
13185  */
13186 
13187 /**
13188   * @brief NPSS has always ON domain logic which is not power gatable  Which
13189   consistes of power, reset, isolation controls for different power domains in
13190   NPSS. (MCU_AON)
13191   */
13192 
13193 typedef struct { /*!< (@ 0x24048000) MCU_AON Structure */
13194 
13195   union {
13196     __IOM unsigned int MCUAON_NPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000000) This register used for
13197                                         NPSS power control set register. */
13198 
13199     struct {
13200       __IOM unsigned int RES : 1;                            /*!< [0..0] bit is reserved */
13201       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery
13202                                                  FF's power gate enable.If
13203                                                  set,Power
13204                                                        Supply is On clearing
13205                                                  this bit has no effect. */
13206       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1;  /*!< [2..2] MCU FSM power gate
13207                                                 enable,If set power supply is on
13208                                                 clearing
13209                                                        this bit has no effect.
13210                                               */
13211       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1;  /*!< [3..3] MCU RTC power gate
13212                                                 enable if set,power supply is on
13213                                                 clearing
13214                                                        this bit has no effect.
13215                                               */
13216       __IOM
13217       unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power
13218                                                          gate enable if
13219                                                          set,power supply is on
13220                                                          clearing this bit has
13221                                                          no effect */
13222       __IOM
13223       unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1;                 /*!< [5..5] MCU PS power gate
13224                                                    enable.if set,power supply is
13225                                                    on clearing this bit has no
13226                                                    effect. */
13227       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1;           /*!< [6..6] MCU temperature sensor
13228                                                power gate enable if set,power
13229                                                        supply is on.clearing
13230                                                this bit has no effect */
13231       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1;       /*!< [7..7] MCU Storage 1 power
13232                                                    gate enable for 64-bit.if
13233                                                    set,power supply is
13234                                                    on,clearing this bit has no
13235                                                    effect. */
13236       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1;       /*!< [8..8] MCU Storage 2 power
13237                                                    gate enable for 64-bit.if
13238                                                    set,power supply is
13239                                                    on,clearing this bit has no
13240                                                    effect. */
13241       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1;       /*!< [9..9] MCU Storage 3 power
13242                                                    gate enable for 64-bit.if
13243                                                    set,power supply is
13244                                                    on,clearing this bit has no
13245                                                    effect. */
13246       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1;      /*!< [10..10] TIMEPERIOD power
13247                                                     gate enable. */
13248       __IOM unsigned int RESERVED1 : 5;                              /*!< [15..11] reserved1              */
13249       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU
13250                                                          control power gate
13251                                                          enable             */
13252       __IOM unsigned int RESERVED2 : 15;                             /*!< [31..17] reserved2                  */
13253     } MCUAON_NPSS_PWRCTRL_SET_REG_b;
13254   };
13255 
13256   union {
13257     __IOM unsigned int MCUAON_NPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000004) This register used
13258                                           for NPSS power control clear
13259                                                          register. */
13260 
13261     struct {
13262       __IOM unsigned int RES : 1;                                    /*!< [0..0] bit is reserved */
13263       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1;         /*!< [1..1] MCU domain battery
13264                                                  FF's power gate enable.If
13265                                                  set,Power Supply is OFF
13266                                                  clearing this bit has no
13267                                                  effect. */
13268       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1;          /*!< [2..2] MCU FSM power gate
13269                                                 enable,If set power supply is
13270                                                 OFF clearing this bit has no
13271                                                 effect. */
13272       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1;          /*!< [3..3] MCU RTC power gate
13273                                                 enable if set,power supply is
13274                                                 OFF clearing this bit has no
13275                                                 effect. */
13276       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1;          /*!< [4..4] MCU WDT power gate
13277                                                 enable if set,power supply is
13278                                                 OFF clearing this bit has no
13279                                                 effect */
13280       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1;           /*!< [5..5] MCU PS power gate
13281                                                enable.if set,power supply is OFF
13282                                                clearing
13283                                                        this bit has no effect.
13284                                              */
13285       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1;           /*!< [6..6] MCU temperature sensor
13286                                                power gate enable if set,power
13287                                                        supply is OFF.clearing
13288                                                this bit has no effect */
13289       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1;       /*!< [7..7] MCU Storage 1 power
13290                                                    gate enable for 64-bit.if
13291                                                    set,power supply is
13292                                                    OFF,clearing this bit has no
13293                                                    effect. */
13294       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1;       /*!< [8..8] MCU Storage 2 power
13295                                                    gate enable for 64-bit.if
13296                                                    set,power supply is
13297                                                    OFF,clearing this bit has no
13298                                                    effect. */
13299       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1;       /*!< [9..9] MCU Storage 3 power
13300                                                    gate enable for 64-bit.if
13301                                                    set,power supply is
13302                                                    OFF,clearing this bit has no
13303                                                    effect. */
13304       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1;      /*!< [10..10] TIMEPERIOD power
13305                                                     gate enable. */
13306       __IOM unsigned int RESERVED1 : 5;                              /*!< [15..11] reserved1              */
13307       __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU
13308                                                          control power gate
13309                                                          enable             */
13310       __IOM unsigned int RESERVED2 : 15;                             /*!< [31..17] reserved2                  */
13311     } MCUAON_NPSS_PWRCTRL_CLEAR_REG_b;
13312   };
13313   __IM unsigned int RESERVED;
13314 
13315   union {
13316     __IOM unsigned int MCUAON_IPMU_RESET_CTRL; /*!< (@ 0x0000000C) This register used for ipmu
13317                                    reset control register         */
13318 
13319     struct {
13320       __IOM unsigned int ULP_ANALOG_SPI_RESET_N : 1; /*!< [0..0] ULP Analog SPI Reset Signal,
13321                                          if bit is 1 then outoff reset,else in
13322                                          reset */
13323       __IOM unsigned int IPMU_SPI_RESET_N : 1;       /*!< [1..1] IPMU SPI Reset Signal,if bit is 1
13324                                    then outoff reset,else in reset */
13325       __IOM unsigned int RESERVED1 : 30;             /*!< [31..2] reserved1 */
13326     } MCUAON_IPMU_RESET_CTRL_b;
13327   };
13328 
13329   union {
13330     __IOM unsigned int MCUAON_SHELF_MODE; /*!< (@ 0x00000010) This register used for
13331                                          control shelf mode.                 */
13332 
13333     struct {
13334       __OM unsigned int ENTER_SHELF_MODE : 16;        /*!< [15..0] Program 0xAAAA for
13335                                                   entering shelf mode.     */
13336       __IOM unsigned int SHUTDOWN_WAKEUP_MODE : 2;    /*!< [17..16] GPIO based wakeup
13337                                                   mode configuration. */
13338       __IOM unsigned int SHELF_MODE_GPIOBASED : 1;    /*!< [18..18] GPIO based shelf mode
13339                                        entering,If set 1 by processor, On
13340                                        Falling edge of GPIO (Based on the option
13341                                        used in shutdown_wakeup_mode register)
13342                                        chip will enter Shelf mode. */
13343       __IOM unsigned int SHELF_MODE_WAKEUP_DELAY : 3; /*!< [21..19] Programmable delay for
13344                                           resetting Chip during exit phase of
13345                                           shelf mode. */
13346       __IOM unsigned int RESERVED1 : 10;              /*!< [31..22] reserved1   */
13347     } MCUAON_SHELF_MODE_b;
13348   };
13349 
13350   union {
13351     __IOM unsigned int MCUAON_GEN_CTRLS; /*!< (@ 0x00000014) This register used for
13352                                         MCUON gen control mode.             */
13353 
13354     struct {
13355       __IOM unsigned int XTAL_CLK_FROM_GPIO : 1;       /*!< [0..0] Select external 32KHz clock from
13356                                     NPSS GPIO's,if bit is 1 then select XTAL
13357                                     clock from GPIO Pins.  Please refer to NPSS
13358                                     GPIO Pin muxing for configuration.else
13359                                     select XTAL clock from IPMU clock sources.
13360                                   */
13361       __IOM unsigned int ULP_ANALOG_WAKEUP_ACCESS : 1; /*!< [1..1] ULP analog wakeup Source
13362                                           Access,if bit is 1 then TASS
13363                                           else bit is 0 then M4SS. */
13364       __IOM unsigned int RES : 14;                     /*!< [15..2] reser          */
13365       __IOM unsigned int ENABLE_PDO : 1;               /*!< [16..16] Enable turning Off POD power
13366                                         domain when SOC_LDO EN is low,When Set
13367                                         to 1, Up on SoC LDO Enable going low, IO
13368                                                      supply (3.3v)to SOC Pads
13369                                         will be tuned-off. */
13370       __IOM unsigned int NPSS_SUPPLY_0P9 : 1;          /*!< [17..17] keep npss supply always at 0.9V,if
13371                                   bit is 1 then npss supply always at 0.9V else
13372                                   bit is zero then npss supply will switch from
13373                                   0.6V to 0.9V  based on high frequency
13374                                           enables. */
13375       __IOM unsigned int RESERVED1 : 14;               /*!< [31..18] reser */
13376     } MCUAON_GEN_CTRLS_b;
13377   };
13378 
13379   union {
13380     __IOM unsigned int MCUAON_PDO_CTRLS; /*!< (@ 0x00000018) This register used for
13381                                         MCUON PDO control mode.             */
13382 
13383     struct {
13384       __IOM
13385       unsigned int SOC_B_IO_DOMAIN_EN_B : 1;       /*!< [0..0] Turn-Off IO supply of SOC
13386                                            domain on bottom side,if bit is 1
13387                                            then turn-off and 0 then turn on */
13388       __IOM unsigned int SOC_L_IO_DOMAIN_EN_B : 1; /*!< [1..1] Turn-Off IO supply of SOC domain
13389                                        on left side,if bit is 1  then turn-off
13390                                        and 0 then turn on */
13391       __IOM unsigned int SOC_T_IO_DOMAIN_EN_B : 1; /*!< [2..2] Turn-Off IO supply of SOC domain
13392                                        on top side,if bit is 1  then turn-off
13393                                        and 0 then turn on */
13394       __IOM unsigned int QSPI_IO_DOMAIN_EN_B : 1;  /*!< [3..3] Turn-Off IO supply of QSPI
13395                                       domain,if bit is 1 then  turn-off and 0
13396                                       then turn on */
13397       __IOM unsigned int SDIO_IO_DOMAIN_EN_B : 1;  /*!< [4..4] Turn-Off IO supply of SDIO
13398                                       domain.,if bit is 1 then turn-off and 0
13399                                       then turn on */
13400       __IOM unsigned int RES : 27;                 /*!< [31..5] reser     */
13401     } MCUAON_PDO_CTRLS_b;
13402   };
13403 
13404   union {
13405     __IOM unsigned int MCUAON_WDT_CHIP_RST; /*!< (@ 0x0000001C) This register used
13406                                            for wdt chip reset purpose. */
13407 
13408     struct {
13409       __IOM unsigned int MCU_WDT_BASED_CHIP_RESET : 1; /*!< [0..0] When cleared, Up on host
13410                                           reset request.Power-On Reset (POR)
13411                                           will be generated */
13412       __IOM unsigned int RESERVED1 : 31;               /*!< [31..1] reserved1    */
13413     } MCUAON_WDT_CHIP_RST_b;
13414   };
13415 
13416   union {
13417     __IOM unsigned int MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS; /*!< (@ 0x00000020) This register
13418                                                 used for khz clock select and
13419                                                 reset status */
13420 
13421     struct {
13422       __IOM unsigned int AON_KHZ_CLK_SEL : 3;               /*!< [2..0] NPSS AON KHz clock selection,if 001
13423                                   Khz RO clock select,else
13424                                           if 010 - Khz RC clock select,else 100
13425                                   Khz Xtal clock select               */
13426       __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED : 1; /*!< [3..3] If Khz clock mux
13427                                                  select is modified,please poll
13428                                                  this bit and wait  till it
13429                                                  becomes one. */
13430 
13431 #if defined(SLI_SI917B0) || defined(SLI_SI915)
13432       __IOM unsigned int AON_KHZ_CLK_SEL_WWD : 4;                  /* [4 .. 7] NPSS AON KHz clock
13433                                                  selection for WWD */
13434       __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED_WWD : 1;    /*!< [8..8] If Khz clock mux
13435                                                      select is modified for
13436                                                      wwd,please poll this bit
13437                                                      and wait  till it becomes
13438                                                      one. */
13439       __IOM unsigned int AON_KHZ_CLK_SEL_SYSRTC : 4;               /* [9 .. 12] NPSS AON KHz clock
13440                                                     selection for SYSRTC */
13441       __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED_SYSRTC : 1; /*!< [13..13] If Khz clock
13442                                                         mux select is modified
13443                                                         for sysrtc,please poll
13444                                                         this
13445                                                                        bit and
13446                                                         wait  till it becomes
13447                                                         one. */
13448       __IOM unsigned int RES : 2;                                  /*!< [14..15] reserved */
13449 #else
13450       __IOM unsigned int RES : 12;                     /*!< [15..4] reser       */
13451 #endif
13452 
13453       __IOM unsigned int MCU_FIRST_POWERUP_POR : 1;     /*!< [16..16] Program this bit to '1' upon
13454                                         power_up.It will be clear when Vbatt
13455                                         power is removed */
13456       __IOM unsigned int MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Program this bit to '1'
13457                                             upon power_up,It will be clear
13458                                                        when reset pin is pulled
13459                                             low. */
13460 #if defined(SLI_SI917B0) || defined(SLI_SI915)
13461       __IOM unsigned int SYSRTC_32KHZ_RC_CLK_DIV_FACTOR : 6; /* [18..23] Clock division factor
13462                                                  for 32Khz_rc_clk (Used in
13463                                                  SYSRTC and MCU WWD) */
13464       __IOM unsigned int RESERVED1 : 8;                      /*!< [24..31] reserved1 */
13465 #else
13466       __IOM unsigned int RESERVED1 : 14;               /*!< [31..18] reserved1 */
13467 #endif
13468     } MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b;
13469   };
13470 } MCU_AON_Type; /*!< Size = 36 (0x24) */
13471 
13472 /* ===========================================================================================================================
13473  */
13474 /* ================                                          ULPCLK
13475  * ================ */
13476 /* ===========================================================================================================================
13477  */
13478 
13479 /**
13480   * @brief This block provides programming support for miscellaneous blocks in
13481   the chip. Various features in the chip are enabled using this. (ULPCLK)
13482   */
13483 
13484 typedef struct { /*!< (@ 0x24041400) ULPCLK Structure */
13485 
13486   union {
13487     __IOM unsigned int ULP_MISC_SOFT_SET_REG; /*!< (@ 0x00000000) ULP MISC soft
13488                                              register set. */
13489 
13490     struct {
13491       __IOM unsigned int PCM_ENABLE_b : 1;                  /*!< [0..0] Used in pcm      */
13492       __IOM unsigned int PCM_FSYNC_START_b : 1;             /*!< [1..1] Used in pcm */
13493       __IOM unsigned int BIT_RES : 2;                       /*!< [3..2] Used in pcm           */
13494       __IOM unsigned int IR_PCLK_EN_b : 1;                  /*!< [4..4] Static clock enable for IR
13495                                           APB Interface */
13496       __IOM unsigned int PCLK_ENABLE_I2C_b : 1;             /*!< [5..5] This bit is used as Static enable
13497                                     for APB clock to I2C module,if bit is zero
13498                                     then clock is disabled else bit is
13499                                           one then clock is enabled. */
13500       __IOM unsigned int CLK_ENABLE_I2S_b : 1;              /*!< [6..6] This bit is used to enable clock to
13501                                    I2S module if bit is set(1)then clock is
13502                                    enabled is bit is zero then clock disabled.
13503                                  */
13504       __IOM unsigned int PCLK_ENABLE_SSI_MASTER_b : 1;      /*!< [7..7] This bit is used to enable
13505                                            APB bus clock to SSI master,if bit is
13506                                            zero clock  will be available only
13507                                            when the request from the module is
13508                                            present.else bit  is one then clock
13509                                                        is enabled. */
13510       __IOM unsigned int SCLK_ENABLE_SSI_MASTER_b : 1;      /*!< [8..8] This bit is used to enable
13511                                           clock serial clock to SSI master,if
13512                                           bit is zero clock  will be available
13513                                           only when the request from the module
13514                                           is present.else bit  is one
13515                                           then clock is enabled. */
13516       __IOM unsigned int PCLK_ENABLE_UART_b : 1;            /*!< [9..9] This bit is used to enable
13517                                      peripheral bus clock to UART4,if bit zero
13518                                      then clock will be available only when the
13519                                      request from the module is present or a
13520                                      transaction is pending
13521                                           on the APB bus,else bit is one then
13522                                      clock is enabled.                     */
13523       __IOM unsigned int SCLK_ENABLE_UART_b : 1;            /*!< [10..10] This bit is used to enable
13524                                      asynchronous serial clock to UART4,if bit
13525                                      is zero clock  will be available only when
13526                                           the request from the module is
13527                                      present.else bit  is one then clock is
13528                                      enabled. */
13529       __IOM unsigned int FIM_PCLK_ENABLE_b : 1;             /*!< [11..11] This bit is used to enable clock
13530                                     to FIM reg file,if this bit is zero then
13531                                     clock will be available only when the
13532                                     request from the module is present  else bit
13533                                     is set(1)then clock is enabled. */
13534       __IOM unsigned int VAD_PCLK_ENABLE_b : 1;             /*!< [12..12] This bit is used to enable clock
13535                                     to FIM reg file,if this bit is zero then
13536                                     clock will be available only when the
13537                                     request from the module is present  else bit
13538                                     is set(1)then clock is enabled. */
13539       __IOM unsigned int CLK_ENABLE_TIMER_b : 1;            /*!< [13..13] This bit is used to enable clock
13540                                      to Timer,if this bit is zero then clock
13541                                      will be available only when the request
13542                                           from the module is present  else bit
13543                                      is set(1)then clock is enabled. */
13544       __IOM unsigned int EGPIO_CLK_EN_b : 1;                /*!< [14..14] This bit is used to enable clock to
13545                                  gpio,if this bit is zero then clock will be
13546                                  available only when the request from the module
13547                                  is present  else bit is set(1)then clock is
13548                                  enabled. */
13549       __IOM unsigned int REG_ACCESS_SPI_CLK_EN_b : 1;       /*!< [15..15] This bit is used to enable
13550                                           clock to register access spi,if this
13551                                           bit is zero then clock will be
13552                                           available only when the request from
13553                                           the module is present  else bit is
13554                                           set(1)then clock is enabled. */
13555       __IOM unsigned int FIM_CLK_EN_b : 1;                  /*!< [16..16] This bit is used to enable clock to
13556                                FIM module,if this bit is zero then clock will be
13557                                gated,else bit is one then clock is enabled. */
13558       __IOM unsigned int VAD_CLK_EN_b : 1;                  /*!< [17..17] This bit is used to enable clock to
13559                                vad module,if this bit is zero then clock will be
13560                                gated,else bit is one then clock is enabled. */
13561       __IOM unsigned int CLK_ENABLE_ULP_MEMORIES_b : 1;     /*!< [18..18] This bit is used to
13562                                           enable clock to memories,if this bit
13563                                           is zero then clock will be available
13564                                           only when the request from the module
13565                                           is present  else bit is set(1)then
13566                                           clock is enabled. */
13567       __IOM unsigned int EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] This bit is used to
13568                                                disable dynamic clock gating on
13569                                                APB clock to egpio */
13570       __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1;           /*!< [20..20] This bit is used to enable
13571                                      static clock to egpio APB interface */
13572       __IOM unsigned int TIMER_PCLK_EN_b : 1;               /*!< [21..21] This bit is used to enable static
13573                                  clock to Timer APB Interface */
13574       __IOM unsigned int AUX_ULP_EXT_TRIG_1_SEL_b : 1;      /*!< [22..22] aux adc dac controller
13575                                           external trigger2 mux select, to
13576                                           choose between  ulp gpio aux ext
13577                                           trigger2 and timer interrupt. */
13578       __IOM unsigned int AUX_ULP_EXT_TRIG_2_SEL_b : 1;      /*!< [23..23] aux adc dac controller
13579                                           external trigger2 mux select, to
13580                                           choose between ulp  gpio aux ext
13581                                           trigger2 and timer interrupt. */
13582       __IOM unsigned int AUX_SOC_EXT_TRIG_1_SEL_b : 1;      /*!< [24..24] aux adc dac controller
13583                                           external trigger3 mux select, to
13584                                           choose between soc aux  ext
13585                                           trigger1and soc aux ext trigger3. */
13586       __IOM unsigned int AUX_SOC_EXT_TRIG_2_SEL_b : 1;      /*!< [25..25] aux adc dac controller
13587                                           external trigger4 mux select, to
13588                                           choose between soc aux ext trigger2and
13589                                           soc aux ext trigger4.           */
13590       __IOM unsigned int ULPSS_M4SS_SLV_SEL_b : 1;          /*!< [26..26] select slave */
13591       __IOM unsigned int ULPSS_TASS_QUASI_SYNC_b : 1;       /*!< [27..27] TASS quasi sync         */
13592       __IOM unsigned int RESERVED1 : 2;                     /*!< [29..28] reserved1            */
13593       __IOM unsigned int FIM_AHB_CLK_ENABLE_b : 1;          /*!< [30..30] static clock enable
13594                                                   for FIM AHB interface */
13595       __IOM unsigned int TOUCH_SENSOR_PCLK_ENABLE_b : 1;    /*!< [31..31] Static clock enable for
13596                                              touch APB interface */
13597     } ULP_MISC_SOFT_SET_REG_b;
13598   };
13599 
13600   union {
13601     __IOM unsigned int ULP_TA_PERI_ISO_REG; /*!< (@ 0x00000004) ULP NWP isolation register. */
13602 
13603     struct {
13604       __IOM unsigned int UDMA_ISO_CNTRL_b : 1;      /*!< [0..0] UDMA module isolation enable,if bit
13605                                    is set(1) then enable else bit is zero then
13606                                    disable. */
13607       __IOM unsigned int IR_ISO_CNTRL_b : 1;        /*!< [1..1] IR module isolation enable,if bit is
13608                                  set(1) then enable else bit is zero then
13609                                  disable. */
13610       __IOM unsigned int I2C_ISO_CNTRL_b : 1;       /*!< [2..2] I2C module isolation enable,if bit is
13611                                   set(1) then enable else bit is zero then
13612                                   disable. */
13613       __IOM unsigned int I2S_ISO_CNTRL_b : 1;       /*!< [3..3] I2S module isolation enable,if bit is
13614                                   set(1) then enable else bit is zero then
13615                                   disable. */
13616       __IOM unsigned int SSI_ISO_CNTRL_b : 1;       /*!< [4..4] SSI module isolation enable ,if bit
13617                                   is set(1) then enable else bit is zero then
13618                                   disable. */
13619       __IOM unsigned int UART_ISO_CNTRL_b : 1;      /*!< [5..5] UART module isolation enable,if bit
13620                                    is set(1) then enable else bit is zero then
13621                                    disable. */
13622       __IOM unsigned int AUX_A2D_ISO_CNTRL_b : 1;   /*!< [6..6] AUX a2d module isolation
13623                                       enable,if bit is set(1) then enable else
13624                                       bit is zero then disable. */
13625       __IOM unsigned int VAD_ISO_CNTRL_b : 1;       /*!< [7..7] VAD module isolation enable,if bit is
13626                                   set(1) then enable else bit is zero then
13627                                   disable. */
13628       __IOM unsigned int TOUCH_ISO_CNTRL_b : 1;     /*!< [8..8] CAP sensor module isolation
13629                                     enable,if bit is set(1) then
13630                                       enable else bit is zero then disable. */
13631       __IOM unsigned int PROC_MISC_ISO_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore,
13632                                         interrupt cntrl, Timer) module isolation
13633                                         enable ,if bit is set(1) then enable
13634                                         else bit is zero then disable. */
13635       __IOM unsigned int RESERVED0 : 1;             /*!< [10..10] reserved0  */
13636       __IOM unsigned int RESERVED1 : 1;             /*!< [11..11] reserved1  */
13637       __IOM unsigned int RESERVED2 : 1;             /*!< [12..12] reserved2  */
13638       __IOM unsigned int RESERVED3 : 1;             /*!< [13..13] reserved3  */
13639       __IOM unsigned int FIM_ISO_CNTRL_b : 1;       /*!< [14..14] FIM module isolation enable ,if bit
13640                                   is set(1) then enable else bit is zero then
13641                                   disable. */
13642       __IOM unsigned int MEM_2K_1_ISO_CNTRL_b : 1;  /*!< [15..15] 2k SRAM memory isolation
13643                                        enable ,if bit is set(1) then
13644                                           enable else bit is zero then disable.
13645                                      */
13646       __IOM unsigned int MEM_2K_2_ISO_CNTRL_b : 1;  /*!< [16..16] 2k SRAM memory isolation
13647                                        enable ,if bit is set(1) then
13648                                           enable else bit is zero then disable.
13649                                      */
13650       __IOM unsigned int MEM_2K_3_ISO_CNTRL_b : 1;  /*!< [17..17] 2k SRAM memory isolation
13651                                        enable ,if bit is set(1) then
13652                                           enable else bit is zero then disable.
13653                                      */
13654       __IOM unsigned int MEM_2K_4_ISO_CNTRL_b : 1;  /*!< [18..18] 2k SRAM memory isolation
13655                                         enable ,if bit is set(1) then
13656                                            enable else bit is zero then disable.
13657                                       */
13658       __IOM unsigned int RESERVED4 : 13;            /*!< [31..19] reserved4 */
13659     } ULP_TA_PERI_ISO_REG_b;
13660   };
13661 
13662   union {
13663     __IOM unsigned int ULP_TA_PERI_RESET_REG; /*!< (@ 0x00000008) ULP NWP peri reset
13664                                              register. */
13665 
13666     struct {
13667       __IOM unsigned int UDMA_SOFT_RESET_CNTRL_b : 1;      /*!< [0..0] UDMA module soft reset
13668                                           enable,if bit is set(1) then out of
13669                                           soft reset else bit is zero then in
13670                                           reset.                             */
13671       __IOM unsigned int IR_SOFT_RESET_CNTRL_b : 1;        /*!< [1..1] IR module soft reset enable,if
13672                                         bit is set(1) then out of soft reset
13673                                         else bit is zero then in reset. */
13674       __IOM unsigned int I2C_SOFT_RESET_CNTRL_b : 1;       /*!< [2..2] I2C module soft reset enable
13675                                          ,if bit is set(1) then out of soft
13676                                          reset else bit is zero then in reset.
13677                                        */
13678       __IOM unsigned int I2S_SOFT_RESET_CNTRL_b : 1;       /*!< [3..3] I2S module soft reset enable
13679                                          ,if bit is set(1) then out of soft
13680                                          reset else bit is zero then in reset.
13681                                        */
13682       __IOM unsigned int SSI_SOFT_RESET_CNTRL_b : 1;       /*!< [4..4] SSI module soft reset enable
13683                                          ,if bit is set(1) then out of soft
13684                                          reset else bit is zero then in reset.
13685                                        */
13686       __IOM unsigned int UART_SOFT_RESET_CNTRL_b : 1;      /*!< [5..5] UART module soft reset enable
13687                                           ,if bit is set(1) then out of soft
13688                                           reset else bit is zero then in reset.
13689                                         */
13690       __IOM unsigned int AUX_A2D_SOFT_RESET_CNTRL_b : 1;   /*!< [6..6] AUX a2d module soft reset
13691                                           enable,if bit is set(1) then out of
13692                                           soft reset else bit is zero then in
13693                                           reset.                         */
13694       __IOM unsigned int VAD_SOFT_RESET_CNTRL_b : 1;       /*!< [7..7] VAD module soft reset
13695                                       enable,if bit is set(1) then out of soft
13696                                       reset else bit is zero then in reset. */
13697       __IOM unsigned int TOUCH_SOFT_RESET_CNTRL_b : 1;     /*!< [8..8] CAP Sensor module soft reset
13698                                         enable,if bit is set(1)
13699                                         then out of soft reset else bit is zero
13700                                         then in reset.                    */
13701       __IOM unsigned int PROC_MISC_SOFT_RESET_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore,
13702                                                interrupt control, Timer) module
13703                                                   soft reset enable,if bit is
13704                                                set(1) then out of soft reset
13705                                                   else bit is zero then in reset
13706                                              */
13707       __IOM unsigned int COMP1_OUTPUT_CNTRL_b : 1;         /*!< [10..10] This is ULP comparator1
13708                                        interrupt unmasking signal. 0 means
13709                                        comparator1 interrupt is masked and 1
13710                                        means unmasking.
13711                                           It is masked at power-on time. */
13712       __IOM unsigned int COMP2_OUTPUT_CNTRL_b : 1;         /*!< [11..11] This is ULP comparator2
13713                                        interrupt unmasking signal. 0 means
13714                                        comparator2 interrupt is masked and 1
13715                                        means unmasking.
13716                                           It is masked at power-on time. */
13717       __IOM unsigned int RESERVED1 : 2;                    /*!< [13..12] reserved1 */
13718       __IOM unsigned int FIM_SOFT_RESET_CNTRL_b : 1;       /*!< [14..14] FIM module soft reset
13719                                          enable,if bit is set(1) then out of
13720                                          soft reset else bit is  zero then in
13721                                          reset                         */
13722       __IOM unsigned int RESERVED2 : 17;                   /*!< [31..15] reserved2  */
13723     } ULP_TA_PERI_RESET_REG_b;
13724   };
13725   __IM unsigned int RESERVED[2];
13726 
13727   union {
13728     __IOM unsigned int ULP_TA_CLK_GEN_REG; /*!< (@ 0x00000014) ULP NWP clock
13729                                           generation register. */
13730 
13731     struct {
13732       __IOM unsigned int ULP2M4_A2A_BRDG_CLK_EN_b : 1; /*!< [0..0] Clock enable for ULP-M4SS
13733                                            AHB-AHB bridge,if bit is set(1)
13734                                                        then enable else bit is
13735                                            zero then in disable */
13736       __IOM unsigned int ULP_PROC_CLK_SEL : 4;         /*!< [4..1] ulp bus clock select. */
13737       __IOM unsigned int ULP_PROC_CLK_DIV_FACTOR : 8;  /*!< [12..5] ulp bus clock
13738                                                      division factor */
13739       __IOM unsigned int RES : 19;                     /*!< [31..13] reserved1                    */
13740     } ULP_TA_CLK_GEN_REG_b;
13741   };
13742 
13743   union {
13744     __IOM unsigned int ULP_I2C_SSI_CLK_GEN_REG; /*!< (@ 0x00000018) ULP I2C SSI
13745                                                clock generation register. */
13746 
13747     struct {
13748       __IOM unsigned int ULP_I2C_CLK_EN_b : 1;       /*!< [0..0] ulp i2c clock enable,if bit is
13749                                        set(1) then enable else     bit is zero then in
13750                                        disable     */
13751       __IOM unsigned int RESERVED1 : 4;              /*!< [4..1] reserved1 */
13752       __IOM unsigned int RESERVED2 : 8;              /*!< [12..5] reserved2 */
13753       __IOM unsigned int RESERVED3 : 3;              /*!< [15..13] reserved3 */
13754       __IOM unsigned int ULP_SSI_CLK_EN_b : 1;       /*!< [16..16] ssi clk enable if set(1) then
13755                                    enable else bit is zero then disable */
13756       __IOM unsigned int ULP_SSI_CLK_DIV_FACTOR : 7; /*!< [23..17] ssi clk enable if
13757                                                     set(1) then enable else bit
13758                                                     is zero then disable */
13759       __IOM unsigned int RESERVED4 : 4;              /*!< [27..24] reserved4              */
13760       __IOM unsigned int ULP_SSI_CLK_SEL : 4;        /*!< [31..28] Ulp ssi clock select. */
13761     } ULP_I2C_SSI_CLK_GEN_REG_b;
13762   };
13763 
13764   union {
13765     __IOM unsigned int ULP_I2S_CLK_GEN_REG; /*!< (@ 0x0000001C) ULP I2S clock
13766                                            generation register. */
13767 
13768     struct {
13769       __IOM unsigned int ULP_I2S_CLK_EN_b : 1;                /*!< [0..0] ulp i2s clk enable,if bit is set(1)
13770                                    then enable else
13771                                           bit is zero then in disable */
13772       __IOM unsigned int ULP_I2S_CLK_SEL_b : 4;               /*!< [4..1] ulp i2s clock select. */
13773       __IOM unsigned int ULP_I2S_CLKDIV_FACTOR : 8;           /*!< [12..5] ulp i2s clock
13774                                                    division factor. */
13775       __IOM unsigned int ULP_I2S_MASTER_SLAVE_MODE_b : 1;     /*!< [13..13] i2s master slave mode
13776                                               decide field. */
13777       __IOM unsigned int ULP_I2S_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Disable dynamic
13778                                                       clock gating of System clock
13779                                                       in I2S     */
13780       __IOM unsigned int RESERVED1 : 1;                       /*!< [15..15] reserved1                */
13781       __IOM unsigned int ULP_I2S_LOOP_BACK_MODE_b : 1;        /*!< [16..16] Enables loop
13782                                                       back mode in I2S. */
13783       __IOM unsigned int ULP_I2S_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [17..17] Disable dynamic
13784                                                   clock gating of APB clock in
13785                                                   I2S        */
13786       __IOM unsigned int ULP_I2S_PCLK_EN_b : 1;               /*!< [18..18] Static clock enable
13787                                                   for APB clock in I2S    */
13788       __IOM unsigned int RESERVED2 : 13;                      /*!< [31..19] reserved2           */
13789     } ULP_I2S_CLK_GEN_REG_b;
13790   };
13791 
13792   union {
13793     __IOM unsigned int ULP_UART_CLK_GEN_REG; /*!< (@ 0x00000020) ulp uart clock
13794                                             generation register. */
13795 
13796     struct {
13797       __IOM unsigned int ULP_UART_FRAC_CLK_SEL_b : 1; /*!< [0..0] ulp uart clk selection,if bit
13798                                           is set(1) then fractional divider
13799                                           output is  selected else swallow
13800                                           divider output is selected */
13801       __IOM unsigned int ULP_UART_CLK_SEL : 4;        /*!< [4..1] ulp uart clock select. */
13802       __IOM unsigned int ULP_UART_CLKDIV_FACTOR : 3;  /*!< [7..5] ulp uart clock
13803                                                     division factor */
13804       __IOM unsigned int RESERVED1 : 24;              /*!< [31..8] reserved1             */
13805     } ULP_UART_CLK_GEN_REG_b;
13806   };
13807 
13808   union {
13809     __IOM unsigned int M4LP_CTRL_REG; /*!< (@ 0x00000024) m4 ulp control register */
13810 
13811     struct {
13812       __IOM unsigned int RESERVED0 : 2;                          /*!< [1..0] reserved0                */
13813       __IOM unsigned int ULP_M4_CORE_CLK_ENABLE_b : 1;           /*!< [2..2] Static clock
13814                                                      enable m4 core in ULP
13815                                                      mode,if bit is set(1)
13816                                                      then clock enable else
13817                                                      clock is disable */
13818       __IOM unsigned int ULP_MEM_CLK_ULP_ENABLE_b : 1;           /*!< [3..3] Static clock enable for M4
13819                                           memories in ULP mode,if bit
13820                                           is set(1) then clock enable else
13821                                           dynamic control */
13822       __IOM unsigned int ULP_MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Disable the
13823                                                      dynamic clock gating for M4
13824                                                      memories in ULP mode,if bit
13825                                                      is set(1) then  dynamic
13826                                                      control disabled else
13827                                                        dynamic control enabled.
13828                                                    */
13829       __IOM unsigned int RESERVED1 : 27;                         /*!< [31..5] reserved1              */
13830     } M4LP_CTRL_REG_b;
13831   };
13832 
13833   union {
13834     __IOM unsigned int CLOCK_STAUS_REG; /*!< (@ 0x00000028) read clock status register */
13835 
13836     struct {
13837       __IM unsigned int CLOCK_SWITCHED_UART_CLK_b : 1;         /*!< [0..0] status of clock mux for
13838                                            uart,if bit is set(1) then clock is
13839                                            switched,else bit is zero then clock
13840                                            not switched.                     */
13841       __IM unsigned int CLOCK_SWITCHED_I2S_CLK_b : 1;          /*!< [1..1] Status of clock mux for
13842                                           i2s,if bit is set(1) then clock is
13843                                           switched,else bit is zero then clock
13844                                           not switched.                     */
13845       __IM unsigned int CLOCK_SWITCHED_CORTEX_SLEEP_CLK_b : 1; /*!< [2..2] Status of clock mux
13846                                                    for m4 sleep clk,if bit is
13847                                                    set(1) then clock is
13848                                                    switched,else bit is zero
13849                                                    then clock not switched. */
13850       __IM unsigned int CLOCK_SWITCHED_PROC_CLK_b : 1;         /*!< [3..3] Status of clock mux for
13851                                            pclk,if bit is set(1) then clock is
13852                                            switched,else bit is zero then clock
13853                                            not switched.                     */
13854       __IM unsigned int CLOCK_SWITCHED_I2C_b : 1;              /*!< [4..4] Status of clock mux for i2c,if
13855                                       bit is set(1) then clock
13856                                       is switched,else bit is zero then clock
13857                                       not switched.                     */
13858       __IM unsigned int CLOCK_SWITCHED_SSI_b : 1;              /*!< [5..5] Status of clock mux for ssi,if
13859                                       bit is set(1) then clock
13860                                       is switched,else bit is zero then clock
13861                                       not switched.                     */
13862       __IM unsigned int CLOCK_SWITCHED_VAD_b : 1;              /*!< [6..6] Status of clock mux for vad,if
13863                                       bit is set(1) then clock
13864                                       is switched,else bit is zero then clock
13865                                       not switched.                     */
13866       __IM unsigned int CLOCK_SWITCHED_AUXADC_b : 1;           /*!< [7..7] Status of clock mux for aux
13867                                           adc dac clock,if bit is set(1) then
13868                                           clock is switched,else bit is zero
13869                                           then clock not switched. */
13870       __IM unsigned int CLOCK_SWITCHED_TIMER_b : 1;            /*!< [8..8] Status of clock mux for async
13871                                          timers,if bit is set(1) then clock is
13872                                          switched,else bit is zero then clock
13873                                          not switched. */
13874       __IM unsigned int CLOCK_SWITCHED_TOUCH_SENSOR_b : 1;     /*!< [9..9] Status of clock mux for
13875                                                 touch sensor,if bit is set(1)
13876                                                        then clock is
13877                                                 switched,else bit is zero then
13878                                                 clock not switched. */
13879       __IM unsigned int CLOCK_SWITCHED_FCLK_VAD_b : 1;         /*!< [10..10] Status of clock mux for
13880                                             vad fast clock,if bit is set(1) then
13881                                             clock is switched,else bit is zero
13882                                             then clock not switched. */
13883       __IM unsigned int CLOCK_SWITCHED_SCLK_VAD_b : 1;         /*!< [11..11] Status of clock mux for
13884                                             vad slow clock,if bit is set(1) then
13885                                             clock is switched,else bit is zero
13886                                             then clock not switched. */
13887       __IM unsigned int CLOCK_SWITCHED_SYSTICK_b : 1;          /*!< [12..12] Status of clock mux for
13888                                            systick clock,if bit is set(1) then
13889                                            clock is switched,else bit is zero
13890                                            then clock not switched. */
13891       __IOM unsigned int RESERVED1 : 19;                       /*!< [31..13] reserved1    */
13892     } CLOCK_STAUS_REG_b;
13893   };
13894 
13895   union {
13896     __IOM unsigned int ULP_TOUCH_CLK_GEN_REG; /*!< (@ 0x0000002C) ULP touch clock
13897                                              generation register */
13898 
13899     struct {
13900       __IOM unsigned int ULP_TOUCH_CLK_EN_b : 1;      /*!< [0..0] ulp touch clk enable,if bit is
13901                                      set(1) then enable,else bit is zero then
13902                                      disable. */
13903       __IOM unsigned int ULP_TOUCH_CLK_SEL : 4;       /*!< [4..1] ulp touch clock select. */
13904       __IOM unsigned int ULP_TOUCH_CLKDIV_FACTOR : 8; /*!< [12..5] ulp touch clock
13905                                                      division factor. */
13906       __IOM unsigned int RESERVED1 : 19;              /*!< [31..13] reserved1              */
13907     } ULP_TOUCH_CLK_GEN_REG_b;
13908   };
13909 
13910   union {
13911     __IOM unsigned int ULP_TIMER_CLK_GEN_REG; /*!< (@ 0x00000030) ULP clock
13912                                              generation for timer */
13913 
13914     struct {
13915       __IOM unsigned int RESERVED1 : 1;           /*!< [0..0] reserved1 */
13916       __IOM unsigned int ULP_TIMER_CLK_SEL : 4;   /*!< [4..1] ulp timer clock select.    */
13917       __IOM unsigned int RESERVED2 : 8;           /*!< [12..5] reserved2 */
13918       __IOM unsigned int ULP_TIMER_IN_SYNC_b : 1; /*!< [13..13] Ulp timer in synchronous mode
13919                                         to ULPSS pclk                      */
13920       __IOM unsigned int RESERVED3 : 18;          /*!< [31..14] reserved3 */
13921     } ULP_TIMER_CLK_GEN_REG_b;
13922   };
13923 
13924   union {
13925     __IOM unsigned int ULP_AUXADC_CLK_GEN_REG; /*!< (@ 0x00000034) ULP AUX clock
13926                                               generation register */
13927 
13928     struct {
13929       __IOM unsigned int ULP_AUX_CLK_EN_b : 1; /*!< [0..0] ulp aux clk enable,if bit is one
13930                                    then clock enable else
13931                                           bit is zero then clock disable. */
13932       __IOM unsigned int ULP_AUX_CLK_SEL : 4;  /*!< [4..1] ulp aux clock select. */
13933       __IOM unsigned int RESERVED1 : 27;       /*!< [31..5] reserved1      */
13934     } ULP_AUXADC_CLK_GEN_REG_b;
13935   };
13936 
13937   union {
13938     __IOM unsigned int ULP_VAD_CLK_GEN_REG; /*!< (@ 0x00000038) ULP vad clock
13939                                            generation register */
13940 
13941     struct {
13942       __IOM unsigned int ULP_VAD_CLK_EN_b : 1;      /*!< [0..0] ulp vad clk enable ,if bit is one
13943                                    then clock enable else
13944                                           bit is zero then clock disable. */
13945       __IOM unsigned int ULP_VAD_CLK_SEL : 3;       /*!< [3..1] ulp vad clock select. */
13946       __IOM unsigned int ULP_VAD_FCLK_EN : 1;       /*!< [4..4] Enables Fast clock to VAD. */
13947       __IOM unsigned int ULP_VAD_FCLK_SEL : 4;      /*!< [8..5] ulp vad Fast clock select. */
13948       __IOM unsigned int ULP_VAD_CLKDIV_FACTOR : 8; /*!< [16..9] ulp vad clock
13949                                                    division factor */
13950       __IOM unsigned int RESERVED1 : 15;            /*!< [31..17] reserved1            */
13951     } ULP_VAD_CLK_GEN_REG_b;
13952   };
13953 
13954   union {
13955     __IOM unsigned int BYPASS_I2S_CLK_REG; /*!< (@ 0x0000003C) bypass i2s clock register */
13956 
13957     struct {
13958       __IOM unsigned int BYPASS_I2S_PLL_SEL : 1;         /*!< [0..0] Bypass_I2S PLL clock,if
13959                                                 bit is one bypass clock is used
13960                                                      else bit is zero then I2S
13961                                                 Clock is used. */
13962       __IOM unsigned int BYPASS_I2S_PLL_CLK_CLN_ON : 1;  /*!< [1..1] I2S PLL Bypass
13963                                                         clock cleaner ON  */
13964       __IOM unsigned int BYPASS_I2S_PLL_CLK_CLN_OFF : 1; /*!< [2..2] I2S PLL Bypass
13965                                                         clock cleaner OFF */
13966       __IOM unsigned int RESERVED3 : 29;                 /*!< [31..3] reserved3                 */
13967     } BYPASS_I2S_CLK_REG_b;
13968   };
13969   __IM unsigned int RESERVED1;
13970 
13971   union {
13972     __IOM unsigned int ULP_RM_RME_REG; /*!< (@ 0x00000044) ulp rm rem register */
13973 
13974     struct {
13975       __IOM unsigned int ULP_MEM_RME_b : 1;      /*!< [0..0] RM enable signal for memories internal
13976                                 tp peripherals. This needs to be programmed when
13977                                 the peripheral memories are not active. */
13978       __IOM unsigned int ULP_MEM_RM : 2;         /*!< [2..1] RM ports for memories internal to
13979                                       peripheral. This needs          to be programmed when the
13980                                       peripheral memories are not active.             */
13981       __IM unsigned int RESERVED1 : 1;           /*!< [3..3] reserved1 */
13982       __IOM unsigned int ULP_MEM_RME_SRAM_b : 1; /*!< [4..4] RM enable signal for
13983                                                 sram memories. This needs to be
13984                                                      programmed when the SRAM is
13985                                                 not active. */
13986       __IOM unsigned int ULP_MEM_RM_SRAM : 2;    /*!< [6..5] RM ports for sram memories. This
13987                                   needs to be programmed when the SRAM  is not
13988                                   active */
13989       __IOM unsigned int RESERVED2 : 25;         /*!< [31..7] reserved2 */
13990     } ULP_RM_RME_REG_b;
13991   };
13992 
13993   union {
13994     __IOM unsigned int ULP_CLK_ENABLE_REG; /*!< (@ 0x00000048) ulp clock enable register. */
13995 
13996     struct {
13997       __IOM unsigned int ULP_32KHZ_RO_CLK_EN_PROG_b : 1;   /*!< [0..0] Static Clock enable to
13998                                           iPMU for 32KHz RO Clock,if bit is
13999                                           one(set) then clock enable else not
14000                                           enable.                            */
14001       __IOM unsigned int ULP_32KHZ_RC_CLK_EN_PROG_b : 1;   /*!< [1..1] Static Clock enable to
14002                                           iPMU for 32KHz RC Clock,if bit is
14003                                           one(set) then clock enable else not
14004                                           enable.                            */
14005       __IOM unsigned int ULP_32KHZ_XTAL_CLK_EN_PROG_b : 1; /*!< [2..2] Static Clock enable to
14006                                              iPMU for 32KHz XTAL Clock,if bit
14007                                              is one(set) then clock enable else
14008                                              not enable. */
14009       __IOM unsigned int ULP_DOUBLER_CLK_EN_PROG_b : 1;    /*!< [3..3] Static Clock
14010                                                      enable to iPMU for Doubler
14011                                                      Clock,if bit is one(set)
14012                                                      then clock enable else not
14013                                                      enable. */
14014       __IOM unsigned int ULP_20MHZ_RO_CLK_EN_PROG_b : 1;   /*!< [4..4] Static Clock enable to
14015                                           iPMU for 20MHz RO clock,if bit is
14016                                           one(set) then clock enable else not
14017                                           enable.                            */
14018       __IOM unsigned int ULP_MHZ_RC_CLK_EN_PROG_b : 1;     /*!< [5..5] Static Clock enable to
14019                                           iPMU for MHz RC Clock,if bit is
14020                                           one(set) then clock enable else not
14021                                           enable.                            */
14022       __IOM unsigned int SOC_CLK_EN_PROG_b : 1;            /*!< [6..6] Static Clock enable to iPMU for
14023                                  PLL-500 Clock,if bit is one(set) then clock
14024                                  enable else not enable. */
14025       __IOM unsigned int I2S_PLLCLK_EN_PROG_b : 1;         /*!< [7..7] Static clock enable
14026                                                to iPMU for I2S-PLL Clock,if bit
14027                                                is one(set) then clock enable
14028                                                else not enable. */
14029       __IOM unsigned int REF_CLK_EN_IPS_PROG_b : 1;        /*!< [8..8] Static Clock enable to iPMU for
14030                                         REF Clock,if bit is one(set)
14031                                                      then clock enable else not
14032                                         enable. */
14033       __IOM unsigned int RESERVED1 : 23;                   /*!< [31..9] reserved1 */
14034     } ULP_CLK_ENABLE_REG_b;
14035   };
14036   __IM unsigned int RESERVED2;
14037 
14038   union {
14039     __IOM unsigned int SYSTICK_CLK_GEN_REG; /*!< (@ 0x00000050) sys tick clock
14040                                            generation register. */
14041 
14042     struct {
14043       __IOM unsigned int SYSTICK_CLK_EN_b : 1;      /*!< [0..0] sys tick clock enable ,if bit is
14044                                    one(set) then clock enable else not enable.
14045                                  */
14046       __IOM unsigned int SYSTICK_CLK_SEL : 4;       /*!< [4..1] sys tick clock select */
14047       __IOM unsigned int SYSTICK_CLKDIV_FACTOR : 8; /*!< [12..5] sys tick clock
14048                                                    division factor */
14049       __IOM unsigned int RESERVED1 : 19;            /*!< [31..13] reserved1            */
14050     } SYSTICK_CLK_GEN_REG_b;
14051   };
14052   __IM unsigned int RESERVED3[3];
14053   __IOM ULPCLK_ULP_SOC_GPIO_MODE_REG_Type ULP_SOC_GPIO_MODE_REG[16]; /*!< (@ 0x00000060) [0..15] */
14054 
14055   union {
14056     __IOM unsigned int ULP_DYN_CLK_CTRL_DISABLE; /*!< (@ 0x000000A0) this register used for ULP
14057                                      dynamic clock control disable. */
14058 
14059     struct {
14060       __IOM unsigned int I2C_PCLK_DYN_CTRL_DISABLE_b : 1;           /*!< [0..0] Dynamic clock control
14061                                            disable for APB interface in i2c
14062                                            module,if bit is one(set)  then
14063                                            dynamic control disabled
14064                                            else bit is zero then Dynamic control
14065                                            enabled. */
14066       __IOM unsigned int I2S_CLK_DYN_CTRL_DISABLE_b : 1;            /*!< [1..1] Dynamic clock control
14067                                           disable for i2s module,if bit is
14068                                           one(set)  then dynamic control
14069                                           disabled else bit is zero
14070                                           then Dynamic control enabled. */
14071       __IOM unsigned int SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1;       /*!< [2..2] Dynamic clock control
14072                                                   disable for pclk ssi module,if
14073                                                        bit is one(set)  then
14074                                                   dynamic control disabled else
14075                                                   bit is zero then Dynamic
14076                                                   control enabled. */
14077       __IOM unsigned int SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1;       /*!< [3..3] Dynamic clock control
14078                                                   disable for ssi module,if bit
14079                                                   is one(set)  then dynamic
14080                                                   control disabled else bit is
14081                                                   zero then Dynamic control
14082                                                   enabled. */
14083       __IOM unsigned int UART_CLK_DYN_CTRL_DISABLE_b : 1;           /*!< [4..4] Dynamic clock control
14084                                               disable for pclk uart module ,if
14085                                                        bit is one(set)  then
14086                                               dynamic control disabled else bit
14087                                                        is zero then Dynamic
14088                                               control enabled. */
14089       __IOM unsigned int UART_SCLK_DYN_CTRL_DISABLE_b : 1;          /*!< [5..5] Dynamic clock
14090                                                      control disable for uart
14091                                                      module,if bit is one(set)
14092                                                      then dynamic control
14093                                                      disabled else bit is zero
14094                                                      then Dynamic control
14095                                                      enabled. */
14096       __IOM unsigned int TIMER_PCLK_DYN_CTRL_DISABLE_b : 1;         /*!< [6..6] Dynamic clock control
14097                                                 disable for timer pclk module,if
14098                                                        bit is one(set)  then
14099                                                 dynamic control disabled else
14100                                                 bit
14101                                                        is zero then Dynamic
14102                                                 control enabled. */
14103       __IOM unsigned int TIMER_SCLK_DYN_CTRL_DISABLE_b : 1;         /*!< [7..7] Dynamic clock control
14104                                                 disable for timer sclk module,if
14105                                                        bit is one(set)  then
14106                                                 dynamic control disabled else
14107                                                 bit
14108                                                        is zero then Dynamic
14109                                                 control enabled. */
14110       __IOM unsigned int REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [8..8] Dynamic clock
14111                                                        control disable for reg
14112                                                        access spi module,if bit
14113                                                        is one(set)  then dynamic
14114                                                        control disabled else bit
14115                                                        is zero then Dynamic
14116                                                        control enabled. */
14117       __IOM unsigned int FIM_CLK_DYN_CTRL_DISABLE_b : 1;            /*!< [9..9] Dynamic clock control
14118                                           disable for fim module,if bit is
14119                                           one(set)  then dynamic control
14120                                           disabled else bit is zero
14121                                           then Dynamic control enabled. */
14122       __IOM unsigned int VAD_CLK_DYN_CTRL_DISABLE_b : 1;            /*!< [10..10] Dynamic clock
14123                                                      control disable for vad
14124                                                      module,if bit is one(set)
14125                                                      then dynamic control
14126                                                      disabled else bit is zero
14127                                                      then Dynamic control
14128                                                      enabled. */
14129       __IOM unsigned int AUX_PCLK_EN_b : 1;                         /*!< [11..11] Static Enable for Aux adc pclk. */
14130       __IOM unsigned int AUX_CLK_EN_b : 1;                          /*!< [12..12] Static Enable for Aux adc clk. */
14131       __IOM unsigned int AUX_MEM_EN_b : 1;                          /*!< [13..13] Static Enable for Aux adc mem. */
14132       __IOM unsigned int AUX_PCLK_DYN_CTRL_DISABLE_b : 1;           /*!< [14..14] Dynamic clock control
14133                                           disable for aux adc module,if bit is
14134                                           one(set)  then dynamic control
14135                                           disabled else bit
14136                                           is zero then Dynamic control enabled.
14137                                         */
14138       __IOM unsigned int AUX_CLK_DYN_CTRL_DISABLE_b : 1;            /*!< [15..15] Dynamic clock control
14139                                          disable for aux adc module,if bit is
14140                                          one(set)  then dynamic control disabled
14141                                          else bit is zero then Dynamic control
14142                                          enabled. */
14143       __IOM unsigned int AUX_CLK_MEM_DYN_CTRL_DISABLE_b : 1;        /*!< [16..16] Dynamic clock
14144                                                  control disable for aux adc
14145                                                  mem,if bit is one(set)  then
14146                                                  dynamic control disabled else
14147                                                  bit is zero then Dynamic
14148                                                  control enabled. */
14149       __IOM unsigned int UDMA_CLK_ENABLE_b : 1;                     /*!< [17..17] Static Enable for UDMA. */
14150       __IOM unsigned int IR_CLK_ENABLE_b : 1;                       /*!< [18..18] Static Enable for IR. */
14151       __IOM
14152       unsigned int IR_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock control
14153                                               disable for ir module ,if bit is
14154                                               one(set)  then dynamic control
14155                                               disabled else bit is zero then
14156                                               Dynamic control enabled. */
14157       __IOM unsigned int RESERVED1 : 12;          /*!< [31..20] reserved1         */
14158     } ULP_DYN_CLK_CTRL_DISABLE_b;
14159   };
14160 
14161   union {
14162     __IOM unsigned int SLP_SENSOR_CLK_REG; /*!< (@ 0x000000A4) this register used
14163                                           for SLP sensor clock register. */
14164 
14165     struct {
14166       __IOM unsigned int DIVISON_FACTOR : 8; /*!< [7..0] Division factor for apb interface
14167                                  clock to sleep sensor subsystem. */
14168       __IOM unsigned int ENABLE_b : 1;       /*!< [8..8] Enable for APB clock to SLPSS */
14169       __IOM unsigned int RESERVED1 : 23;     /*!< [31..9] reserved1 */
14170     } SLP_SENSOR_CLK_REG_b;
14171   };
14172 } ULPCLK_Type; /*!< Size = 168 (0xa8) */
14173 
14174 /* ===========================================================================================================================
14175  */
14176 /* ================                                            FIM
14177  * ================ */
14178 /* ===========================================================================================================================
14179  */
14180 
14181 /**
14182  * @brief FIM support fixed point Multiplications implemented through
14183  * programmable shifting. (FIM)
14184  */
14185 
14186 typedef struct { /*!< (@ 0x24070000) FIM Structure */
14187 
14188   union {
14189     __IOM unsigned int FIM_MODE_INTERRUPT; /*!< (@ 0x00000000) Configuration for FIM Operation
14190                                Mode and Interrupt Control */
14191 
14192     struct {
14193       __IOM unsigned int LATCH_MODE : 1; /*!< [0..0] Enable latch mode */
14194       __IOM unsigned int OPER_MODE : 8;  /*!< [8..1] Indicates the Mode of Operation
14195                                         to be performed.                   */
14196       __IM unsigned int RESERVED1 : 1;   /*!< [9..9] reserved1   */
14197       __OM unsigned int INTR_CLEAR : 1;  /*!< [10..10] Writing 1 to this bit clears
14198                                         the interrupt                       */
14199       __IM unsigned int RESERVED2 : 21;  /*!< [31..11] reserved2  */
14200     } FIM_MODE_INTERRUPT_b;
14201   };
14202 
14203   union {
14204     __IOM unsigned int FIM_INP1_ADDR; /*!< (@ 0x00000004) This register used for COP
14205                                      input address for 0 register. */
14206 
14207     struct {
14208       __IOM unsigned int INP1_ADDR : 32; /*!< [31..0] Indicates the Start Address of
14209                                         1st Input Data for FIM Operations */
14210     } FIM_INP1_ADDR_b;
14211   };
14212 
14213   union {
14214     __IOM unsigned int FIM_INP2_ADDR; /*!< (@ 0x00000008) This register used for COP
14215                                      input address for 1 register */
14216 
14217     struct {
14218       __IOM unsigned int INP2_ADDR : 32; /*!< [31..0] Indicates the Start Address of
14219                                         2nd Input Data for FIM Operations */
14220     } FIM_INP2_ADDR_b;
14221   };
14222 
14223   union {
14224     __IOM unsigned int FIM_OUT_ADDR; /*!< (@ 0x0000000C) Memory Offset Address for
14225                                     Output from FIM Operations       */
14226 
14227     struct {
14228       __IOM unsigned int OUT_ADDR : 32; /*!< [31..0] Indicates the Start Address of
14229                                        Output Data for FIM Operations     */
14230     } FIM_OUT_ADDR_b;
14231   };
14232 
14233   union {
14234     __IOM unsigned int FIM_SCALAR_POLE_DATA1; /*!< (@ 0x00000010) Indicates the Input Scalar
14235                                   Data for Scalar Operations indicates the
14236                                   feedback coefficient for IIR Operations */
14237 
14238     struct {
14239       __IOM unsigned int SCALAR_POLE_DATA1 : 32; /*!< [31..0] Pole 0/Scalar Value */
14240     } FIM_SCALAR_POLE_DATA1_b;
14241   };
14242 
14243   union {
14244     __IOM unsigned int FIM_POLE_DATA2; /*!< (@ 0x00000014) Feedback coefficient for
14245                                       IIR filter operation              */
14246 
14247     struct {
14248       __IOM unsigned int POLE_DATA2 : 32; /*!< [31..0] Indicates the feedback
14249                                          coefficient for IIR Operations */
14250     } FIM_POLE_DATA2_b;
14251   };
14252 
14253   union {
14254     __IOM unsigned int FIM_SAT_SHIFT; /*!< (@ 0x00000018) Configuration for precision of Output
14255                           Data for FIM Operations */
14256 
14257     struct {
14258       __IOM unsigned int SAT_VAL : 5;   /*!< [4..0] Indicates the number of MSB's to
14259                                        be saturated for Output   Data   */
14260       __IOM unsigned int TRUNCATE : 5;  /*!< [9..5] Truncate  */
14261       __IOM unsigned int SHIFT_VAL : 6; /*!< [15..10] Indicates the number of bits
14262                                        to be right-shifted for Output Data */
14263       __IOM unsigned int ROUND : 2;     /*!< [17..16] Round     */
14264       __IOM unsigned int SAT_EN : 1;    /*!< [18..18] Saturation enable bit    */
14265       __IM unsigned int RESERVED2 : 13; /*!< [31..19] reserved2 */
14266     } FIM_SAT_SHIFT_b;
14267   };
14268 
14269   union {
14270     __IOM unsigned int FIM_CONFIG_REG1; /*!< (@ 0x0000001C) Configuration Register
14271                                        for FIM Operations.                 */
14272 
14273     struct {
14274       __IOM unsigned int MAT_LEN : 6;   /*!< [5..0] Indicates the number of columns in 1st input
14275                           for Matrix Multiplication. This is same as number of
14276                           rows in 2nd input for Matrix Multiplication. */
14277       __IOM unsigned int INP1_LEN : 10; /*!< [15..6] Indicates the length of 1st input for FIM
14278                             Operations other than filtering (FIR, IIR) and
14279                             Interpolation                         */
14280       __IOM unsigned int INP2_LEN : 10; /*!< [25..16] Indicates the length of 2nd input for FIM
14281                             Operations other than filtering (FIR, IIR) and
14282                             Interpolation.                        */
14283       __IOM unsigned int DECIM_FAC : 6; /*!< [31..26] Decimation Factor */
14284     } FIM_CONFIG_REG1_b;
14285   };
14286 
14287   union {
14288     __IOM unsigned int FIM_CONFIG_REG2; /*!< (@ 0x00000020) Configuration Register
14289                                        for FIM Operations                  */
14290 
14291     struct {
14292       __OM unsigned int START_OPER : 1;         /*!< [0..0] Start trigger for the FIM operations,this
14293                              is reset upon write register */
14294       __IOM unsigned int INSTR_BUFF_ENABLE : 1; /*!< [1..1] Instruction buffer enable */
14295       __IM unsigned int RES : 6;                /*!< [7..2] reserved5     */
14296       __IOM unsigned int CPLX_FLAG : 2;         /*!< [9..8] Complex Flag,not valid in matrix mode */
14297       __IOM unsigned int COL_M2 : 6;            /*!< [15..10] Indicates the number of columns
14298                                     in 2nd input for Matrix Multiplication */
14299       __IOM unsigned int ROW_M1 : 6;            /*!< [21..16] Indicates the number of rows in
14300                                     1st input for Matrix Multiplication */
14301       __IOM unsigned int INTRP_FAC : 6;         /*!< [27..22] Indicates the Interpolation Factor */
14302       __IM unsigned int RESERVED1 : 4;          /*!< [31..28] reserved1 */
14303     } FIM_CONFIG_REG2_b;
14304   };
14305 } FIM_Type; /*!< Size = 36 (0x24) */
14306 
14307 /* ===========================================================================================================================
14308  */
14309 /* ================                                          NWP_FSM
14310  * ================ */
14311 /* ===========================================================================================================================
14312  */
14313 
14314 /**
14315  * @brief NWP FSM one register Structure (NWP_FSM)
14316  */
14317 
14318 typedef struct { /*!< (@ 0x41300110) NWP_FSM Structure */
14319 
14320   union {
14321     __IOM unsigned int TASS_REF_CLOCK_SELECT; /*!< (@ 0x00000000) TASS REF CLOCK SELECT */
14322 
14323     struct {
14324       __IOM unsigned int M4SS_REF_CLK_SEL_NWP : 3;         /*!< [2..0] M4SS REF CLK SEL NWP */
14325       __IOM unsigned int RESERVED1 : 1;                    /*!< [3..3] reserved1 */
14326       __IOM unsigned int ULPSS_REF_CLK_SEL_NWP : 3;        /*!< [6..4] ULPSS REF CLK SEL NWP */
14327       __IOM unsigned int RESERVED2 : 9;                    /*!< [15..7] reserved2  */
14328       __IOM unsigned int TASS_REF_CLK_SEL_NWP : 3;         /*!< [18..16] TASS REF CLK SEL NWP */
14329       __IOM unsigned int RESERVED3 : 3;                    /*!< [21..19] reserved3 */
14330       __IOM unsigned int TASS_REF_CLK_CLEANER_OFF_NWP : 1; /*!< [22..22] TASS REF CLK CLEANER
14331                                                OFF NWP */
14332       __IOM unsigned int TASS_REF_CLK_CLEANER_ON_NWP : 1;  /*!< [23..23] TASS REF CLK
14333                                                          CLEANER ON NWP */
14334       __IOM unsigned int RESERVED4 : 8;                    /*!< [31..24] reserved4                   */
14335     } TASS_REF_CLOCK_SELECT_b;
14336   };
14337 } NWP_FSM_Type; /*!< Size = 4 (0x4) */
14338 
14339 /* ===========================================================================================================================
14340  */
14341 /* ================                                           OPAMP
14342  * ================ */
14343 /* ===========================================================================================================================
14344  */
14345 
14346 /**
14347  * @brief The opamps top consists of 3 general purpose Operational Amplifiers
14348  * (OPAMP) offering rail-to-rail inputs and outputs (OPAMP)
14349  */
14350 
14351 typedef struct { /*!< (@ 0x24043A14) OPAMP Structure */
14352 
14353   union {
14354     __IOM unsigned int OPAMP_1; /*!< (@ 0x00000000) Programs opamp1 */
14355 
14356     struct {
14357       __IOM unsigned int OPAMP1_ENABLE : 1;         /*!< [0..0] To enable opamp 1 */
14358       __IOM unsigned int OPAMP1_LP_MODE : 1;        /*!< [1..1] Enable or disable low power mode */
14359       __IOM unsigned int OPAMP1_R1_SEL : 2;         /*!< [3..2] Programmability to select
14360                                            resister bank R1 */
14361       __IOM unsigned int OPAMP1_R2_SEL : 3;         /*!< [6..4] Programmability to select
14362                                            resister bank R2 */
14363       __IOM unsigned int OPAMP1_EN_RES_BANK : 1;    /*!< [7..7] enables the resistor bank 1 for
14364                                      enable 0 for disable               */
14365       __IOM unsigned int OPAMP1_RES_MUX_SEL : 3;    /*!< [10..8] selecting input for
14366                                                 registor bank */
14367       __IOM unsigned int OPAMP1_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out
14368                                         or vdd i.e 0-out and 1-vdd          */
14369       __IOM unsigned int OPAMP1_OUT_MUX_EN : 1;     /*!< [12..12] out mux enable */
14370       __IOM unsigned int OPAMP1_INN_SEL : 3;        /*!< [15..13] selecting -ve input of opamp */
14371       __IOM unsigned int OPAMP1_INP_SEL : 4;        /*!< [19..16] selecting +ve input of opamp */
14372       __IOM unsigned int OPAMP1_OUT_MUX_SEL : 1;    /*!< [20..20] to connect opamp1
14373                                                 output to pad */
14374       __IOM unsigned int MEMS_RES_BANK_EN : 1;      /*!< [21..21] enables mems res bank        */
14375       __IOM unsigned int VREF_MUX_EN : 4;           /*!< [25..22] vref mux enable  */
14376       __IOM unsigned int MUX_EN : 1;                /*!< [26..26] Mux Enable       */
14377       __IOM unsigned int VREF_MUX_SEL : 4;          /*!< [30..27] vref mux enable */
14378       __IOM unsigned int OPAMP1_DYN_EN : 1;         /*!< [31..31] dynamic enable for opamp1 */
14379     } OPAMP_1_b;
14380   };
14381 
14382   union {
14383     __IOM unsigned int OPAMP_2; /*!< (@ 0x00000004) Programs opamp2 */
14384 
14385     struct {
14386       __IOM unsigned int OPAMP2_ENABLE : 1;         /*!< [0..0] enables the opamp2 */
14387       __IOM unsigned int OPAMP2_LP_MODE : 1;        /*!< [1..1] select the power mode 0-normal mode
14388                                  and 1-low power mode           */
14389       __IOM unsigned int OPAMP2_R1_SEL : 2;         /*!< [3..2] Programmability to select
14390                                            resister bank R1 */
14391       __IOM unsigned int OPAMP2_R2_SEL : 3;         /*!< [6..4] Programmability to select
14392                                            resister bank R2 */
14393       __IOM unsigned int OPAMP2_EN_RES_BANK : 1;    /*!< [7..7] enables the resistor bank 1 for
14394                                      enable 0 for disable               */
14395       __IOM unsigned int OPAMP2_RES_MUX_SEL : 3;    /*!< [10..8] selecting input for
14396                                                 registor bank */
14397       __IOM unsigned int OPAMP2_RES_TO_OUT_VDD : 2; /*!< [12..11] connect resistor bank to out
14398                                         or vdd or gnd or DAC i.e
14399                                           0-out and 1-vdd 2-DAC 3-gnd */
14400       __IOM unsigned int OPAMP2_OUT_MUX_EN : 1;     /*!< [13..13] out mux enable */
14401       __IOM unsigned int OPAMP2_INN_SEL : 2;        /*!< [15..14] selecting -ve input of opamp */
14402       __IOM unsigned int OPAMP2_INP_SEL : 3;        /*!< [18..16] selecting +ve input of opamp2 */
14403       __IOM unsigned int OPAMP2_DYN_EN : 1;         /*!< [19..19] dynamic enable for opamp2         */
14404       __IOM unsigned int RESERVED1 : 12;            /*!< [31..20] res */
14405     } OPAMP_2_b;
14406   };
14407 
14408   union {
14409     __IOM unsigned int OPAMP_3; /*!< (@ 0x00000008) Programs opamp3 */
14410 
14411     struct {
14412       __IOM unsigned int OPAMP3_ENABLE : 1;         /*!< [0..0] enables the opamp3 1 for
14413                                            enable 0 for disable */
14414       __IOM unsigned int OPAMP3_LP_MODE : 1;        /*!< [1..1] select the power mode 0-normal mode
14415                                  and 1-low power mode           */
14416       __IOM unsigned int OPAMP3_R1_SEL : 2;         /*!< [3..2] Programmability to select
14417                                            resister bank R1 */
14418       __IOM unsigned int OPAMP3_R2_SEL : 3;         /*!< [6..4] Programmability to select
14419                                            resister bank R2 */
14420       __IOM unsigned int OPAMP3_EN_RES_BANK : 1;    /*!< [7..7] enables the resistor bank 1 for
14421                                      enable 0 for disable               */
14422       __IOM unsigned int OPAMP3_RES_MUX_SEL : 3;    /*!< [10..8] selecting input for
14423                                                 registor bank */
14424       __IOM unsigned int OPAMP3_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out
14425                                         or vdd i.e 0-out and 1-vdd          */
14426       __IOM unsigned int OPAMP3_OUT_MUX_EN : 1;     /*!< [12..12] out mux enable */
14427       __IOM unsigned int OPAMP3_INN_SEL : 2;        /*!< [14..13] selecting -ve input of opamp */
14428       __IOM unsigned int OPAMP3_INP_SEL : 3;        /*!< [17..15] selecting +ve input of opamp */
14429       __IOM unsigned int OPAMP3_DYN_EN : 1;         /*!< [18..18] dynamic enable for opamp2         */
14430       __IOM unsigned int RESERVED1 : 13;            /*!< [31..19] res */
14431     } OPAMP_3_b;
14432   };
14433 } OPAMP_Type; /*!< Size = 12 (0xc) */
14434 
14435 /* ===========================================================================================================================
14436  */
14437 /* ================                                     AUX_ADC_DAC_COMP
14438  * ================ */
14439 /* ===========================================================================================================================
14440  */
14441 
14442 /**
14443   * @brief The ADC-DAC Controller works on a ADC with a resolution of 12bits at
14444   5Mega sample per second when ADC reference Voltage is greater than 2.8v or
14445   5Mega sample per second when ADC reference Voltage is less than 2.8v.
14446   (AUX_ADC_DAC_COMP)
14447   */
14448 
14449 typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */
14450 
14451   union {
14452     __IOM unsigned int AUXDAC_CTRL_1; /*!< (@ 0x00000000) Control register1 for DAC */
14453 
14454     struct {
14455       __IOM unsigned int ENDAC_FIFO_CONFIG : 1;   /*!< [0..0] This bit activates the
14456                                                DAC path in Aux ADC-DAC
14457                                                controller. Data samples will be
14458                                                played on  DAC only when this bit
14459                                                      is set. */
14460       __IOM unsigned int DAC_STATIC_MODE : 1;     /*!< [1..1] This bit is used to select
14461                                              non-FIFO mode in DAC. */
14462       __IOM unsigned int DAC_FIFO_FLUSH : 1;      /*!< [2..2] This bit is used to flush
14463                                              the DAC FIFO.  */
14464       __IOM unsigned int DAC_FIFO_THRESHOLD : 3;  /*!< [5..3] These bits control the DAC FIFO
14465                                      threshold. When used by DMA, this will act
14466                                      as almost full threshold. For NWP, it acts
14467                                      as almost empty threshold */
14468       __IOM unsigned int DAC_ENABLE_F : 1;        /*!< [6..6] This bit is used to enable
14469                                            AUX DAC controller ,valid  only when
14470                                            DAC enable is happpen  */
14471       __IOM unsigned int DAC_WORD_MODE : 1;       /*!< [7..7] This bit is used to select
14472                                            the data size valid on the APB */
14473       __IOM unsigned int AUX_DAC_MAC_MUX_SEL : 1; /*!< [8..8] It is recommended to
14474                                                  write these bits to 0 */
14475 
14476       __IOM unsigned int DAC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [12..9] It is recommended to write
14477                                             these bits to 0 */
14478 
14479       __IOM unsigned int DAC_FIFO_AFULL_THRESHOLD : 4; /*!< [16..13] It is recommended to write
14480                                            these bits to 0 */
14481 
14482       __IOM unsigned int RESERVED1 : 15; /*!< [31..9] Reserved1 */
14483     } AUXDAC_CTRL_1_b;
14484   };
14485 
14486   union {
14487     __IOM unsigned int AUXADC_CTRL_1; /*!< (@ 0x00000004) Control register1 for ADC */
14488 
14489     struct {
14490       __IOM unsigned int ADC_ENABLE : 1;               /*!< [0..0] This bits activates the ADC
14491                                         path in Aux ADC-DAC controller. */
14492       __IOM unsigned int ADC_STATIC_MODE : 1;          /*!< [1..1] This bit is used to select
14493                                              non-FIFO mode in ADC. */
14494       __IOM unsigned int ADC_FIFO_FLUSH : 1;           /*!< [2..2] This bit is used to flush
14495                                              the ADC FIFO  */
14496       __IOM unsigned int RESERVED1 : 3;                /*!< [5..3] RESERVED1       */
14497       __IOM unsigned int ADC_MULTIPLE_CHAN_ACTIVE : 1; /*!< [6..6] This bit is used to control
14498                                            the auxadc sel signal going
14499                                            to the Aux ADC.  */
14500       __IOM unsigned int ADC_CH_SEL_MSB : 2;           /*!< [8..7] It is recommended to write
14501                                             these bits to 0 */
14502       __IOM unsigned int BYPASS_NOISE_AVG : 1;         /*!< [9..9] ADC in Bypass noise avg mode. */
14503       __IOM unsigned int EN_ADC_CLK : 1;               /*!< [10..10] Enable AUX ADC Divider output clock */
14504       __IOM unsigned int ENDIFF : 1;                   /*!< [11..11] Control to the Aux ADC */
14505       __IOM unsigned int ADC_CH_SEL_LS : 2;            /*!< [13..12] Aux ADC channel number from which the
14506                                 data has to be sampled This is valid only when
14507                                 adc multiple channel active is zero. When
14508                                 channel number is greater than three, upper bits
14509                                 should also be programmed ADC CHANNEL SELECT MS
14510                                 to bits in this register */
14511       __IOM unsigned int ADC_WORD_MODE : 1;            /*!< [14..14] This bit is used to select the read
14512                                 data size valid on the APB */
14513       __IOM unsigned int AUX_ADC_MAC_MUX_SEK : 1;      /*!< [15..15] When set, AUX-ADC control is
14514                                       handed over to Aux ADC-ADC controller. By
14515                                       default, AUX-ADC is under the control of
14516                                           baseband. */
14517       __IOM
14518       unsigned int OVERRUN_DMA : 1;            /*!< [16..16] overrun bit in dma mode to
14519                                        enable the over-writing of buffer from
14520                                        beginning when buffer is full. */
14521       __IOM unsigned int RESERVED2 : 4;        /*!< [20..17] Reserved2 */
14522       __IOM unsigned int ADC_WAKE_UP_TIME : 5; /*!< [25..21] overrun bit in dma mode to enable
14523                                    the over-writing of buffer from beginning
14524                                    when buffer is wake up time (number
14525                                           of clock cycles) , dependant upon AUX
14526                                    ADC latency.                        */
14527       __IOM unsigned int EN_ADC_TRUN_OFF : 1;  /*!< [26..26] Enable power save mode to turn off
14528                                   AUX ADC when sampling clock is idle and enable
14529                                   it before sampling event, programmed by
14530                                   adc_wake_up_time */
14531       __IOM unsigned int ADC_NUM_PHASE : 1;    /*!< [27..27] ADC number of phase */
14532       __IOM unsigned int RESERVED3 : 4;        /*!< [31..28] Reserved3     */
14533     } AUXADC_CTRL_1_b;
14534   };
14535 
14536   union {
14537     __IOM unsigned int AUXDAC_CLK_DIV_FAC; /*!< (@ 0x00000008) DAC clock division register */
14538 
14539     struct {
14540       __IOM unsigned int DAC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the
14541                                               DAC clock division factor */
14542       __IOM unsigned int RESERVED1 : 22;       /*!< [31..10] Reserved1       */
14543     } AUXDAC_CLK_DIV_FAC_b;
14544   };
14545 
14546   union {
14547     __IOM unsigned int AUXADC_CLK_DIV_FAC; /*!< (@ 0x0000000C) ADC clock division register */
14548 
14549     struct {
14550       __IOM unsigned int ADC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the
14551                                             Total-Duration of the ADC clock          */
14552       __IOM unsigned int RESERVED1 : 6;        /*!< [15..10] Reserved1      */
14553       __IOM unsigned int ADC_CLK_ON_DUR : 9;   /*!< [24..16] These bits control the
14554                                             On-Duration of the ADC clock */
14555       __IOM unsigned int RESERVED2 : 7;        /*!< [31..25] Reserved2      */
14556     } AUXADC_CLK_DIV_FAC_b;
14557   };
14558 
14559   union {
14560     __IOM unsigned int AUXDAC_DATA_REG; /*!< (@ 0x00000010) Writing to this register will fill
14561                             DAC FIFO for streaming Data to DAC */
14562 
14563     struct {
14564       __IOM unsigned int AUXDAC_DATA : 10; /*!< [9..0] Writing to this register will fill DAC
14565                                FIFO for streaming Data to DAC */
14566       __IOM unsigned int RESERVED1 : 22;   /*!< [31..10] Reserved1 */
14567     } AUXDAC_DATA_REG_b;
14568   };
14569 
14570   union {
14571     __IOM unsigned int AUXADC_DATA; /*!< (@ 0x00000014) AUXADC Data Read through Register. */
14572 
14573     struct {
14574       __IM unsigned int AUXADC_DATA : 12; /*!< [11..0] AUXADC Data Read through Register */
14575       __IM unsigned int AUXADC_CH_ID : 4; /*!< [15..12] AUXADC Channel ID */
14576       __IOM unsigned int RESERVED1 : 16;  /*!< [31..16] Reserved1  */
14577     } AUXADC_DATA_b;
14578   };
14579 
14580   union {
14581     __IOM unsigned int ADC_DET_THR_CTRL_0; /*!< (@ 0x00000018) ADC detection
14582                                           threshold control 0 */
14583 
14584     struct {
14585       __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_0 : 8; /*!< [7..0] The value against
14586                                                   which the ADC output has to be
14587                                                   compared is to be programmed
14588                                                   in this register */
14589       __IOM unsigned int COMP_LESS_THAN_EN : 1;               /*!< [8..8] When set, Aux ADC-DAC controller
14590                                     raises an interrupt to processor when the
14591                                     Aux ADC output falls below the  programmed
14592                                     Aux ADC detection threshold. */
14593       __IOM
14594       unsigned int COMP_GRTR_THAN_EN : 1;                     /*!< [9..9] When set, Aux ADC-DAC
14595                                         controller raises an interrupt to
14596                                         processor when the Aux ADC output is
14597                                         greater than the programmed Aux ADC
14598                                         detection threshold.. */
14599       __IOM unsigned int COMP_EQ_EN : 1;                      /*!< [10..10] When set, Aux ADC-DAC controller raises
14600                              an interrupt to processor when  the Aux ADC output
14601                              is equal to the programmed Aux ADC detection
14602                              threshold */
14603       __IOM unsigned int RANGE_COMPARISON_ENABLE : 1;         /*!< [11..11] When set, Aux ADC-DAC
14604                                           controller raises an interrupt to
14605                                           processor when the Aux ADC output
14606                                           falls within the range specified in
14607                                           AUX ADC Detection threshold0  and AUX
14608                                           ADC Detection threshold1 */
14609       __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_1 : 4; /*!< [15..12] Carries upper four
14610                                                   bits of ADC detection
14611                                                   threshold      */
14612       __IOM unsigned int RESERVED1 : 16;                      /*!< [31..16] Reserved1           */
14613     } ADC_DET_THR_CTRL_0_b;
14614   };
14615 
14616   union {
14617     __IOM unsigned int ADC_DET_THR_CTRL_1; /*!< (@ 0x0000001C) ADC detection
14618                                           threshold control 1 */
14619 
14620     struct {
14621       __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_2 : 8;      /*!< [7..0] The value against
14622                                                   which the ADC output has to be
14623                                                   compared is to be programmed
14624                                                   in this register. */
14625       __IOM unsigned int COMP_LESS_THAN_EN : 1;                    /*!< [8..8] When set, Aux ADC-DAC controller
14626                                     raises an interrupt to NWP when the Aux ADC
14627                                     output  falls below the programmed Aux ADC
14628                                     detection threshold. */
14629       __IOM unsigned int COMP_GRTR_THAN_EN : 1;                    /*!< [9..9] When set, Aux ADC-DAC controller
14630                                     raises an interrupt to NWP when the Aux ADC
14631                                     output is greater than the programmed Aux
14632                                     ADC detection threshold. */
14633       __IOM unsigned int COMP_EQ_EN : 1;                           /*!< [10..10] When set, Aux ADC-DAC controller raises
14634                              an interrupt to NWP when the  Aux ADC output is
14635                              equal to the programmed Aux ADC detection
14636                              threshold. */
14637       __IOM unsigned int ADC_DETECTION_THRESHOLD_4_UPPER_BITS : 4; /*!< [14..11] Upper 4 bits
14638                                                        of ADC detection
14639                                                        threshold 2 for ADC  */
14640       __IOM unsigned int RESERVED1 : 17;                           /*!< [31..15] Reserved1                */
14641     } ADC_DET_THR_CTRL_1_b;
14642   };
14643 
14644   union {
14645     __IOM unsigned int INTR_CLEAR_REG; /*!< (@ 0x00000020) ADC detection threshold
14646                                       control 1                          */
14647 
14648     struct {
14649       __IOM unsigned int CLR_INTR : 1;        /*!< [0..0] This bit is used to clear
14650                                              threshold detection interrupt        */
14651       __IOM unsigned int RESERVED1 : 7;       /*!< [7..1] Reserved1       */
14652       __IOM unsigned int INTR_CLEAR_REG : 16; /*!< [23..8] If enabled, corresponding
14653                                              first_mem_switch_intr bits
14654                                                      will be cleared. */
14655       __IOM unsigned int RESERVED2 : 8;       /*!< [31..24] Reserved2       */
14656     } INTR_CLEAR_REG_b;
14657   };
14658 
14659   union {
14660     __IOM unsigned int INTR_MASK_REG; /*!< (@ 0x00000024) Mask interrupt register */
14661 
14662     struct {
14663       __IOM unsigned int THRESHOLD_DETECTION_INTR_EN : 1;    /*!< [0..0] When Cleared, threshold
14664                                               detection interrupt will be
14665                                               unmasked  */
14666       __IOM unsigned int DAC_FIFO_EMPTY_INTR_MASK : 1;       /*!< [1..1] When Cleared, dac_FIFO_empty
14667                                            interrupt will be unmasked */
14668       __IOM unsigned int DAC_FIFO_AEMPTY_INTR_MASK : 1;      /*!< [2..2] When Cleared, adc FIFO full
14669                                             interrupt will be unmasked */
14670       __IOM unsigned int ADC_FIFO_FULL_INTR_MASK : 1;        /*!< [3..3] When Cleared, adc FIFO full
14671                                           interrupt will be unmasked */
14672       __IOM unsigned int ADC_FIFO_AFULL_INTR_MASK : 1;       /*!< [4..4] When Cleared, adc FIFO afull
14673                                            interrupt will be unmasked */
14674       __IOM unsigned int ADC_FIFO_OVERFLOW_INTR_MASK : 1;    /*!< [5..5] When Cleared, dac FIFO
14675                                               underrun interrupt will be
14676                                               unmasked    */
14677       __IOM unsigned int DAC_FIFO_UNDERRUN_INTR_MASK : 1;    /*!< [6..6] When Cleared, dac FIFO
14678                                               underrun interrupt will be
14679                                               unmasked    */
14680       __IOM unsigned int FIRST_MEM_SWITCH_INTR_MASK : 16;    /*!< [22..7] When Cleared,
14681                                                          first_mem_switch_intr
14682                                                          will be unmasked */
14683       __IOM unsigned int ADC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [23..23] When Cleared, adc
14684                                                  static_mode_data_intr will be
14685                                                  unmasked */
14686       __IOM unsigned int DAC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [24..24] When Cleared, dac
14687                                                  static_mode_data_intr will be
14688                                                  unmasked */
14689       __IOM unsigned int RESERVED1 : 7;                      /*!< [31..25] Reserved1           */
14690     } INTR_MASK_REG_b;
14691   };
14692 
14693   union {
14694     __IM unsigned int INTR_STATUS_REG; /*!< (@ 0x00000028) Status interrupt register */
14695 
14696     struct {
14697       __IM unsigned int ADC_THRESHOLD_DETECTION_INTR : 1; /*!< [0..0] This bit is set when ADC
14698                                                threshold matches with the
14699                                                programmed conditions This will
14700                                                be be cleared as soon as this
14701                                                interrupt is acknowledged by
14702                                                processor */
14703       __IM unsigned int DAC_FIFO_EMPTY : 1;               /*!< [1..1] Set when DAC FIFO is empty. This bit
14704                                  gets cleared when the DAC FIFO at least a
14705                                  single sample is available in DAC FIFO */
14706       __IM unsigned int DAC_FIFO_AEMPTY : 1;              /*!< [2..2] Set when the FIFO occupancy grater
14707                                   than or equal to DAC FIFO threshold. */
14708       __IM unsigned int ADC_FIFO_FULL : 1;                /*!< [3..3] Set when ADC FIFO is full,This bit gets
14709                                 cleared when data is read from the FIFO */
14710       __IM unsigned int ADC_FIFO_AFULL : 1;               /*!< [4..4] Set when ADC FIFO occupancy less than
14711                                  or equal to ADC FIFO threshold */
14712       __IM unsigned int ADC_FIFO_OVERFLOW : 1;            /*!< [5..5] Set when a write attempt is made to
14713                                     ADC FIFO when the FIFO is already full */
14714       __IM unsigned int DAC_FIFO_UNDERRUN : 1;            /*!< [6..6] Set when a read is done on DAC FIFO
14715                                     when the FIFO is empty */
14716       __IM unsigned int FIRST_MEM_SWITCH_INTR : 16;       /*!< [22..7] Interrupt
14717                                                    indicating the first memory
14718                                                    has been filled and the DMA
14719                                                    write is being shifted to
14720                                                    second memory chunk for
14721                                                    ping-pong operation */
14722       __IM unsigned int ADC_STATIC_MODE_DATA_INTR : 1;    /*!< [23..23] Set when a proper data
14723                                             packet is ready to read in static
14724                                                        mode for ADC */
14725       __IM unsigned int DAC_STATIC_MODE_DATA_INTR : 1;    /*!< [24..24] Set when a proper data
14726                                             packet is ready to read in static
14727                                                        mode for DAC */
14728       __IM unsigned int RESERVED1 : 7;                    /*!< [31..25] Reserved1       */
14729     } INTR_STATUS_REG_b;
14730   };
14731 
14732   union {
14733     __IM unsigned int INTR_MASKED_STATUS_REG; /*!< (@ 0x0000002C) Interrupt masked
14734                                              status register */
14735 
14736     struct {
14737       __IM unsigned int ADC_THRESHOLD_DETECTION_INTR_MASKED : 1; /*!< [0..0] Masked Interrupt.
14738                                                       This bit is set when ADC
14739                                                       threshold matches with
14740                                                       the programmed conditions
14741                                                     */
14742       __IM unsigned int DAC_FIFO_EMPTY_MASKED : 1;               /*!< [1..1] Masked Interrupt.Set
14743                                                   when DAC FIFO is empty */
14744       __IM unsigned int DAC_FIFO_AEMPTY_MASKED : 1;              /*!< [2..2] Masked Interrupt. Set when the
14745                                          FIFO occupancy less than equal to DAC
14746                                          FIFO threshold. */
14747       __IM unsigned int ADC_FIFO_FULL_MASKED : 1;                /*!< [3..3] Masked Interrupt. Set
14748                                                  when ADC FIFO is full. */
14749       __IM unsigned int ADC_FIFO_AFULL_MASKED : 1;               /*!< [4..4] Masked Interrupt. Set when ADC
14750                                         FIFO occupancy greater than ADC FIFO
14751                                         threshold */
14752       __IM unsigned int ADC_FIFO_OVERFLOW_MASKED : 1;            /*!< [5..5] Masked Interrupt. Set when a
14753                                            write attempt is made to ADC FIFO
14754                                            when the FIFO is already full. */
14755       __IM unsigned int DAC_FIFO_UNDERRUN_MASKED : 1;            /*!< [6..6] Masked Interrupt. Set when a
14756                                            read is done on DAC FIFO when the
14757                                            FIFO is empty. */
14758       __IM unsigned int FIRST_MEM_SWITCH_INTR_MASKED : 16;       /*!< [22..7] Masked Interrupt
14759                                            status indicating the first memory
14760                                            has been filled and the DMA write is
14761                                            being shifted  to
14762                                            second memory chunk for ping-pong
14763                                            operation */
14764       __IM unsigned int ADC_STATIC_MODE_DATA_INTR_MASKED : 1;    /*!< [23..23] Masked Interrupt.
14765                                                    Set when a proper data packet
14766                                                    is ready to read in static
14767                                                    mode for ADC */
14768       __IM unsigned int DAC_STATIC_MODE_DATA_INTR_MASKED : 1;    /*!< [24..24] Masked Interrupt.
14769                                                    Set when a proper data packet
14770                                                    is ready to read in static
14771                                                    mode for DAC */
14772       __IM unsigned int RESERVED1 : 7;                           /*!< [31..25] Reserved1              */
14773     } INTR_MASKED_STATUS_REG_b;
14774   };
14775 
14776   union {
14777     __IM unsigned int FIFO_STATUS_REG; /*!< (@ 0x00000030) Interrupt masked status
14778                                       register                           */
14779 
14780     struct {
14781       __IM unsigned int DAC_FIFO_FULL : 1;   /*!< [0..0] Set when DAC FIFO is full. In
14782                                          word mode, FIFO will be shown as full
14783                                          unless there is space for 16-bits. */
14784       __IM unsigned int DAC_FIFO_AFULL : 1;  /*!< [1..1] Set when DAC FIFO occupancy
14785                                            greater than FIFO threshold */
14786       __IM unsigned int ADC_FIFO_EMPTY : 1;  /*!< [2..2] Set when FIFO is empty. This bit gets
14787                                  cleared when the ADC FIFO is not empty. */
14788       __IM unsigned int ADC_FIFO_AEMPTY : 1; /*!< [3..3] Set when the FIFO occupancy
14789                                             less than ADC FIFO threshold */
14790       __IM unsigned int DAC_FIFO_EMPTY : 1;  /*!< [4..4] Set when FIFO is empty. This bit gets
14791                                  cleared when the DAC FIFO is not empty. */
14792       __IM unsigned int DAC_FIFO_AEMPTY : 1; /*!< [5..5] Set when the FIFO occupancy
14793                                             less than DAC FIFO threshold */
14794       __IM unsigned int ADC_FIFO_FULL : 1;   /*!< [6..6] Set when ADC FIFO is full.
14795                                             This bit gets cleared when   data is
14796                                             read from the FIFO.   */
14797       __IM unsigned int ADC_FIFO_AFULL : 1;  /*!< [7..7] Set when ADC FIFO occupancy
14798                                             greater than ADC FIFO threshold.  */
14799       __IM unsigned int RESERVED1 : 24;      /*!< [31..8] Reserved1      */
14800     } FIFO_STATUS_REG_b;
14801   };
14802 
14803   union {
14804     __IOM unsigned int ADC_CTRL_REG_2; /*!< (@ 0x00000034) ADC Control register2 */
14805 
14806     struct {
14807       __IOM unsigned int EXT_TRIG_DETECT_1 : 2; /*!< [1..0] Condition to detect event on
14808                                     external trigger 1 00: None (trigger
14809                                     disabled) 01: Positive edge 10: Negative
14810                                     edge 11: Positive or negative edge. */
14811       __IOM unsigned int EXT_TRIG_DETECT_2 : 2; /*!< [3..2] Condition to detect event on
14812                                     external trigger 2 00: None (trigger
14813                                     disabled) 01: Positive edge 10: Negative
14814                                     edge 11: Positive or negative edge. */
14815       __IOM unsigned int EXT_TRIG_DETECT_3 : 2; /*!< [5..4] Condition to detect event on
14816                                     external trigger 3 00: None (trigger
14817                                     disabled) 01: Positive edge 10: Negative
14818                                     edge 11: Positive or negative edge. */
14819       __IOM unsigned int EXT_TRIG_DETECT_4 : 2; /*!< [7..6] Condition to detect event on
14820                                     external trigger 4 00: None (trigger
14821                                     disabled) 01: Positive edge 10: Negative
14822                                     edge 11: Positive or negative edge. */
14823       __IOM unsigned int EXT_TRIGGER_SEL_4 : 4; /*!< [11..8] 4-bit Channel ID corresponding to
14824                                     external trigger 4.             */
14825       __IOM unsigned int EXT_TRIGGER_SEL_3 : 4; /*!< [15..12] 4-bit Channel ID corresponding to
14826                                     external trigger 3. */
14827       __IOM unsigned int EXT_TRIGGER_SEL_2 : 4; /*!< [19..16] Enable bit corresponding to
14828                                     channel id selected for trigger 2. */
14829       __IOM unsigned int EXT_TRIGGER_SEL_1 : 4; /*!< [23..20] 4-bit Channel ID corresponding to
14830                                     external trigger 1. */
14831       __IOM unsigned int TRIG_1_MATCH : 1;      /*!< [24..24] indicating trigger 1 is matched. Write
14832                                1 to clear this bit. */
14833       __IOM unsigned int TRIG_2_MATCH : 1;      /*!< [25..25] indicating trigger 2 is matched. Write
14834                                1 to clear this bit. */
14835       __IOM unsigned int TRIG_3_MATCH : 1;      /*!< [26..26] indicating trigger 3 is matched. Write
14836                                1 to clear this bit. */
14837       __IOM unsigned int TRIG_4_MATCH : 1;      /*!< [27..27] indicating trigger 4 is matched. Write
14838                                1 to clear this bit. */
14839       __IOM unsigned int RESERVED1 : 4;         /*!< [31..28] Reserved1 */
14840     } ADC_CTRL_REG_2_b;
14841   };
14842   __IOM AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type ADC_CH_BIT_MAP_CONFIG[16]; /*!< (@ 0x00000038) [0..15] */
14843 
14844   union {
14845     __IOM unsigned int ADC_CH_OFFSET[16]; /*!< (@ 0x00000138) This Register specifies initial
14846                               offset value with respect  to AUX_ADC clock after
14847                               which Channel(0-16)should be sampled. */
14848 
14849     struct {
14850       __IOM unsigned int CH_OFFSET : 16; /*!< [15..0] This Register field specifies initial
14851                              offset value with respect  to AUX_ADC clock after
14852                              which Channel(0-16)should be sampled. */
14853       __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */
14854     } ADC_CH_OFFSET_b[16];
14855   };
14856 
14857   union {
14858     __IOM unsigned int ADC_CH_FREQ[16]; /*!< (@ 0x00000178) This register specifies Sampling
14859                             frequency rate at which AUX ADC Date is sampled for
14860                             Channel(1 to 16 ) */
14861 
14862     struct {
14863       __IOM unsigned int CH_FREQ_VALUE : 16; /*!< [15..0] This register specifies Sampling
14864                                  frequency rate at which AUX ADC Date is sampled
14865                                  for Channel all respective channel (1-16) */
14866       __IOM unsigned int RESERVED1 : 16;     /*!< [31..16] Reserved1 */
14867     } ADC_CH_FREQ_b[16];
14868   };
14869 
14870   union {
14871     __IOM unsigned int ADC_CH_PHASE_1; /*!< (@ 0x000001B8) ADC Channel Phase 1 */
14872 
14873     struct {
14874       __IOM unsigned int CH1_PHASE : 4; /*!< [3..0] Phase corresponding to channel-1 */
14875       __IOM unsigned int CH2_PHASE : 4; /*!< [7..4] Phase corresponding to channel-2 */
14876       __IOM unsigned int CH3_PHASE : 4; /*!< [11..8] Phase corresponding to channel-3 */
14877       __IOM unsigned int CH4_PHASE : 4; /*!< [15..12] Phase corresponding to channel-4 */
14878       __IOM unsigned int CH5_PHASE : 4; /*!< [19..16] Phase corresponding to channel-5 */
14879       __IOM unsigned int CH6_PHASE : 4; /*!< [23..20] Phase corresponding to channel-6 */
14880       __IOM unsigned int CH7_PHASE : 4; /*!< [27..24] Phase corresponding to channel-7 */
14881       __IOM unsigned int CH8_PHASE : 4; /*!< [31..28] Phase corresponding to channel-8 */
14882     } ADC_CH_PHASE_1_b;
14883   };
14884 
14885   union {
14886     __IOM unsigned int ADC_CH_PHASE_2; /*!< (@ 0x000001BC) ADC Channel Phase 2 */
14887 
14888     struct {
14889       __IOM unsigned int CH9_PHASE : 4;  /*!< [3..0] Phase corresponding to channel-9 */
14890       __IOM unsigned int CH10_PHASE : 4; /*!< [7..4] Phase corresponding to channel-10 */
14891       __IOM unsigned int CH11_PHASE : 4; /*!< [11..8] Phase corresponding to channel-11 */
14892       __IOM unsigned int CH12_PHASE : 4; /*!< [15..12] Phase corresponding to channel-12 */
14893       __IOM unsigned int CH13_PHASE : 4; /*!< [19..16] Phase corresponding to channel-13 */
14894       __IOM unsigned int CH14_PHASE : 4; /*!< [23..20] Phase corresponding to channel-14 */
14895       __IOM unsigned int CH15_PHASE : 4; /*!< [27..24] Phase corresponding to channel-15 */
14896       __IOM unsigned int CH16_PHASE : 4; /*!< [31..28] Phase corresponding to channel-16 */
14897     } ADC_CH_PHASE_2_b;
14898   };
14899   __IM unsigned int RESERVED;
14900 
14901   union {
14902     __IOM unsigned int ADC_SINGLE_CH_CTRL_1; /*!< (@ 0x000001C4) ADC SINGLE Channel
14903                                             Configuration */
14904 
14905     struct {
14906       __IOM unsigned int ADC_CH_INDEX_SINGLE_CHAN_1 : 32; /*!< [31..0] [31:0]out of total 48
14907                                               bits of bit map for single channel
14908                                                        mode of a particular
14909                                               channel. */
14910     } ADC_SINGLE_CH_CTRL_1_b;
14911   };
14912 
14913   union {
14914     __IOM unsigned int ADC_SINGLE_CH_CTRL_2; /*!< (@ 0x000001C8) ADC SINGLE Channel
14915                                             Configuration */
14916 
14917     struct {
14918       __IOM unsigned int ADC_CH_INDEX_SINGLE_CHAN_2 : 16; /*!< [15..0] [47:32] out of total 48
14919                                               bits of bit map for single channel
14920                                                        mode of a particular
14921                                               channel. */
14922       __IOM unsigned int ADC_INTERPOL_SINGLE_CHAN : 2;    /*!< [17..16] Interpolation angle for
14923                                            the particular channel in single
14924                                                        channel mode whose bit
14925                                            sequence has been written to
14926                                            adc_ch_index_single_c an. */
14927       __IOM unsigned int RESERVED1 : 14;                  /*!< [31..18] Reserved1    */
14928     } ADC_SINGLE_CH_CTRL_2_b;
14929   };
14930 
14931   union {
14932     __IOM unsigned int ADC_SEQ_CTRL; /*!< (@ 0x000001CC) This register explain
14933                                     configuration parameter for AUXADC */
14934 
14935     struct {
14936       __IOM unsigned int ADC_SEQ_CTRL_PING_PONG : 16; /*!< [15..0] To enable/disable per
14937                                           channel DAM mode (One-hot coding) */
14938       __IOM unsigned int ADC_SEQ_CTRL_DMA_MODE : 16;  /*!< [31..16] To enable/disable per
14939                                          channel ping-pong operation (One-hot
14940                                                        coding). */
14941     } ADC_SEQ_CTRL_b;
14942   };
14943 
14944   union {
14945     __IOM unsigned int VAD_BBP_ID; /*!< (@ 0x000001D0) This register explain VDD BBP ID */
14946 
14947     struct {
14948       __IOM unsigned int BPP_ID : 4;          /*!< [3..0] Channel id for bbp samples. */
14949       __IOM unsigned int BPP_EN : 1;          /*!< [4..4] Enables Aux-ADC samples to BBP */
14950       __IOM unsigned int AUX_ADC_BPP_EN : 1;  /*!< [5..5] Enable Indication for BBP        */
14951       __IOM unsigned int RESERVED1 : 10;      /*!< [15..6] RESERVED1 */
14952       __IOM unsigned int DISCONNET_MODE : 16; /*!< [31..16] Per channel discontinuous mode
14953                                   enable signal. When discontinuous mode is
14954                                   enabled, data is sampled only once from that
14955                                   channel and the enable bit is reset to 0. */
14956     } VAD_BBP_ID_b;
14957   };
14958 
14959   union {
14960     __IOM unsigned int ADC_INT_MEM_1; /*!< (@ 0x000001D4) This register explain start address
14961                           of first/second buffer corresponding to the channel
14962                           location ADC INT MEM 2 */
14963 
14964     struct {
14965       __IOM unsigned int PROG_WR_DATA : 32; /*!< [31..0] These 32-bits specifies the
14966                                            start address of first/second
14967                                                      buffer corresponding to the
14968                                            channel  location ADC INT MEM */
14969     } ADC_INT_MEM_1_b;
14970   };
14971 
14972   union {
14973     __IOM unsigned int ADC_INT_MEM_2; /*!< (@ 0x000001D8) This register explain ADC
14974                                      INT MEM2.                        */
14975 
14976     struct {
14977       __IOM unsigned int PROG_WR_DATA : 10; /*!< [9..0] These 10-bits specify the buffer length
14978                                 of first/second buffer corresponding to the
14979                                 channel location ADC INT MEM2                 */
14980       __IOM unsigned int PROG_WR_ADDR : 5;  /*!< [14..10] These bits correspond to
14981                                           the address of the internal memory
14982                                           basing on the channel number,  whose
14983                                           information we want to program */
14984       __IOM unsigned int PROG_WR_DATA1 : 1; /*!< [15..15] Valid bit for first/second buffers
14985                                 corresponding to ADC INT MEM2 */
14986       __IOM unsigned int RESERVED3 : 16;    /*!< [31..16] Reserved3 */
14987     } ADC_INT_MEM_2_b;
14988   };
14989 
14990   union {
14991     __IOM unsigned int INTERNAL_DMA_CH_ENABLE; /*!< (@ 0x000001DC) This register is
14992                                               internal channel enable */
14993 
14994     struct {
14995       __IOM unsigned int PER_CHANNEL_ENABLE : 16; /*!< [15..0] Enable bit for Each
14996                                                  channel,like channel0 for bit0
14997                                                  to channel15 for bit15 etc */
14998       __IOM unsigned int RESERVED3 : 15;          /*!< [30..16] Reserved3          */
14999       __IOM unsigned int INTERNAL_DMA_ENABLE : 1; /*!< [31..31] When Set, Internal DMA will be
15000                                       used for reading ADC
15001                                           samples from ADC FIFO and  writing
15002                                       them to ULP SRAM Memories.             */
15003     } INTERNAL_DMA_CH_ENABLE_b;
15004   };
15005 
15006   union {
15007     __IOM unsigned int TS_PTAT_ENABLE; /*!< (@ 0x000001E0) This register is enable
15008                                       PTAT for temperature sensor */
15009 
15010     struct {
15011       __IOM unsigned int TS_PTAT_EN : 1; /*!< [0..0] BJT based Temperature sensor            */
15012       __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */
15013     } TS_PTAT_ENABLE_b;
15014   };
15015 
15016   union {
15017     __OM unsigned int ADC_FIFO_THRESHOLD; /*!< (@ 0x000001E4) Configured FIFO to ADC */
15018 
15019     struct {
15020       __OM unsigned int ADC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [3..0] FIFO almost empty
15021                                                       threshold for ADC */
15022       __OM unsigned int ADC_FIFO_AFULL_THRESHOLD : 4;  /*!< [7..4] FIFO almost full
15023                                                       threshold for ADC  */
15024       __OM unsigned int RESERVED1 : 24;                /*!< [31..8] Reserved1                */
15025     } ADC_FIFO_THRESHOLD_b;
15026   };
15027   __IM unsigned int RESERVED1[6];
15028 
15029   union {
15030     __IOM unsigned int BOD; /*!< (@ 0x00000200) Programs resistor bank, reference
15031                            buffer and scaler */
15032 
15033     struct {
15034       __IOM unsigned int EN_BOD_TEST_MUX : 1; /*!< [0..0] 1 - To enable test mux         */
15035       __IOM unsigned int BOD_TEST_SEL : 2;    /*!< [2..1] Select bits for test mux */
15036       __IOM unsigned int REFBUF_EN : 1;       /*!< [3..3] Reference buffer configuration 1
15037                                        for enable 0 for disable          */
15038       __IOM unsigned int REFBUF_VOLT_SEL : 4; /*!< [7..4] selection of voltage of
15039                                              reference buffer */
15040       __IOM unsigned int BOD_RES_EN : 1;      /*!< [8..8] configuration of register bank
15041                                         1 for enable and 0 for disable */
15042       __IOM unsigned int BOD_THRSH : 5;       /*!< [13..9] Programmability for resistor bank */
15043       __IOM unsigned int RESERVED2 : 18;      /*!< [31..14] Reserved2 */
15044     } BOD_b;
15045   };
15046 
15047   union {
15048     __IOM unsigned int COMPARATOR1; /*!< (@ 0x00000204) Programs comparators1 and
15049                                    comparators2                     */
15050 
15051     struct {
15052       __IOM unsigned int CMP1_EN : 1;        /*!< [0..0] To enable comparator1 */
15053       __IOM unsigned int CMP1_EN_FILTER : 1; /*!< [1..1] To enable filter for comparator 1 */
15054       __IOM unsigned int CMP1_HYST : 2;      /*!< [3..2] Programmability to control
15055                                             hysteresis of comparator1      */
15056       __IOM unsigned int CMP1_MUX_SEL_P : 4; /*!< [7..4] Select for positive input
15057                                             of comparator_1 */
15058       __IOM unsigned int CMP1_MUX_SEL_N : 4; /*!< [11..8] Select for negative input
15059                                             of comparator_1 */
15060       __IOM unsigned int CMP2_EN : 1;        /*!< [12..12] To enable comparator 2        */
15061       __IOM unsigned int CMP2_EN_FILTER : 1; /*!< [13..13] To enable filter for
15062                                             comparator 2 */
15063       __IOM unsigned int CMP2_HYST : 2;      /*!< [15..14] Programmability to control
15064                                        hysteresis of comparator2             */
15065       __IOM unsigned int CMP2_MUX_SEL_P : 4; /*!< [19..16] Select for positive input
15066                                             of comparator_2 */
15067       __IOM unsigned int CMP2_MUX_SEL_N : 4; /*!< [23..20] Select for negative input
15068                                             of comparator_2 */
15069       __IOM unsigned int COM_DYN_EN : 1;     /*!< [24..24] Dynamic enable for registers */
15070       __IOM unsigned int RESERVED1 : 7;      /*!< [31..25] Reserved1 */
15071     } COMPARATOR1_b;
15072   };
15073 
15074   union {
15075     __IOM unsigned int AUXADC_CONFIG_2; /*!< (@ 0x00000208) This register is AUX-ADC
15076                                        config2                           */
15077 
15078     struct {
15079       __IOM unsigned int AUXADC_INP_SEL : 5;    /*!< [4..0] Mux select for positive
15080                                             input of adc */
15081       __IOM unsigned int AUXADC_INN_SEL : 4;    /*!< [8..5] Mux select for negetive
15082                                             input of adc */
15083       __IOM unsigned int AUXADC_DIFF_MODE : 1;  /*!< [9..9] AUX ADC Differential Mode         */
15084       __IOM unsigned int AUXADC_ENABLE : 1;     /*!< [10..10] Static Enable */
15085       __IOM unsigned int AUXADC_DYN_ENABLE : 1; /*!< [11..11] Aux ADC Configuration Enable */
15086       __IOM unsigned int RESERVED2 : 20;        /*!< [31..12] Reserved2 */
15087     } AUXADC_CONFIG_2_b;
15088   };
15089 
15090   union {
15091     __IOM unsigned int AUXDAC_CONIG_1; /*!< (@ 0x0000020C) This register is AUX-DAC
15092                                       config1                           */
15093 
15094     struct {
15095       __IOM unsigned int AUXDAC_EN_S : 1;        /*!< [0..0] Enable signal DAC       */
15096       __IOM unsigned int AUXDAC_OUT_MUX_EN : 1;  /*!< [1..1] Aux OUT mux Enable */
15097       __IOM unsigned int AUXDAC_OUT_MUX_SEL : 1; /*!< [2..2] AUXDAC OUT MUX SELECT Enable   */
15098       __IOM unsigned int RESERVED1 : 1;          /*!< [3..3] Reserved1 */
15099       __IOM unsigned int AUXDAC_DATA_S : 10;     /*!< [13..4] Satatic AUX Dac Data */
15100       __IOM unsigned int AUXDAC_DYN_EN : 1;      /*!< [14..14] Satatic AUX Dac Data  */
15101       __IOM unsigned int RESERVED2 : 17;         /*!< [31..15] RESERVED2     */
15102     } AUXDAC_CONIG_1_b;
15103   };
15104 
15105   union {
15106     __IOM unsigned int AUX_LDO; /*!< (@ 0x00000210) This register is AUX-LDO configuration */
15107 
15108     struct {
15109       __IOM unsigned int LDO_CTRL : 4;         /*!< [3..0] Enable ldo control field */
15110       __IOM unsigned int LDO_DEFAULT_MODE : 1; /*!< [4..4] ldo default mode enable      */
15111       __IOM unsigned int BYPASS_LDO : 1;       /*!< [5..5] bypass the LDO */
15112       __IOM unsigned int ENABLE_LDO : 1;       /*!< [6..6] Turn LDO */
15113       __IOM unsigned int DYN_EN : 1;           /*!< [7..7] Dynamic Enable     */
15114       __IOM unsigned int RESERVED1 : 24;       /*!< [31..8] It is recommended to write
15115                                         these bits to 0. */
15116     } AUX_LDO_b;
15117   };
15118 } AUX_ADC_DAC_COMP_Type; /*!< Size = 532 (0x214) */
15119 
15120 /* ===========================================================================================================================
15121  */
15122 /* ================                                            IR
15123  * ================ */
15124 /* ===========================================================================================================================
15125  */
15126 
15127 /**
15128  * @brief IR Decoder are used for the decoding the external ir sensor input.
15129  * (IR)
15130  */
15131 
15132 typedef struct { /*!< (@ 0x24040C00) IR Structure */
15133 
15134   union {
15135     __IOM unsigned int IR_OFF_TIME_DURATION; /*!< (@ 0x00000000) This register used for IR
15136                                  sleep duration timer value. */
15137 
15138     struct {
15139       __IOM unsigned int IR_OFF_TIME_DURATION : 17; /*!< [16..0] This field define
15140                                                    ir off time */
15141       __IM unsigned int RES : 15;                   /*!< [31..17] reserved5                   */
15142     } IR_OFF_TIME_DURATION_b;
15143   };
15144 
15145   union {
15146     __IOM unsigned int IR_ON_TIME_DURATION; /*!< (@ 0x00000004) This register used for IR
15147                                 Detection duration timer value. */
15148 
15149     struct {
15150       __IOM unsigned int IR_ON_TIME_DURATION : 12; /*!< [11..0] This field define ir on time
15151                                        for ir detection on                  */
15152       __IM unsigned int RES : 20;                  /*!< [31..12] reserved5       */
15153     } IR_ON_TIME_DURATION_b;
15154   };
15155 
15156   union {
15157     __IOM unsigned int IR_FRAME_DONE_THRESHOLD; /*!< (@ 0x00000008) This register used count
15158                                     with respect to 32KHz clock after not more
15159                                     toggle are expected to a given pattern. */
15160 
15161     struct {
15162       __IOM unsigned int IR_FRAME_DONE_THRESHOLD : 15; /*!< [14..0] count with respect to 32KHz
15163                                           clock after not more toggle are
15164                                           expected to a given pattern */
15165       __IM unsigned int RES : 17;                      /*!< [31..15] reserved5           */
15166     } IR_FRAME_DONE_THRESHOLD_b;
15167   };
15168 
15169   union {
15170     __IOM unsigned int IR_DET_THRESHOLD; /*!< (@ 0x0000000C) This register used Minimum Number
15171                              of edges to detected during on-time failing which
15172                              IR detection is re-stated. */
15173 
15174     struct {
15175       __IOM unsigned int IR_DET_THRESHOLD : 7; /*!< [6..0] Minimum Number of edges to detected
15176                                    during on-time failing
15177                                           which IR detection is re-stated. */
15178       __IM unsigned int RES : 25;              /*!< [31..7] reserved5   */
15179     } IR_DET_THRESHOLD_b;
15180   };
15181 
15182   union {
15183     __IOM unsigned int IR_CONFIG; /*!< (@ 0x00000010) This register used to configure the ir
15184                       structure for application purpose. */
15185 
15186     struct {
15187       __IOM unsigned int EN_IR_DET : 1;      /*!< [0..0] Enable IR detection logic bit if bit 1 then
15188                             detection enable if 0 then not enable. */
15189       __IOM unsigned int IR_DET_RSTART : 1;  /*!< [1..1] Enable IR detection re-start logic bit
15190                                 if bit 1 then re-start. */
15191       __IOM unsigned int EN_CLK_IR_CORE : 1; /*!< [2..2] Enable 32KHz clock to IR Core bit ,if
15192                                  bit 1 then clock gating disable and bit is 0
15193                                  then clock gating Enable */
15194       __IM unsigned int RES : 5;             /*!< [7..3] reserved5  */
15195       __IOM unsigned int EN_CONT_IR_DET : 1; /*!< [8..8] This bit is Enable continues IR
15196                                  detection,When enabled there will be no power
15197                                  cycling on External IR Sensor. */
15198       __IM unsigned int RES1 : 7;            /*!< [15..9] reserved6 */
15199       __IOM unsigned int SREST_IR_CORE : 1;  /*!< [16..16] This bit is used soft
15200                                            reset IR core block */
15201       __IM unsigned int RES2 : 15;           /*!< [31..17] reserved7          */
15202     } IR_CONFIG_b;
15203   };
15204 
15205   union {
15206     __IOM unsigned int IR_MEM_ADDR_ACCESS; /*!< (@ 0x00000014) This register used to access
15207                                memory address for application purpose. */
15208 
15209     struct {
15210       __IOM unsigned int IR_MEM_ADDR : 7;         /*!< [6..0] This field is used to IR read
15211                                           address.                             */
15212       __IOM unsigned int RES : 1;                 /*!< [7..7] reserved5          */
15213       __IOM unsigned int IR_MEM_WR_EN : 1;        /*!< [8..8] IR memory write enable. */
15214       __IOM unsigned int IR_MEM_RD_EN : 1;        /*!< [9..9] This field used to IR memory
15215                                           read enable. */
15216       __IOM unsigned int RES1 : 6;                /*!< [15..10] reserved1         */
15217       __IOM unsigned int IR_MEM_WR_TEST_MODE : 1; /*!< [16..16] IR memory write
15218                                                  enable in test mode.. */
15219       __IOM unsigned int RES2 : 15;               /*!< [31..17] reserved2               */
15220     } IR_MEM_ADDR_ACCESS_b;
15221   };
15222 
15223   union {
15224     __IM unsigned int IR_MEM_READ; /*!< (@ 0x00000018) This register used to IR Read
15225                                   data from memory.            */
15226 
15227     struct {
15228       __IM unsigned int IR_MEM_DATA_OUT : 16;  /*!< [15..0] This field is used to IR
15229                                              Read data from memory. */
15230       __IM unsigned int RES : 8;               /*!< [23..16] reserved5              */
15231       __IM unsigned int IR_DATA_MEM_DEPTH : 7; /*!< [30..24] This field used to indicated
15232                                     valid number of IR Address
15233                                            in the memory to be read. */
15234       __IM unsigned int RES1 : 1;              /*!< [31..31] reserved6    */
15235     } IR_MEM_READ_b;
15236   };
15237 } IR_Type; /*!< Size = 28 (0x1c) */
15238 
15239 /* ===========================================================================================================================
15240  */
15241 /* ================                                            CTS
15242  * ================ */
15243 /* ===========================================================================================================================
15244  */
15245 
15246 /**
15247   * @brief The capacitive touch sensor (CTS) controller is used to detect the
15248   position of the touch from the user on the capacitive touch screen (CTS)
15249   */
15250 
15251 typedef struct { /*!< (@ 0x24042C00) CTS Structure */
15252 
15253   union {
15254     __IOM unsigned int CTS_CONFIG_REG_0_0; /*!< (@ 0x00000000) Configuration Register 0_0 */
15255 
15256     struct {
15257       __IOM unsigned int CLK_SEL1 : 2;          /*!< [1..0] Mux select for clock_mux_1 */
15258       __IOM unsigned int PRE_SCALAR_1 : 8;      /*!< [9..2] Division factor for clock divider */
15259       __IOM unsigned int PRE_SCALAR_2 : 4;      /*!< [13..10] Division factor for clock divider */
15260       __IOM unsigned int CLK_SEL2 : 1;          /*!< [14..14] Mux select for clock_mux_2 */
15261       __IOM unsigned int CTS_STATIC_CLK_EN : 1; /*!< [15..15] Enable static for
15262                                                capacitive touch sensor */
15263       __IOM unsigned int FIFO_AFULL_THRLD : 6;  /*!< [21..16] Threshold for fifo afull */
15264       __IOM unsigned int FIFO_AEMPTY_THRLD : 6; /*!< [27..22] Threshold for fifo aempty    */
15265       __IM unsigned int FIFO_EMPTY : 1;         /*!< [28..28] FIFO empty status bit */
15266       __IM unsigned int RESERVED1 : 3;          /*!< [31..29] Reserved1  */
15267     } CTS_CONFIG_REG_0_0_b;
15268   };
15269 
15270   union {
15271     __IOM unsigned int CTS_FIFO_ADDRESS; /*!< (@ 0x00000004) FIFO Address Register */
15272 
15273     struct {
15274       __IOM unsigned int FIFO : 32; /*!< [31..0] Used for FIFO reads and write operations */
15275     } CTS_FIFO_ADDRESS_b;
15276   };
15277   __IM unsigned int RESERVED[62];
15278 
15279   union {
15280     __IOM unsigned int CTS_CONFIG_REG_1_1; /*!< (@ 0x00000100) Configuration Register 1_1 */
15281 
15282     struct {
15283       __IOM unsigned int POLYNOMIAL_LEN : 2;  /*!< [1..0] Length of polynomial */
15284       __IOM unsigned int SEED_LOAD : 1;       /*!< [2..2] Seed of polynomial      */
15285       __IOM unsigned int BUFFER_DELAY : 5;    /*!< [7..3] Delay of buffer. Delay programmed will
15286                                be equal to delay in nano seconds.  Max delay
15287                                value is 32.Default delay should be programmed
15288                                before using Capacitive touch sensor module. */
15289       __IOM unsigned int WAKE_UP_ACK : 1;     /*!< [8..8] Ack for wake up interrupt. This is a
15290                               level signal. To acknowledge wake up , set this
15291                               bit to one and reset it
15292                                          . */
15293       __IOM unsigned int ENABLE1 : 1;         /*!< [9..9] Enable signal      */
15294       __IOM unsigned int SOFT_RESET_2 : 1;    /*!< [10..10] Reset the FIFO write and
15295                                           FIFO read occupancy pointers */
15296       __IOM unsigned int CNT_ONEHOT_MODE : 1; /*!< [11..11] Continuous or One hot mode */
15297       __IOM unsigned int SAMPLE_MODE : 2;     /*!< [13..12] Select bits for FIFO write
15298                                          and FIFO average */
15299       __IOM unsigned int RESET_WR_FIFO : 1;   /*!< [14..14] Resets the signal fifo_wr_int      */
15300       __OM unsigned int BYPASS : 1;           /*!< [15..15] Bypass signal   */
15301       __IOM unsigned int BIT_SEL : 2;         /*!< [17..16] Selects different set of 12 bits
15302                                      to be stored in FIFO            */
15303       __IOM unsigned int EXT_TRIG_SEL : 1;    /*!< [18..18] Select bit for NPSS clock
15304                                           or Enable */
15305       __IOM unsigned int EXT_TRIG_EN : 1;     /*!< [19..19] Select bit for NPSS clock or
15306                                          Enable                              */
15307       __IOM unsigned int RESERVED2 : 12;      /*!< [31..20] Reserved2  */
15308     } CTS_CONFIG_REG_1_1_b;
15309   };
15310 
15311   union {
15312     __IOM unsigned int CTS_CONFIG_REG_1_2; /*!< (@ 0x00000104) Configuration Register 1_2 */
15313 
15314     struct {
15315       __IOM unsigned int PWM_ON_PERIOD : 16;  /*!< [15..0] PWM ON period  */
15316       __IOM unsigned int PWM_OFF_PERIOD : 16; /*!< [31..16] PWM OFF period */
15317     } CTS_CONFIG_REG_1_2_b;
15318   };
15319 
15320   union {
15321     __IOM unsigned int CTS_CONFIG_REG_1_3; /*!< (@ 0x00000108) Configuration Register 1_3 */
15322 
15323     struct {
15324       __IOM unsigned int PRS_SEED : 32; /*!< [31..0] Pseudo random generator (PRS)
15325                                        seed value                          */
15326     } CTS_CONFIG_REG_1_3_b;
15327   };
15328 
15329   union {
15330     __IOM unsigned int CTS_CONFIG_REG_1_4; /*!< (@ 0x0000010C) Configuration Register 1_4 */
15331 
15332     struct {
15333       __IOM unsigned int PRS_POLY : 32; /*!< [31..0] Polynomial programming register
15334                                        for PRS generator                 */
15335     } CTS_CONFIG_REG_1_4_b;
15336   };
15337 
15338   union {
15339     __IOM unsigned int CTS_CONFIG_REG_1_5; /*!< (@ 0x00000110) Configuration Register 1_5 */
15340 
15341     struct {
15342       __IOM unsigned int INTER_SENSOR_DELAY : 16; /*!< [15..0] Inter-sensor scan
15343                                                  delay value */
15344       __IOM unsigned int N_SAMPLE_COUNT : 16;     /*!< [31..16] Number of repetitions of
15345                                              sensor scan */
15346     } CTS_CONFIG_REG_1_5_b;
15347   };
15348 
15349   union {
15350     __IOM unsigned int CTS_CONFIG_REG_1_6; /*!< (@ 0x00000114) Configuration Register 1_6 */
15351 
15352     struct {
15353       __IOM unsigned int SENSOR_CFG : 32; /*!< [31..0] Register of scan controller
15354                                          containing the programmed bit map */
15355     } CTS_CONFIG_REG_1_6_b;
15356   };
15357 
15358   union {
15359     __IOM unsigned int CTS_CONFIG_REG_1_7; /*!< (@ 0x00000118) Configuration Register 1_7 */
15360 
15361     struct {
15362       __IOM unsigned int VALID_SENSORS : 4;      /*!< [3..0] Value of number of sensors
15363                                            valid in the bit map */
15364       __IOM unsigned int RESERVED1 : 2;          /*!< [5..4] Reserved1     */
15365       __IOM unsigned int REF_VOLT_CONFIG : 9;    /*!< [14..6] This is given as an input voltage to
15366                                   analog model as
15367                                           comparator reference voltage. */
15368       __IOM unsigned int WAKEUP_MODE : 1;        /*!< [15..15] Select bit for high/low mode. */
15369       __IOM unsigned int WAKE_UP_THRESHOLD : 16; /*!< [31..16] Wakeup threshold. */
15370     } CTS_CONFIG_REG_1_7_b;
15371   };
15372 
15373   union {
15374     __IM unsigned int CTS_CONFIG_REG_1_8; /*!< (@ 0x0000011C) Configuration Register 1_8 */
15375 
15376     struct {
15377       __IM unsigned int PRS_STATE : 32; /*!< [31..0] Current state of PRS */
15378     } CTS_CONFIG_REG_1_8_b;
15379   };
15380 
15381   union {
15382     __IOM unsigned int CTS_CONFIG_REG_1_9; /*!< (@ 0x00000120) Configuration Register 1_9 */
15383 
15384     struct {
15385       __IOM unsigned int TRIG_DIV : 10;  /*!< [9..0] Allows one pulse for every 'trig_div' no.
15386                             of pulses of 1 ms clock */
15387       __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */
15388     } CTS_CONFIG_REG_1_9_b;
15389   };
15390 } CTS_Type; /*!< Size = 292 (0x124) */
15391 
15392 /* ===========================================================================================================================
15393  */
15394 /* ================                                        MISC_CONFIG
15395  * ================ */
15396 /* ===========================================================================================================================
15397  */
15398 
15399 /**
15400  * @brief MISC CONFIG Register (MISC_CONFIG)
15401  */
15402 
15403 typedef struct { /*!< (@ 0x46008000) MISC_CONFIG Structure */
15404 
15405   union {
15406     __IOM unsigned int MISC_CFG_HOST_INTR_MASK; /*!< (@ 0x00000000) MISC CFG HOST
15407                                                INTR MASK */
15408 
15409     struct {
15410       __IOM unsigned int HOST_INTR_MSK : 8;                 /*!< [7..0] Writing 1 in any bit masks
15411                                            the corresponding interrupt in
15412                                            HOST_INTR_STATUS. */
15413       __IOM unsigned int HOST_SPI_INTR_OPEN_DRAIN_MODE : 1; /*!< [8..8] Writing 1 to this bit
15414                                                 configures the host SPI
15415                                                 interrupt in open drain mode.
15416                                                 When open drain mode is enabled
15417                                                 and interrupt is configured in
15418                                                 active high mode,  external
15419                                                        PULLDOWN has to be used
15420                                                 on the board. */
15421       __IOM
15422       unsigned int HOST_SPI_INTR_ACTIVE_LOW_MODE : 1; /*!< [9..9] Writing 1 to this
15423                                                     bit configures the host SPI
15424                                                     interrupt in active low
15425                                                     mode. By default, it will be
15426                                                     active high. */
15427       __IOM unsigned int RESERVED1 : 22;              /*!< [31..10] reserved1             */
15428     } MISC_CFG_HOST_INTR_MASK_b;
15429   };
15430 } MISC_CONFIG_Type; /*!< Size = 4 (0x4) */
15431 
15432 #if defined(SLI_SI917B0) || defined(SLI_SI915)
15433 /**************************************************************************/ /**
15434                                                                               * @defgroup RSI_DEVICE_SYSRTC SYSRTC
15435                                                                               * @{
15436                                                                               * @brief RSI_DEVICE SYSRTC Register Declaration.
15437                                                                               *****************************************************************************/
15438 
15439 /** SYSRTC Register Declaration. */
15440 typedef struct {
15441   __IM unsigned int IPVERSION;           /**< IP VERSION */
15442   __IOM unsigned int EN;                 /**< Module Enable Register                             */
15443   __IOM unsigned int SWRST;              /**< Software Reset Register */
15444   __IOM unsigned int CFG;                /**< Configuration Register                             */
15445   __IOM unsigned int CMD;                /**< Command Register                                   */
15446   __IM unsigned int STATUS;              /**< Status register */
15447   __IOM unsigned int CNT;                /**< Counter Value Register                             */
15448   __IM unsigned int SYNCBUSY;            /**< Synchronization Busy Register            */
15449   __IOM unsigned int LOCK;               /**< Configuration Lock Register               */
15450   unsigned int RESERVED0[3U];            /**< Reserved for future use            */
15451   __IOM unsigned int FAILDETCTRL;        /**< Failure Detection        */
15452   __IOM unsigned int FAILDETLOCK;        /**< FAILDET Lock Register        */
15453   unsigned int RESERVED1[2U];            /**< Reserved for future use            */
15454   __IOM unsigned int GRP0_IF;            /**< Group Interrupt Flags            */
15455   __IOM unsigned int GRP0_IEN;           /**< Group Interrupt Enables           */
15456   __IOM unsigned int GRP0_CTRL;          /**< Group Control Register          */
15457   __IOM unsigned int GRP0_CMP0VALUE;     /**< Compare 0 Value Register     */
15458   __IOM unsigned int GRP0_CMP1VALUE;     /**< Compare 1 Value Register     */
15459   __IM unsigned int GRP0_CAP0VALUE;      /**< Capture 0 Value Register      */
15460   __IM unsigned int GRP0_SYNCBUSY;       /**< Synchronization busy Register       */
15461   unsigned int RESERVED2[1U];            /**< Reserved for future use            */
15462   __IOM unsigned int GRP1_IF;            /**< Group Interrupt Flags            */
15463   __IOM unsigned int GRP1_IEN;           /**< Group Interrupt Enables           */
15464   __IOM unsigned int GRP1_CTRL;          /**< Group Control Register          */
15465   __IOM unsigned int GRP1_CMP0VALUE;     /**< Compare 0 Value Register     */
15466   __IOM unsigned int GRP1_CMP1VALUE;     /**< Compare 1 Value Register     */
15467   __IM unsigned int GRP1_CAP0VALUE;      /**< Capture 0 Value Register      */
15468   __IM unsigned int GRP1_SYNCBUSY;       /**< Synchronization busy Register       */
15469   unsigned int RESERVED3[33U];           /**< GRP2 - GRP7,Reserved for future use           */
15470   __IM unsigned int IPVERSION_SET;       /**< IP VERSION       */
15471   __IOM unsigned int EN_SET;             /**< Module Enable Register             */
15472   __IOM unsigned int SWRST_SET;          /**< Software Reset Register          */
15473   __IOM unsigned int CFG_SET;            /**< Configuration Register            */
15474   __IOM unsigned int CMD_SET;            /**< Command Register            */
15475   __IM unsigned int STATUS_SET;          /**< Status register          */
15476   __IOM unsigned int CNT_SET;            /**< Counter Value Register            */
15477   __IM unsigned int SYNCBUSY_SET;        /**< Synchronization Busy Register        */
15478   __IOM unsigned int LOCK_SET;           /**< Configuration Lock Register           */
15479   unsigned int RESERVED4[3U];            /**< Reserved for future use            */
15480   __IOM unsigned int FAILDETCTRL_SET;    /**< Failure Detection    */
15481   __IOM unsigned int FAILDETLOCK_SET;    /**< FAILDET Lock Register    */
15482   unsigned int RESERVED5[2U];            /**< Reserved for future use            */
15483   __IOM unsigned int GRP0_IF_SET;        /**< Group Interrupt Flags        */
15484   __IOM unsigned int GRP0_IEN_SET;       /**< Group Interrupt Enables       */
15485   __IOM unsigned int GRP0_CTRL_SET;      /**< Group Control Register      */
15486   __IOM unsigned int GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */
15487   __IOM unsigned int GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */
15488   __IM unsigned int GRP0_CAP0VALUE_SET;  /**< Capture 0 Value Register  */
15489   __IM unsigned int GRP0_SYNCBUSY_SET;   /**< Synchronization busy Register   */
15490   unsigned int RESERVED6[1U];            /**< Reserved for future use            */
15491   __IOM unsigned int GRP1_IF_SET;        /**< Group Interrupt Flags        */
15492   __IOM unsigned int GRP1_IEN_SET;       /**< Group Interrupt Enables       */
15493   __IOM unsigned int GRP1_CTRL_SET;      /**< Group Control Register      */
15494   __IOM unsigned int GRP1_CMP0VALUE_SET; /**< Compare 0 Value Register */
15495   __IOM unsigned int GRP1_CMP1VALUE_SET; /**< Compare 1 Value Register */
15496   __IM unsigned int GRP1_CAP0VALUE_SET;  /**< Capture 0 Value Register  */
15497   __IM unsigned int GRP1_SYNCBUSY_SET;   /**< Synchronization busy Register   */
15498   unsigned int RESERVED7[33U];           /**< Reserved for future use           */
15499   __IM unsigned int IPVERSION_CLR;       /**< IP VERSION       */
15500   __IOM unsigned int EN_CLR;             /**< Module Enable Register             */
15501   __IOM unsigned int SWRST_CLR;          /**< Software Reset Register          */
15502   __IOM unsigned int CFG_CLR;            /**< Configuration Register            */
15503   __IOM unsigned int CMD_CLR;            /**< Command Register            */
15504   __IM unsigned int STATUS_CLR;          /**< Status register          */
15505   __IOM unsigned int CNT_CLR;            /**< Counter Value Register            */
15506   __IM unsigned int SYNCBUSY_CLR;        /**< Synchronization Busy Register        */
15507   __IOM unsigned int LOCK_CLR;           /**< Configuration Lock Register           */
15508   unsigned int RESERVED8[3U];            /**< Reserved for future use            */
15509   __IOM unsigned int FAILDETCTRL_CLR;    /**< Failure Detection    */
15510   __IOM unsigned int FAILDETLOCK_CLR;    /**< FAILDET Lock Register    */
15511   unsigned int RESERVED9[2U];            /**< Reserved for future use            */
15512   __IOM unsigned int GRP0_IF_CLR;        /**< Group Interrupt Flags        */
15513   __IOM unsigned int GRP0_IEN_CLR;       /**< Group Interrupt Enables       */
15514   __IOM unsigned int GRP0_CTRL_CLR;      /**< Group Control Register      */
15515   __IOM unsigned int GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */
15516   __IOM unsigned int GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */
15517   __IM unsigned int GRP0_CAP0VALUE_CLR;  /**< Capture 0 Value Register  */
15518   __IM unsigned int GRP0_SYNCBUSY_CLR;   /**< Synchronization busy Register   */
15519   unsigned int RESERVED10[1U];           /**< Reserved for future use           */
15520   __IOM unsigned int GRP1_IF_CLR;        /**< Group Interrupt Flags        */
15521   __IOM unsigned int GRP1_IEN_CLR;       /**< Group Interrupt Enables       */
15522   __IOM unsigned int GRP1_CTRL_CLR;      /**< Group Control Register      */
15523   __IOM unsigned int GRP1_CMP0VALUE_CLR; /**< Compare 0 Value Register */
15524   __IOM unsigned int GRP1_CMP1VALUE_CLR; /**< Compare 1 Value Register */
15525   __IM unsigned int GRP1_CAP0VALUE_CLR;  /**< Capture 0 Value Register  */
15526   __IM unsigned int GRP1_SYNCBUSY_CLR;   /**< Synchronization busy Register   */
15527   unsigned int RESERVED11[33U];          /**< Reserved for future use          */
15528   __IM unsigned int IPVERSION_TGL;       /**< IP VERSION       */
15529   __IOM unsigned int EN_TGL;             /**< Module Enable Register             */
15530   __IOM unsigned int SWRST_TGL;          /**< Software Reset Register          */
15531   __IOM unsigned int CFG_TGL;            /**< Configuration Register            */
15532   __IOM unsigned int CMD_TGL;            /**< Command Register            */
15533   __IM unsigned int STATUS_TGL;          /**< Status register          */
15534   __IOM unsigned int CNT_TGL;            /**< Counter Value Register            */
15535   __IM unsigned int SYNCBUSY_TGL;        /**< Synchronization Busy Register        */
15536   __IOM unsigned int LOCK_TGL;           /**< Configuration Lock Register           */
15537   unsigned int RESERVED12[3U];           /**< Reserved for future use           */
15538   __IOM unsigned int FAILDETCTRL_TGL;    /**< Failure Detection    */
15539   __IOM unsigned int FAILDETLOCK_TGL;    /**< FAILDET Lock Register    */
15540   unsigned int RESERVED13[2U];           /**< Reserved for future use           */
15541   __IOM unsigned int GRP0_IF_TGL;        /**< Group Interrupt Flags        */
15542   __IOM unsigned int GRP0_IEN_TGL;       /**< Group Interrupt Enables       */
15543   __IOM unsigned int GRP0_CTRL_TGL;      /**< Group Control Register      */
15544   __IOM unsigned int GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */
15545   __IOM unsigned int GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */
15546   __IM unsigned int GRP0_CAP0VALUE_TGL;  /**< Capture 0 Value Register  */
15547   __IM unsigned int GRP0_SYNCBUSY_TGL;   /**< Synchronization busy Register   */
15548   unsigned int RESERVED14[1U];           /**< Reserved for future use           */
15549   __IOM unsigned int GRP1_IF_TGL;        /**< Group Interrupt Flags        */
15550   __IOM unsigned int GRP1_IEN_TGL;       /**< Group Interrupt Enables       */
15551   __IOM unsigned int GRP1_CTRL_TGL;      /**< Group Control Register      */
15552   __IOM unsigned int GRP1_CMP0VALUE_TGL; /**< Compare 0 Value Register */
15553   __IOM unsigned int GRP1_CMP1VALUE_TGL; /**< Compare 1 Value Register */
15554   __IM unsigned int GRP1_CAP0VALUE_TGL;  /**< Capture 0 Value Register  */
15555   __IM unsigned int GRP1_SYNCBUSY_TGL;   /**< Synchronization busy Register   */
15556   unsigned int RESERVED15[32U];          /**< Reserved for future use          */
15557   __IOM unsigned int MCUSYSRTC_REG1;     /**< input and output configuration     */
15558 
15559 } SYSRTC_TypeDef;
15560 
15561 /* =========================================================================================================================== */
15562 /* ================                                            SDC                                            ================ */
15563 /* =========================================================================================================================== */
15564 
15565 /**
15566   * @brief SDC_SDC_DATA_REG [SDC_DATA_REG] (SDC Data registers (0-15))
15567   */
15568 typedef struct {
15569   union {
15570     __IM unsigned int DATA_REG; /*!< (@ 0x00000000) SDC Data register                                          */
15571 
15572     struct {
15573       __IM unsigned int
15574         SDC_DATA_SAMPLE : 12;          /*!< [11..0] Sample 0 collected from Sensor through Aux ADC.                   */
15575       __IM unsigned int SMP_ID_CH : 2; /*!< [13..12] Channel iD for sample                                            */
15576       __IM unsigned int
15577         RESERVED1 : 18; /*!< [31..14] reserved1                                                        */
15578     } DATA_REG_b;
15579   };
15580 } SDC_SDC_DATA_REG_Type;
15581 
15582 /**
15583   * @brief Sensor Data Collector Register structure (SDC)
15584   */
15585 
15586 typedef struct { /*!< (@ 0x24042400) SDC Structure                                              */
15587 
15588   union {
15589     __IOM unsigned int
15590       SDC_GEN_CONFIG_0; /*!< (@ 0x00000000) SDC general configuration 0                                */
15591 
15592     struct {
15593       __IOM unsigned int INTR_STATUS_CLEAR : 1; /*!< [0..0] Writing 1 clears interrupt, reading gives SDC Interrupt
15594                                                      status                                                                    */
15595       __IOM unsigned int
15596         RESERVED1 : 31; /*!< [31..1] Reserevd                                                          */
15597     } SDC_GEN_CONFIG_0_b;
15598   };
15599 
15600   union {
15601     __IOM unsigned int
15602       SDC_GEN_CONFIG_1; /*!< (@ 0x00000004) SDC general configuration 1                                */
15603 
15604     struct {
15605       __IOM unsigned int RST_WRT_PTR : 1; /*!< [0..0] Writing 1 will resets the write pointer so that new samples
15606                                                      can be filled in Buffer.                                                  */
15607       __IM unsigned int WRT_PTR : 4; /*!< [4..1] Write pointer Value                                                */
15608       __IOM unsigned int SAMP_THRESH : 4; /*!< [8..5] Number of data sampled to be collected from Aux-ADC and
15609                                                      stored in Buffer before interrupt is raised/wakeup is initialed           */
15610       __IOM unsigned int
15611         RESERVED1 : 23; /*!< [31..9] Reserevd                                                          */
15612     } SDC_GEN_CONFIG_1_b;
15613   };
15614 
15615   union {
15616     __IOM unsigned int
15617       SDC_GEN_CONFIG_2; /*!< (@ 0x00000008) SDC general configuration 2                                */
15618 
15619     struct {
15620       __IOM unsigned int
15621         SDC_SAMP_EN : 1; /*!< [0..0] SDC Data Sampling mode                                             */
15622       __IOM unsigned int
15623         NUM_CH_SEL : 3; /*!< [3..1] Number of Channels to be used                                      */
15624       __IOM unsigned int
15625         RESERVED1 : 28; /*!< [31..4] Reserevd                                                          */
15626     } SDC_GEN_CONFIG_2_b;
15627   };
15628 
15629   union {
15630     __IOM unsigned int
15631       SDC_GEN_CONFIG_3; /*!< (@ 0x00000014) SDC general configuration 3                                */
15632 
15633     struct {
15634       __IOM unsigned int
15635         SAMP_TRIG_SEL : 1; /*!< [0..0] select the trigger event on which AUX-ADC Data is sampled          */
15636       __IOM unsigned int
15637         CNT_TRIG_EVNT : 10; /*!< [10..1] which trigger event AUX-ADC Data will sampled                     */
15638       __IOM unsigned int
15639         SDC_CLK_DIV : 10; /*!< [20..11] SDCSS clock division factor                                      */
15640       __IOM unsigned int
15641         RESERVED1 : 11; /*!< [31..21] Reserevd                                                         */
15642     } SDC_GEN_CONFIG_3_b;
15643   };
15644   __IM unsigned int RESERVED[2];
15645   union {
15646     __IOM unsigned int
15647       SDC_AUXADC_CONFIG_1; /*!< (@ 0x00000018) SDC AUX ADC configuration 1                                */
15648 
15649     struct {
15650       __IOM unsigned int
15651         SDC_AUXADC_INPUT_P_SEL_CH1 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-1               */
15652       __IOM unsigned int
15653         SDC_AUXADC_INPUT_N_SEL_CH1 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-1               */
15654       __IOM unsigned int
15655         SDC_AUXADC_DIFF_MODE_CH1 : 1; /*!< [9..9] Enable Differential Mode in AUX ADC for Channel -1               */
15656       __IOM unsigned int
15657         SDC_AUXADC_EN : 1; /*!< [10..10] AUXADC Enable from SDC Block                                     */
15658       __IOM unsigned int SDC_ADC_CONFIG_EN : 1; /*!< [11..11] On Enabling this register, SDC ADC Configuration will
15659                                                      be Applied.                                                               */
15660       __IOM unsigned int
15661         RESERVED1 : 20; /*!< [31..12] Reserevd                                                         */
15662     } SDC_AUXADC_CONFIG_1_b;
15663   };
15664 
15665   union {
15666     __IOM unsigned int
15667       SDC_AUXDAC_CONFIG_1; /*!< (@ 0x0000001C) SDC AUX DAC configuration 1                                */
15668 
15669     struct {
15670       __IOM unsigned int
15671         SDC_DAC_EN : 1; /*!< [0..0] Enable signal DAC                                                  */
15672       __IOM unsigned int
15673         SDC_DAC_OUT_MUX_EN : 1; /*!< [1..1] Enable signal for Connecting DAC Output to GPIO                    */
15674       __IOM unsigned int SDC_DAC_OUT_MUX_SEL : 1; /*!< [2..2] Programming register for choosing GPIO in which DAC Output
15675                                                      is connected                                                              */
15676       __IOM unsigned int
15677         RESERVED1 : 1; /*!< [3..3] Reserved                                                           */
15678       __IOM unsigned int
15679         SDC_DAC_DATA : 10; /*!< [13..4] SDC Aux DAC Data                                                  */
15680       __IOM unsigned int SDC_DAC_CONFIG_EN : 1; /*!< [14..14] On Enabling this register, SDC DAC Configuration will
15681                                                      be Applied.                                                               */
15682       __IOM unsigned int
15683         RESERVED2 : 17; /*!< [31..15] Reserevd                                                         */
15684     } SDC_AUXDAC_CONFIG_1_b;
15685   };
15686 
15687   union {
15688     __IOM unsigned int
15689       SDC_AUXLDO_CONFIG; /*!< (@ 0x00000020) SDC AUX LDO configuration                                  */
15690 
15691     struct {
15692       __IOM unsigned int
15693         SDC_AUXLDO_VOLT_CTRL : 4; /*!< [3..0] SDC AUX LDO Voltage Control Selection                              */
15694       __IOM unsigned int
15695         RESERVED1 : 1; /*!< [4..4] RESERVED                                                           */
15696       __IOM unsigned int SDC_AUXLDO_BYP_EB : 1; /*!< [5..5] Configure AUXLDO in Buypass mode.When Enabled, Ouput
15697                                                      supply of LDO will be same as Input supply.                               */
15698       __IOM unsigned int
15699         SDC_AUXLDO_EN : 1; /*!< [6..6] Turn-On AUX LDO                                                    */
15700       __IOM unsigned int
15701         SDC_AUXLDO_CONFIG_EN : 1; /*!< [7..7] SDC Aux LDO Configuration Control Enable                           */
15702       __IOM unsigned int
15703         RESERVED2 : 24; /*!< [31..8] Reserved                                                          */
15704     } SDC_AUXLDO_CONFIG_b;
15705   };
15706 
15707   union {
15708     __IOM unsigned int
15709       SDC_AUXOPAMP_CONFIG_1; /*!< (@ 0x00000024) SDC AUX OPAMP configuration 1                              */
15710 
15711     struct {
15712       __IOM unsigned int SDC_OPAMP_EN_CH1 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-1
15713                                                      Operation                                                                 */
15714       __IOM unsigned int
15715         SDC_OPAMP_LP_MODE : 1; /*!< [1..1] Configuration of OPAMP1 Operation mode                             */
15716       __IOM unsigned int
15717         SDC_OPAMP_R1_SEL : 2; /*!< [3..2] Configuration for Resistor Ladder R1 of OPAMP1 for controlling
15718                                                      it gain.                                                                  */
15719       __IOM unsigned int
15720         SDC_OPAMP_R2_SEL : 3; /*!< [6..4] Configuration for Resistor Ladder R2 of OPAMP1 for controlling
15721                                                      it gain.                                                                  */
15722       __IOM unsigned int SDC_OPAMP_RES_BACK_EN : 1; /*!< [7..7] Configuration register for controlling Resistor Bank
15723                                                      of OPAMP                                                                  */
15724       __IOM unsigned int
15725         SDC_OPAMP_RES_MUX_SEL : 3; /*!< [10..8] Configuration register for Connecting R1 Resistor Ladder
15726                                                      input                                                                     */
15727       __IOM unsigned int
15728         SDC_OPAMP_RES_TO_OUT_VDD : 1; /*!< [11..11] Configuration register for Connecting R2 Resistor Ladder
15729                                                      input                                                                     */
15730       __IOM unsigned int
15731         SDC_OPAMP_OUT_MUX_EN : 1; /*!< [12..12] Configur this register to OPAMP1 Output will be connected
15732                                                      to GPIO                                                                   */
15733       __IOM unsigned int
15734         SDC_OPAMP_IN_N_SEL : 3; /*!< [15..13] Configuration register for selecting N Input of OPAMP1.          */
15735       __IOM unsigned int
15736         SDC_OPAMP_IN_P_SEL_CH1 : 4; /*!< [19..16] Configuration register for selecting P Input of OPAMP1.,for
15737                                                      CH1                                                                       */
15738       __IOM unsigned int SDC_OPAMP_OUT_MUX_SEL : 1; /*!< [20..20] Configuration register for connecting OPAMP1 output
15739                                                      to GPIO                                                                   */
15740       __IM unsigned int RESERVED1 : 1; /*!< [21..21] Reserved                                                         */
15741       __IOM unsigned int SDC_VREF_MUX_1_EN : 1; /*!< [22..22] Connect Low Drive Strength voltage reference for ULP
15742                                                      GPIO 1 For external use                                                   */
15743       __IOM unsigned int SDC_VREF_MUX_2_EN : 1; /*!< [23..23] Connect Low Drive Strength voltage reference for ULP
15744                                                      GPIO 3 For external use                                                   */
15745       __IOM unsigned int SDC_VREF_MUX_3_EN : 1; /*!< [24..24] Connect Low Drive Strength voltage reference for ULP
15746                                                      GPIO 4 For external use                                                   */
15747       __IOM unsigned int SDC_VREF_MUX_4_EN : 1; /*!< [25..25] Connect Low Drive Strength voltage reference for ULP
15748                                                      GPIO 15 For external use                                                  */
15749       __IOM unsigned int
15750         RESERVED2 : 1; /*!< [26..26] Reserved                                                         */
15751       __IOM unsigned int SDC_VREF_MUX_1_SEL : 1;  /*!< [27..27] Selection register for choosing Voltage reference to
15752                                                      external use on ULP_GPIO_1                                                */
15753       __IOM unsigned int SDC_VREF_MUX_2_SEL : 1;  /*!< [28..28] Selection register for choosing Voltage reference to
15754                                                      external use on ULP_GPIO_3                                                */
15755       __IOM unsigned int SDC_VREF_MUX_3_SEL : 1;  /*!< [29..29] Selection register for choosing Voltage reference to
15756                                                      external use on ULP_GPIO_4                                                */
15757       __IOM unsigned int SDC_VREF_MUX_4_SEL : 1;  /*!< [30..30] Selection register for choosing Voltage reference to
15758                                                      external use on ULP_GPIO_15                                               */
15759       __IOM unsigned int SDC_OPAMP_CONFIG_EN : 1; /*!< [31..31] On Enabling this register, SDC OPAMP Configuration
15760                                                      will be Applied.                                                          */
15761     } SDC_AUXOPAMP_CONFIG_1_b;
15762   };
15763 
15764   union {
15765     __IOM unsigned int
15766       SDC_AUXADC_CONFIG_2; /*!< (@ 0x00000028) SDC AUX ADC configuration 2                                */
15767 
15768     struct {
15769       __IOM unsigned int
15770         SDC_AUXADC_INPUT_P_SEL_CH2 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-2               */
15771       __IOM unsigned int
15772         SDC_AUXADC_INPUT_N_SEL_CH2 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-2               */
15773       __IOM unsigned int
15774         SDC_AUXADC_DIFF_MODE_CH2 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode               */
15775       __IOM unsigned int
15776         RESERVED1 : 22; /*!< [31..10] Reserevd                                                         */
15777     } SDC_AUXADC_CONFIG_2_b;
15778   };
15779 
15780   union {
15781     __IOM unsigned int
15782       SDC_AUXADC_CONFIG_3; /*!< (@ 0x0000002C) SDC AUX ADC configuration 3                                */
15783 
15784     struct {
15785       __IOM unsigned int
15786         SDC_AUXADC_INPUT_P_SEL_CH3 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-3               */
15787       __IOM unsigned int
15788         SDC_AUXADC_INPUT_N_SEL_CH3 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-3               */
15789       __IOM unsigned int
15790         SDC_AUXADC_DIFF_MODE_CH3 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode               */
15791       __IOM unsigned int
15792         RESERVED1 : 22; /*!< [31..10] Reserved                                                         */
15793     } SDC_AUXADC_CONFIG_3_b;
15794   };
15795 
15796   union {
15797     __IOM unsigned int
15798       SDC_AUXADC_CONFIG_4; /*!< (@ 0x00000030) SDC AUX ADC configuration 4                                */
15799 
15800     struct {
15801       __IOM unsigned int
15802         SDC_AUXADC_INPUT_P_SEL_CH4 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-4               */
15803       __IOM unsigned int
15804         SDC_AUXADC_INPUT_N_SEL_CH4 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-4               */
15805       __IOM unsigned int
15806         SDC_AUXADC_DIFF_MODE_CH4 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode               */
15807       __IOM unsigned int
15808         RESERVED1 : 22; /*!< [31..10] Reserved                                                         */
15809     } SDC_AUXADC_CONFIG_4_b;
15810   };
15811 
15812   union {
15813     __IOM unsigned int
15814       SDC_AUXOPAMP_CONFIG_2; /*!< (@ 0x00000034) SDC AUX OPAMP Configuration 2                              */
15815 
15816     struct {
15817       __IOM unsigned int SDC_OPAMP_EN_CH2 : 1;       /*!< [0..0] Enable signal for turning OPAMP to used for Channel-2
15818                                                      Operation                                                                 */
15819       __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH2 : 4; /*!< [4..1] Configuration register for selecting P Input of OPAMP1
15820                                                      for Channel-2                                                             */
15821       __IOM unsigned int SDC_OPAMP_EN_CH3 : 1;       /*!< [5..5] Enable signal for turning OPAMP to used for Channel-4
15822                                                      Operation                                                                 */
15823       __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH3 : 4; /*!< [9..6] Configuration register for selecting P Input of OPAMP1
15824                                                      for Channel-3                                                             */
15825       __IOM unsigned int SDC_OPAMP_EN_CH4 : 1;       /*!< [10..10] Enable signal for turning OPAMP to used for Channel-4
15826                                                      Operation                                                                 */
15827       __IOM unsigned int
15828         SDC_OPAMP_IN_P_SEL_CH4 : 1; /*!< [11..11] Configuration register for selecting P Input of OPAMP1
15829                                                      for Channel-4                                                             */
15830       unsigned int : 3;
15831       __IOM unsigned int
15832         RESERVED1 : 17; /*!< [31..15] Reserved                                                         */
15833     } SDC_AUXOPAMP_CONFIG_2_b;
15834   };
15835   __IOM SDC_SDC_DATA_REG_Type
15836     SDC_DATA_REG[16]; /*!< (@ 0x00000038) SDC Data registers (0-15)                                  */
15837 } SDC_Type;
15838 /** @} End of group RSI_DEVICE_SYSRTC */
15839 
15840 #include "si91x_mvp.h"
15841 
15842 #endif
15843 
15844 /** @} */ /* End of group Device_Peripheral_peripherals */
15845 
15846 /* ===========================================================================================================================
15847  */
15848 /* ================                          Device Specific Peripheral Address
15849  * Map                           ================ */
15850 /* ===========================================================================================================================
15851  */
15852 
15853 /** @addtogroup Device_Peripheral_peripheralAddr
15854  * @{
15855  */
15856 
15857 #define I2C0_BASE              0x44010000UL
15858 #define I2C1_BASE              0x47040000UL
15859 #define I2C2_BASE              0x24040000UL
15860 #define MCPWM_BASE             0x47070000UL
15861 #define UDMA0_BASE             0x44030000UL
15862 #define UDMA1_BASE             0x24078000UL
15863 #define GPDMA_G_BASE           0x21080000UL
15864 #define GPDMA_C_BASE           0x21081004UL
15865 #define HWRNG_BASE             0x45090000UL
15866 #define TIMERS_BASE            0x24042000UL
15867 #define QEI_BASE               0x47060000UL
15868 #define USART0_BASE            0x44000100UL
15869 #define UART0_BASE             0x44000000UL
15870 #define UART1_BASE             0x45020000UL
15871 #define ULP_UART_BASE          0x24041800UL
15872 #define GSPI0_BASE             0x45030000UL
15873 #define SSI0_BASE              0x44020000UL
15874 #define SSISlave_BASE          0x45010000UL
15875 #define SSI2_BASE              0x24040800UL
15876 #define SIO_BASE               0x47000000UL
15877 #define QSPI_BASE              0x12000000UL
15878 #define CRC_BASE               0x45080000UL
15879 #define EFUSE_BASE             0x4600C000UL
15880 #define I2S0_BASE              0x47050000UL
15881 #define I2S1_BASE              0x24040400UL
15882 #define IID_AES_BASE           0x20480500UL
15883 #define IID_QK_BASE            0x20480600UL
15884 #define IID_RPINE_BASE         0x20480400UL
15885 #define CT0_BASE               0x45060000UL
15886 #define CT1_BASE               0x45060100UL
15887 #define CT2_BASE               0x45061000UL
15888 #define CT3_BASE               0x45061100UL
15889 #define CT_MUX_REG_BASE        0x4506F000UL
15890 #define EGPIO_BASE             0x46130000UL
15891 #define EGPIO1_BASE            0x2404C000UL
15892 #define SDIO0_BASE             0x20200000UL
15893 #define SPI_SLAVE_BASE         0x20200000UL
15894 #define M4CLK_BASE             0x46000000UL
15895 #define TIME_PERIOD_BASE       0x24048200UL
15896 #define MCU_WDT_BASE           0x24048300UL
15897 #define RTC_BASE               0x2404821CUL
15898 #define BATT_FF_BASE           0x24048400UL
15899 #define MCU_FSM_BASE           0x24048100UL
15900 #define MCU_ProcessSensor_BASE 0x24048540UL
15901 #define MCU_RET_BASE           0x24048600UL
15902 #define MCU_TEMP_BASE          0x24048500UL
15903 #define MCU_AON_BASE           0x24048000UL
15904 #define ULPCLK_BASE            0x24041400UL
15905 #define SDC_BASE               0x24042400UL
15906 
15907 #if defined(SLI_SI917B0) || defined(SLI_SI915)
15908 #define SYSRTC_BASE 0x24048C00UL
15909 
15910 #define MVP_S_BASE  (0x24000000UL) /* MVP_S base address */
15911 #define MVP_NS_BASE (0x24000000UL) /* MVP_NS base address */
15912 
15913 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) \
15914      || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S == 1)))
15915 #define MVP_BASE (MVP_S_BASE) /* MVP base address */
15916 #else
15917 #define MVP_BASE (MVP_NS_BASE) /* MVP base address */
15918 #endif                         /* SL_TRUSTZONE_PERIPHERAL_MVP_S */
15919 #endif
15920 
15921 #if ((defined ENHANCED_FIM) && (defined INST_BUFF_ENABLE))
15922 /* Asign some random ULPSS memory when instruction buffer is enabled */
15923 #define FIM_BASE 0x24060100UL
15924 #else
15925 #define FIM_BASE 0x24070000UL
15926 #endif
15927 #define NWP_FSM_BASE          0x41300110UL
15928 #define OPAMP_BASE            0x24043A14UL
15929 #define AUX_ADC_DAC_COMP_BASE 0x24043800UL
15930 #define IR_BASE               0x24040C00UL
15931 #define CTS_BASE              0x24042C00UL
15932 #define MISC_CONFIG_BASE      0x46008000UL
15933 
15934 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
15935 
15936 /* ===========================================================================================================================
15937  */
15938 /* ================                                  Peripheral declaration
15939  * ================ */
15940 /* ===========================================================================================================================
15941  */
15942 
15943 /** @addtogroup Device_Peripheral_declaration
15944  * @{
15945  */
15946 
15947 #define I2C0              ((I2C0_Type *)I2C0_BASE)
15948 #define I2C1              ((I2C0_Type *)I2C1_BASE)
15949 #define I2C2              ((I2C0_Type *)I2C2_BASE)
15950 #define MCPWM             ((MCPWM_Type *)MCPWM_BASE)
15951 #define UDMA0             ((UDMA0_Type *)UDMA0_BASE)
15952 #define UDMA1             ((UDMA0_Type *)UDMA1_BASE)
15953 #define GPDMA_G           ((GPDMA_G_Type *)GPDMA_G_BASE)
15954 #define GPDMA_C           ((GPDMA_C_Type *)GPDMA_C_BASE)
15955 #define HWRNG             ((HWRNG_Type *)HWRNG_BASE)
15956 #define QEI               ((QEI_Type *)QEI_BASE)
15957 #define USART0            ((USART0_Type *)USART0_BASE)
15958 #define UART0             ((USART0_Type *)UART0_BASE)
15959 #define UART1             ((USART0_Type *)UART1_BASE)
15960 #define ULP_UART          ((USART0_Type *)ULP_UART_BASE)
15961 #define GSPI0             ((GSPI0_Type *)GSPI0_BASE)
15962 #define SSI0              ((SSI0_Type *)SSI0_BASE)
15963 #define SSISlave          ((SSI0_Type *)SSISlave_BASE)
15964 #define SSI2              ((SSI0_Type *)SSI2_BASE)
15965 #define SIO               ((SIO_Type *)SIO_BASE)
15966 #define QSPI              ((QSPI_Type *)QSPI_BASE)
15967 #define CRC               ((CRC_Type *)CRC_BASE)
15968 #define EFUSE             ((EFUSE_Type *)EFUSE_BASE)
15969 #define I2S0              ((I2S0_Type *)I2S0_BASE)
15970 #define I2S1              ((I2S0_Type *)I2S1_BASE)
15971 #define IID_AES           ((IID_AES_Type *)IID_AES_BASE)
15972 #define IID_QK            ((IID_QK_Type *)IID_QK_BASE)
15973 #define IID_RPINE         ((IID_RPINE_Type *)IID_RPINE_BASE)
15974 #define CT0               ((CT0_Type *)CT0_BASE)
15975 #define CT1               ((CT0_Type *)CT1_BASE)
15976 #define CT2               ((CT0_Type *)CT2_BASE)
15977 #define CT3               ((CT0_Type *)CT3_BASE)
15978 #define CT_MUX_REG        ((CT_MUX_REG_Type *)CT_MUX_REG_BASE)
15979 #define EGPIO             ((EGPIO_Type *)EGPIO_BASE)
15980 #define EGPIO1            ((EGPIO_Type *)EGPIO1_BASE)
15981 #define SDIO0             ((SDIO0_Type *)SDIO0_BASE)
15982 #define SPI_SLAVE         ((SPI_SLAVE_Type *)SPI_SLAVE_BASE)
15983 #define M4CLK             ((M4CLK_Type *)M4CLK_BASE)
15984 #define TIME_PERIOD       ((TIME_PERIOD_Type *)TIME_PERIOD_BASE)
15985 #define MCU_WDT           ((MCU_WDT_Type *)MCU_WDT_BASE)
15986 #define RTC               ((RTC_Type *)RTC_BASE)
15987 #define BATT_FF           ((BATT_FF_Type *)BATT_FF_BASE)
15988 #define MCU_FSM           ((MCU_FSM_Type *)MCU_FSM_BASE)
15989 #define MCU_ProcessSensor ((MCU_ProcessSensor_Type *)MCU_ProcessSensor_BASE)
15990 #define MCU_RET           ((MCU_RET_Type *)MCU_RET_BASE)
15991 #define MCU_TEMP          ((MCU_TEMP_Type *)MCU_TEMP_BASE)
15992 #define MCU_AON           ((MCU_AON_Type *)MCU_AON_BASE)
15993 #define ULPCLK            ((ULPCLK_Type *)ULPCLK_BASE)
15994 #define FIM               ((FIM_Type *)FIM_BASE)
15995 #define NWP_FSM           ((NWP_FSM_Type *)NWP_FSM_BASE)
15996 #define OPAMP             ((OPAMP_Type *)OPAMP_BASE)
15997 #define AUX_ADC_DAC_COMP  ((AUX_ADC_DAC_COMP_Type *)AUX_ADC_DAC_COMP_BASE)
15998 #define IR                ((IR_Type *)IR_BASE)
15999 #define CTS               ((CTS_Type *)CTS_BASE)
16000 #define MISC_CONFIG       ((MISC_CONFIG_Type *)MISC_CONFIG_BASE)
16001 #define SDC               ((SDC_Type *)SDC_BASE)
16002 #define ULP_I2C           I2C2 // Renaming I2C2 base address as ULP_I2C
16003 #if defined(SLI_SI917B0) || defined(SLI_SI915)
16004 #define SYSRTC0 ((SYSRTC_TypeDef *)SYSRTC_BASE)
16005 #define MVP     ((MVP_TypeDef *)MVP_BASE) /**< MVP base pointer */
16006 #endif
16007 /** @} */ /* End of group Device_Peripheral_declaration */
16008 
16009 /* =========================================  End of section using anonymous
16010  * unions  ========================================= */
16011 #if defined(__CC_ARM)
16012 #pragma pop
16013 #elif defined(__ICCARM__)
16014                                                        /* leave anonymous unions enabled */
16015 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
16016 #pragma clang diagnostic pop
16017 #elif defined(__GNUC__)
16018 /* anonymous unions are enabled by default */
16019 #elif defined(__TMS470__)
16020 /* anonymous unions are enabled by default */
16021 #elif defined(__TASKING__)
16022 #pragma warning restore
16023 #elif defined(__CSMC__)
16024 /* anonymous unions are enabled by default */
16025 #endif
16026 
16027 #ifdef __cplusplus
16028 }
16029 #endif
16030 
16031 #endif /* RS1XXXX_H */
16032 
16033 /** @} */ /* End of group RS1xxxx */
16034 
16035 /** @} */ /* End of group Silicon Lab Inc. */