1 /******************************************************************************
2 * @file sl_si91x_peripheral_gpio.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29 #ifndef SL_PERIPHERAL_GPIO_H
30 #define SL_PERIPHERAL_GPIO_H
31
32 #if !defined(GPIO_PRESENT)
33 #include "sl_si91x_gpio.h"
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /***************************************************************************/ /**
40 * @addtogroup GPIO-PERIPHERAL-DRIVER GPIO Peripheral Driver
41 * @ingroup SI91X_PERIPHERAL_APIS
42 * @{
43 *
44 ******************************************************************************/
45 /*******************************************************************************
46 ******************************* DEFINES ***********************************
47 ******************************************************************************/
48 #define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT ///< GPIO port A maximum pins
49 #define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT ///< GPIO port B maximum pins
50 #define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT ///< GPIO port C maximum pins
51 #define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT ///< GPIO port D maximum pins
52 #define _GPIO_PORT_E_PIN_COUNT 0
53 #define _GPIO_PORT_F_PIN_COUNT 0
54 #define _GPIO_PORT_G_PIN_COUNT 0
55 #define _GPIO_PORT_H_PIN_COUNT 0
56 #define _GPIO_PORT_I_PIN_COUNT 0
57 #define _GPIO_PORT_J_PIN_COUNT 0
58 #define _GPIO_PORT_K_PIN_COUNT 0
59
60 #define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) ///< GPIO port A pin mask
61 #define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) ///< GPIO port B pin mask
62 #define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) ///< GPIO port C pin mask
63 #define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) ///< GPIO port D pin mask
64 #define _GPIO_PORT_E_PIN_MASK 0x0000UL
65 #define _GPIO_PORT_F_PIN_MASK 0x0000UL
66 #define _GPIO_PORT_G_PIN_MASK 0x0000UL
67 #define _GPIO_PORT_H_PIN_MASK 0x0000UL
68 #define _GPIO_PORT_I_PIN_MASK 0x0000UL
69 #define _GPIO_PORT_J_PIN_MASK 0x0000UL
70 #define _GPIO_PORT_K_PIN_MASK 0x0000UL
71
72 ///< GPIO pins selection for selected port
73 #define _GPIO_PORT_SIZE(port) \
74 ((port) == 0 ? _GPIO_PORT_A_PIN_COUNT \
75 : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \
76 : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \
77 : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \
78 : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \
79 : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \
80 : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \
81 : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \
82 : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \
83 : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \
84 : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \
85 : 0)
86
87 ///< GPIO pins mask for selected port
88 #define _GPIO_PORT_MASK(port) \
89 (((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \
90 : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \
91 : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \
92 : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \
93 : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \
94 : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \
95 : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \
96 : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \
97 : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \
98 : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \
99 : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \
100 : 0UL)
101
102 #define SL_GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) ///< Validation of GPIO port.
103
104 #define SL_GPIO_PORT_PIN_VALID(port, pin) \
105 ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) ///< Validating GPIO port and pin
106
107 #define GPIO_PIN_MAX 15 ///< Highest GPIO pin number.
108
109 ///@brief Highest GPIO port number.
110 #if (_GPIO_PORT_K_PIN_COUNT > 0)
111 #define GPIO_PORT_MAX 10
112 #elif (_GPIO_PORT_J_PIN_COUNT > 0)
113 #define GPIO_PORT_MAX 9
114 #elif (_GPIO_PORT_I_PIN_COUNT > 0)
115 #define GPIO_PORT_MAX 8
116 #elif (_GPIO_PORT_H_PIN_COUNT > 0)
117 #define GPIO_PORT_MAX 7
118 #elif (_GPIO_PORT_G_PIN_COUNT > 0)
119 #define GPIO_PORT_MAX 6
120 #elif (_GPIO_PORT_F_PIN_COUNT > 0)
121 #define GPIO_PORT_MAX 5
122 #elif (_GPIO_PORT_E_PIN_COUNT > 0)
123 #define GPIO_PORT_MAX 4
124 #elif (_GPIO_PORT_D_PIN_COUNT > 0)
125 #define GPIO_PORT_MAX 3
126 #else
127 #error "Max GPIO port number is undefined for this part."
128 #endif
129
130 #define GPIO_EXTINTNO_MAX 15 ///< Highest EXT GPIO interrupt number.
131
132 /*******************************************************************************
133 ******************************** ENUMS ************************************
134 ******************************************************************************/
135
136 ///@brief GPIO ports IDs.
137 typedef enum {
138 #if (_GPIO_PORT_A_PIN_COUNT > 0)
139 SL_GPIO_PORT_A = 0, ///< GPIO Port A
140 #endif
141 #if (_GPIO_PORT_B_PIN_COUNT > 0)
142 SL_GPIO_PORT_B = 1, ///< GPIO Port B
143 #endif
144 #if (_GPIO_PORT_C_PIN_COUNT > 0)
145 SL_GPIO_PORT_C = 2, ///< GPIO Port C
146 #endif
147 #if (_GPIO_PORT_D_PIN_COUNT > 0)
148 SL_GPIO_PORT_D = 3, ///< GPIO Port D
149 #endif
150 #if (_GPIO_PORT_E_PIN_COUNT > 0)
151 SL_GPIO_PORT_E = 4,
152 #endif
153 #if (_GPIO_PORT_F_PIN_COUNT > 0)
154 SL_GPIO_PORT_F = 5,
155 #endif
156 #if (_GPIO_PORT_G_PIN_COUNT > 0)
157 SL_GPIO_PORT_G = 6,
158 #endif
159 #if (_GPIO_PORT_H_PIN_COUNT > 0)
160 SL_GPIO_PORT_H = 7,
161 #endif
162 #if (_GPIO_PORT_I_PIN_COUNT > 0)
163 SL_GPIO_PORT_I = 8,
164 #endif
165 #if (_GPIO_PORT_J_PIN_COUNT > 0)
166 SL_GPIO_PORT_J = 9,
167 #endif
168 #if (_GPIO_PORT_K_PIN_COUNT > 0)
169 SL_GPIO_PORT_K = 10,
170 #endif
171 } sl_gpio_port_t;
172
173 ///@brief GPIO Pin Modes.
174 typedef enum {
175 SL_GPIO_MODE_0 = _MODE0, ///< Pin MUX GPIO Mode 0.
176 SL_GPIO_MODE_1 = _MODE1, ///< Pin MUX GPIO Mode 1.
177 SL_GPIO_MODE_2 = _MODE2, ///< Pin MUX GPIO Mode 2.
178 SL_GPIO_MODE_3 = _MODE3, ///< Pin MUX GPIO Mode 3.
179 SL_GPIO_MODE_4 = _MODE4, ///< Pin MUX GPIO Mode 4.
180 SL_GPIO_MODE_5 = _MODE5, ///< Pin MUX GPIO Mode 5.
181 SL_GPIO_MODE_6 = _MODE6, ///< Pin MUX GPIO Mode 6.
182 SL_GPIO_MODE_7 = _MODE7, ///< Pin MUX GPIO Mode 7.
183 SL_GPIO_MODE_8 = _MODE8, ///< Pin MUX GPIO Mode 8.
184 SL_GPIO_MODE_9 = _MODE9, ///< Pin MUX GPIO Mode 9.
185 SL_GPIO_MODE_10 = _MODE10, ///< Pin MUX GPIO Mode 10.
186 SL_GPIO_MODE_14 = _MODE14, ///< Pin MUX GPIO Mode 14.
187 SL_GPIO_MODE_DISABLED = _GPIO_P_MODEL_MODE0_DISABLED, ///< Input disabled. Pull-up if DOUT is set.
188 SL_GPIO_MODE_INPUT = _GPIO_P_MODEL_MODE0_INPUT, ///< Input enabled. Filter if DOUT is set.
189 SL_GPIO_MODE_INPUT_PULL = _GPIO_P_MODEL_MODE0_INPUTPULL, ///< Input enabled. DOUT determines pull direction.
190 SL_GPIO_MODE_INPUT_PULL_FILTER =
191 _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, ///< Input enabled with filter. DOUT determines pull direction.
192 SL_GPIO_MODE_PUSH_PULL = _GPIO_P_MODEL_MODE0_PUSHPULL, ///< Push-pull output.
193 SL_GPIO_MODE_PUSH_PULL_ALTERNATE = _GPIO_P_MODEL_MODE0_PUSHPULLALT, ///< Push-pull using alternate control.
194 SL_GPIO_MODE_WIRED_OR = _GPIO_P_MODEL_MODE0_WIREDOR, ///< Wired-or output.
195 SL_GPIO_MODE_WIRED_OR_PULL_DOWN = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, ///< Wired-or output with pull-down.
196 SL_GPIO_MODE_WIRED_AND = _GPIO_P_MODEL_MODE0_WIREDAND, ///< Open-drain output.
197 SL_GPIO_MODE_WIRED_AND_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, ///< Open-drain output with filter.
198 SL_GPIO_MODE_WIRED_AND_PULLUP = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, ///< Open-drain output with pull-up.
199 SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER =
200 _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, ///< Open-drain output with filter and pull-up.
201 SL_GPIO_MODE_WIRED_AND_ALTERNATE = _GPIO_P_MODEL_MODE0_WIREDANDALT, ///< Open-drain output using alternate control.
202 SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER =
203 _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, ///< Open-drain output using alternate control with filter.
204 SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP =
205 _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, ///< Open-drain output using alternate control with pull-up.
206 SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER =
207 _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, ///< Open-drain output using alternate control with filter and pull-up.
208 } sl_gpio_mode_t;
209
210 ///@brief GPIO Interrupt Configurations.
211 typedef enum {
212 SL_GPIO_INTERRUPT_DISABLE = 0, ///< disable the interrupt
213 SL_GPIO_INTERRUPT_ENABLE = (1 << 0), ///< enable the interrupt
214 SL_GPIO_INTERRUPT_HIGH = (1 << 0), ///< interrupt when pin level is '1'
215 SL_GPIO_INTERRUPT_LOW = (1 << 1), ///< interrupt when pin level is '0'
216 SL_GPIO_INTERRUPT_RISING_EDGE = (1 << 2), ///< interrupt when rising edge is detected
217 SL_GPIO_INTERRUPT_FALLING_EDGE = (1 << 3), ///< interrupt when falling edge is detected
218 SL_GPIO_INTERRUPT_RISE_FALL_EDGE =
219 (SL_GPIO_INTERRUPT_FALLING_EDGE
220 | SL_GPIO_INTERRUPT_RISING_EDGE), ///< interrupt when rising and falling edge is detected
221 } sl_gpio_interrupt_flag_t;
222
223 /*******************************************************************************
224 ***************************** PROTOTYPES **********************************
225 ******************************************************************************/
226
227 /***************************************************************************/ /**
228 * @brief Configure the MCU HP instance pin interrupts with trigger type(level/edge)
229 * and register the callback function for interrupts.
230 * @pre \ref sl_si91x_gpio_enable_clock() \n
231 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
232 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
233 * @pre \ref sl_gpio_set_pin_mode() \n
234 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
235 * @param[in] port - The port to associate with the pin.
236 * HP instance - PORT 0,1,2,3
237 * ULP instance - PORT 4
238 * @param[in] pin - The pin number on the port.
239 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each.
240 * Port 3 has 9 pins.
241 * ULP instance has total 12 pins.
242 * @param[in] int_no - The interrupt number to trigger.
243 * @param[in] flags - Interrupt configuration flags
244 * @return None
245 ******************************************************************************/
246 void sl_gpio_configure_interrupt(sl_gpio_port_t port, uint8_t pin, uint32_t int_no, sl_gpio_interrupt_flag_t flags);
247
248 /***************************************************************************/ /**
249 * @brief Set the pin mode (alternate function) of a GPIO for either HP instance (or) ULP instance as per the port number.
250 * @pre \ref sl_si91x_gpio_enable_clock() \n
251 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
252 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
253 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
254 * Use corresponding pad receiver API for corresponding GPIO instance.
255 * @param[in] port - The port to associate with the pin.
256 * HP instance - PORT 0,1,2,3
257 * ULP instance - PORT 4
258 * @param[in] pin - The pin number on the port.
259 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each.
260 * Port 3 has 9 pins.
261 * ULP instance has total 12 pins.
262 * @param[in] mode - The desired pin mode.
263 * @param[in] output_value - A value to set for the pin in the GPIO register.
264 * The GPIO setting is important for some input mode configurations.
265 * @return None
266 ******************************************************************************/
267 void sl_gpio_set_pin_mode(sl_gpio_port_t port, uint8_t pin, sl_gpio_mode_t mode, uint32_t output_value);
268
269 /***************************************************************************/ /**
270 * @brief Get the pin mode (alternate function) of a GPIO for either HP instance or ULP instance as per the port number.
271 * @pre \ref sl_si91x_gpio_enable_clock() \n
272 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
273 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
274 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
275 * Use corresponding pad receiver API for corresponding GPIO instance.
276 * @pre \ref sl_gpio_set_pin_mode();
277 * @param[in] port - The port to associate with the pin.
278 * HP instance - PORT 0,1,2,3
279 * ULP instance - PORT 4
280 * @param[in] pin - The pin number on the port.
281 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each.
282 * Port 3 has 9 pins.
283 * ULP instance has total 12 pins.
284 * @return returns Pin status
285 * '0' - Output
286 * '1' - Input
287 ******************************************************************************/
288 sl_gpio_mode_t sl_gpio_get_pin_mode(sl_gpio_port_t port, uint8_t pin);
289
290 /***************************************************************************/ /**
291 * @brief Set a single GPIO pin of a GPIO port with 1.
292 * @pre \ref sl_si91x_gpio_enable_clock() \n
293 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
294 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
295 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
296 * Use corresponding pad receiver API for corresponding GPIO instance. \n
297 * @pre \ref sl_gpio_set_pin_mode(); \n
298 * @pre \ref sl_si91x_gpio_set_pin_direction(); \n
299 * @param[in] port - The port to associate with the pin.
300 * HP instance - PORT 0,1,2,3
301 * ULP instance - PORT 4
302 * @param[in] pin - The pin number on the port.
303 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each.
304 * Port 3 has 9 pins.
305 * ULP instance has total 12 pins.
306 * @return None
307 ******************************************************************************/
sl_gpio_set_pin_output(sl_gpio_port_t port,uint8_t pin)308 static __INLINE void sl_gpio_set_pin_output(sl_gpio_port_t port, uint8_t pin)
309 {
310 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
311 if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) {
312 SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin));
313 GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG = SET;
314 } else if (port == SL_GPIO_ULP_PORT) {
315 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin));
316 ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = SET;
317 } else {
318 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin));
319 // Set pin in UULP GPIO instance by controlling pin value
320 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = SET;
321 }
322 }
323
324 /***************************************************************************/ /**
325 * @brief Set the selected bits value of GPIO data out register to 1.
326 * @pre \ref sl_si91x_gpio_enable_clock() \n
327 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
328 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
329 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
330 * Use corresponding pad receiver API for corresponding GPIO instance. \n
331 * @pre \ref sl_gpio_set_pin_mode(); \n
332 * @pre \ref sl_si91x_gpio_set_pin_direction(); \n
333 * @param[in] port - The port to associate with the pin.
334 * HP instance - PORT 0,1,2,3
335 * ULP instance - PORT 4
336 * @param[in] pins - The GPIO pins in a port are set to 1's.
337 * @return None
338 ******************************************************************************/
sl_gpio_set_port_output(sl_gpio_port_t port,uint32_t pins)339 static __INLINE void sl_gpio_set_port_output(sl_gpio_port_t port, uint32_t pins)
340 {
341 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
342 if (port == SL_GPIO_ULP_PORT) {
343 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (pins);
344 } else {
345 GPIO->PORT_CONFIG[port].PORT_SET_REG = (pins);
346 }
347 }
348
349 /***************************************************************************/ /**
350 * @brief Set GPIO port value with the selected mask bits.
351 * @pre \ref sl_si91x_gpio_enable_clock() \n
352 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
353 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
354 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
355 * Use corresponding pad receiver API for corresponding GPIO instance. \n
356 * @pre \ref sl_gpio_set_pin_mode(); \n
357 * @pre \ref sl_si91x_gpio_set_pin_direction(); \n
358 * @param[in] port - The port to associate with the pin.
359 * HP instance - PORT 0,1,2,3
360 * ULP instance - PORT 4
361 * @param[in] val - Value to write to port configuration register.
362 * @param[in] mask - Mask indicating which bits to modify.
363 * @return None
364 ******************************************************************************/
sl_gpio_set_port_output_value(sl_gpio_port_t port,uint32_t val,uint32_t mask)365 static __INLINE void sl_gpio_set_port_output_value(sl_gpio_port_t port, uint32_t val, uint32_t mask)
366 {
367 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
368 if (port == SL_GPIO_ULP_PORT) {
369 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (ULP_GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask)
370 | (val & mask);
371 } else {
372 GPIO->PORT_CONFIG[port].PORT_SET_REG = (GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask) | (val & mask);
373 }
374 }
375
376 /***************************************************************************/ /**
377 * @brief Set slewrate for pins on a GPIO port.
378 * @pre \ref sl_si91x_gpio_enable_clock() \n
379 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
380 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
381 * @param[in] port - The GPIO port to configure.
382 * @param[in] slewrate - The slewrate to configure for pins on this GPIO port.
383 * @param[in] slewrate_alt - The slewrate to configure for pins using alternate modes on this GPIO port.
384 * @return None
385 ******************************************************************************/
sl_gpio_set_slew_rate(sl_gpio_port_t port,uint32_t slewrate,uint32_t slewrate_alt)386 static __INLINE void sl_gpio_set_slew_rate(sl_gpio_port_t port, uint32_t slewrate, uint32_t slewrate_alt)
387 {
388 UNUSED_VAR(slewrate_alt);
389 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
390 for (uint8_t i = (port * MAX_GPIO_PORT_PIN); i < (MAX_GPIO_PORT_PIN * (port + 1)); i++) {
391 PAD_REG(i)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_SR = (sl_si91x_gpio_slew_rate_t)slewrate;
392 }
393 }
394
395 /***************************************************************************/ /**
396 * @brief Clear a single pin in GPIO configuration register to 0.
397 * @pre \ref sl_si91x_gpio_enable_clock() \n
398 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
399 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
400 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(); for ULP instance \n
401 * Use corresponding pad receiver API for corresponding GPIO instance. \n
402 * @pre \ref sl_gpio_set_pin_mode(); \n
403 * @pre \ref sl_si91x_gpio_set_pin_direction(); \n
404 * @param[in] port - The port to associate with the pin.
405 * HP instance - PORT 0,1,2,3
406 * ULP instance - PORT 4
407 * @param[in] pin - The pin to set.
408 * @return None
409 ******************************************************************************/
sl_gpio_clear_pin_output(sl_gpio_port_t port,uint8_t pin)410 static __INLINE void sl_gpio_clear_pin_output(sl_gpio_port_t port, uint8_t pin)
411 {
412 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
413 if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) {
414 SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin));
415 GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG = CLR;
416 } else if (port == SL_GPIO_ULP_PORT) {
417 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin));
418 ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = CLR;
419 } else {
420 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin));
421 // Set pin in UULP GPIO instance by controlling pin value
422 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = CLR;
423 }
424 }
425
426 /***************************************************************************/ /**
427 * @brief Clear bits in configuration register for a port to 0.
428 * @pre \ref sl_si91x_gpio_enable_clock() \n
429 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
430 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
431 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
432 * Use corresponding pad receiver API for corresponding GPIO instance. \n
433 * @pre \ref sl_gpio_set_pin_mode() \n
434 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
435 * @param[in] port - The port to associate with the pin.
436 * HP instance - PORT 0,1,2,3
437 * ULP instance - PORT 4
438 * @param[in] pins - The GPIO pins in a port to clear.
439 * @return None
440 ******************************************************************************/
sl_gpio_clear_port_output(sl_gpio_port_t port,uint32_t pins)441 static __INLINE void sl_gpio_clear_port_output(sl_gpio_port_t port, uint32_t pins)
442 {
443 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
444 if (port == SL_GPIO_ULP_PORT) {
445 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_CLEAR_REG = (pins);
446 } else {
447 GPIO->PORT_CONFIG[port].PORT_CLEAR_REG = (pins);
448 }
449 }
450
451 /***************************************************************************/ /**
452 * @brief Read the pin value for a single pin in a GPIO port.
453 * @pre \ref sl_si91x_gpio_enable_clock() \n
454 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
455 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
456 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
457 * Use corresponding pad receiver API for corresponding GPIO instance. \n
458 * @pre \ref sl_gpio_set_pin_mode() \n
459 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
460 * @param[in] port - The port to associate with the pin.
461 * HP instance - PORT 0,1,2,3
462 * ULP instance - PORT 4
463 * @param[in] pin - The pin number on the port.
464 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each.
465 * Port 3 has 9 pins.
466 * ULP instance has total 12 pins.
467 * @return The GPIO pin value
468 * '0' - Output\n
469 * '1' - Input\n
470 ******************************************************************************/
sl_gpio_get_pin_input(sl_gpio_port_t port,uint8_t pin)471 static __INLINE uint8_t sl_gpio_get_pin_input(sl_gpio_port_t port, uint8_t pin)
472 {
473 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
474 if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) {
475 SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin));
476 return (uint8_t)GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG;
477 } else if (port == SL_GPIO_ULP_PORT) {
478 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin));
479 return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG;
480 } else {
481 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin));
482 // Read pin status in UULP GPIO instance
483 return (UULP_GPIO_STATUS >> pin) & MASK_INTR;
484 }
485 }
486
487 /***************************************************************************/ /**
488 * @brief Get the current pin value of selected pin in a GPIO port.
489 * @pre \ref sl_si91x_gpio_enable_clock() \n
490 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
491 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
492 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
493 * Use corresponding pad receiver API for corresponding GPIO instance. \n
494 * @pre \ref sl_gpio_set_pin_mode() \n
495 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
496 * @param[in] port - The port to associate with the pin.
497 * HP instance - PORT 0,1,2,3
498 * ULP instance - PORT 4
499 * @param[in] pin - The pin to get setting for.
500 * @return The GPIO pin value
501 * '0' - Output\n
502 * '1' - Input\n
503 ******************************************************************************/
sl_gpio_get_pin_output(sl_gpio_port_t port,uint8_t pin)504 static __INLINE uint8_t sl_gpio_get_pin_output(sl_gpio_port_t port, uint8_t pin)
505 {
506 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
507 if (port == SL_GPIO_ULP_PORT) {
508 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin));
509 return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG;
510 } else {
511 SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin));
512 return (uint8_t)GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG;
513 }
514 }
515
516 /***************************************************************************/ /**
517 * @brief Read the port value for GPIO port.
518 * @pre \ref sl_si91x_gpio_enable_clock() \n
519 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
520 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
521 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
522 * Use corresponding pad receiver API for corresponding GPIO instance. \n
523 * @pre \ref sl_gpio_set_pin_mode() \n
524 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
525 * @param[in] port - The port to associate with the pin.
526 * HP instance - PORT 0,1,2,3
527 * ULP instance - PORT 4
528 * @return The pin values of the GPIO port.
529 ******************************************************************************/
sl_gpio_get_port_input(sl_gpio_port_t port)530 static __INLINE uint32_t sl_gpio_get_port_input(sl_gpio_port_t port)
531 {
532 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
533 if (port == SL_GPIO_ULP_PORT) {
534 return ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK;
535 } else {
536 return GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK;
537 }
538 }
539
540 /***************************************************************************/ /**
541 * @brief Get the current pin values of a selected GPIO Port register.
542 * @pre \ref sl_si91x_gpio_enable_clock() \n
543 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
544 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
545 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
546 * Use corresponding pad receiver API for corresponding GPIO instance. \n
547 * @pre \ref sl_gpio_set_pin_mode() \n
548 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
549 * @param[in] port - The port to associate with the pin.
550 * HP instance - PORT 0,1,2,3
551 * ULP instance - PORT 4
552 * @return The port value for the requested port.
553 ******************************************************************************/
sl_gpio_get_port_output(sl_gpio_port_t port)554 static __INLINE uint32_t sl_gpio_get_port_output(sl_gpio_port_t port)
555 {
556 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
557 if (port == SL_GPIO_ULP_PORT) {
558 return (ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK);
559 } else {
560 return (GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK);
561 }
562 }
563
564 /***************************************************************************/ /**
565 * @brief Toggle a single pin in selected GPIO port register.
566 * @pre \ref sl_si91x_gpio_enable_clock() \n
567 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
568 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
569 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
570 * Use corresponding pad receiver API for corresponding GPIO instance. \n
571 * @pre \ref sl_gpio_set_pin_mode() \n
572 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
573 * @param[in] port - The port to associate with the pin.
574 * HP instance - PORT 0,1,2,3
575 * ULP instance - PORT 4
576 * @param[in] pin - The pin number on the port.
577 * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each.
578 * Port 3 has 9 pins.
579 * ULP instance has total 12 pins.
580 * @return None
581 ******************************************************************************/
sl_gpio_toggle_pin_output(sl_gpio_port_t port,uint8_t pin)582 static __INLINE void sl_gpio_toggle_pin_output(sl_gpio_port_t port, uint8_t pin)
583 {
584 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
585 if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) {
586 SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin));
587 GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG ^= SET;
588 } else if (port == SL_GPIO_ULP_PORT) {
589 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin));
590 ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG ^= SET;
591 } else {
592 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin));
593 // Set or Clear pin in UULP GPIO instance by controlling pin value
594 UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET;
595 }
596 }
597
598 /***************************************************************************/ /**
599 * @brief Toggle selected pins in GPIO port register.
600 * @pre \ref sl_si91x_gpio_enable_clock() \n
601 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
602 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
603 * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n
604 * Use corresponding pad receiver API for corresponding GPIO instance. \n
605 * @pre \ref sl_gpio_set_pin_mode() \n
606 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
607 * @param[in] port - The port to associate with the pin.
608 * HP instance - PORT 0,1,2,3
609 * ULP instance - PORT 4
610 * @param[in] pins - Port pins to toggle.
611 * @return None
612 ******************************************************************************/
sl_gpio_toggle_port_output(sl_gpio_port_t port,uint32_t pins)613 static __INLINE void sl_gpio_toggle_port_output(sl_gpio_port_t port, uint32_t pins)
614 {
615 SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port));
616 if (port == SL_GPIO_ULP_PORT) {
617 ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_TOGGLE_REG = pins;
618 } else {
619 GPIO->PORT_CONFIG[port].PORT_TOGGLE_REG = pins;
620 }
621 }
622
623 /***************************************************************************/ /**
624 * @brief Enable MCU HP instance GPIO pin interrupts.
625 * @pre \ref sl_si91x_gpio_enable_clock() \n
626 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
627 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
628 * @pre \ref sl_gpio_set_pin_mode() \n
629 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
630 * @param[in] flags - GPIO interrupt sources to enable.
631 * @return None
632 ******************************************************************************/
sl_gpio_enable_interrupts(uint32_t flags)633 static __INLINE void sl_gpio_enable_interrupts(uint32_t flags)
634 {
635 uint16_t intch, int_flag;
636 intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK);
637 int_flag = (uint16_t)(flags & INTERRUPT_MASK);
638 if ((int_flag & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) {
639 GPIO->INTR[intch].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SET;
640 }
641 if ((int_flag & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) {
642 GPIO->INTR[intch].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SET;
643 }
644 if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) {
645 GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SET;
646 }
647 if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) {
648 GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SET;
649 }
650 }
651
652 /***************************************************************************/ /**
653 * @brief Disable MCU HP Instance GPIO pin interrupts.
654 * @pre \ref sl_si91x_gpio_enable_clock() \n
655 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
656 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
657 * @pre \ref sl_gpio_set_pin_mode() \n
658 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
659 * @param[in] flags - GPIO interrupt sources to disable.
660 * @return None
661 ******************************************************************************/
sl_gpio_disable_interrupts(uint32_t flags)662 static __INLINE void sl_gpio_disable_interrupts(uint32_t flags)
663 {
664 uint16_t intch, int_flag;
665 intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK);
666 int_flag = (uint16_t)(flags & LSB_NIBBLE_MASK);
667 if ((int_flag & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) {
668 GPIO->INTR[intch].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = CLR;
669 }
670 if ((int_flag & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) {
671 GPIO->INTR[intch].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = CLR;
672 }
673 if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) {
674 GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = CLR;
675 }
676 if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) {
677 GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = CLR;
678 }
679 }
680
681 /***************************************************************************/ /**
682 * @brief Clear MCU HP Instance GPIO pin interrupts.
683 * @pre \ref sl_si91x_gpio_enable_clock() \n
684 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
685 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
686 * @pre \ref sl_gpio_set_pin_mode() \n
687 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
688 * @param[in] flags - Bitwise logic OR of GPIO interrupt sources to clear.
689 * @return None
690 ******************************************************************************/
sl_gpio_clear_interrupts(uint32_t flags)691 static __INLINE void sl_gpio_clear_interrupts(uint32_t flags)
692 {
693 uint32_t reg_data = GPIO->INTR[flags].GPIO_INTR_STATUS;
694 if (reg_data != 0)
695 GPIO->INTR[flags].GPIO_INTR_STATUS = INTR_CLR;
696 }
697
698 /**************************************************************************/ /**
699 * @brief Set MCU HP Instance GPIO pin interrupts.
700 * @pre \ref sl_si91x_gpio_enable_clock() \n
701 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
702 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
703 * @pre \ref sl_gpio_set_pin_mode() \n
704 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
705 * @param[in] flags - GPIO interrupt sources to set to pending.
706 * @return None
707 *****************************************************************************/
sl_gpio_set_interrupts(uint32_t flags)708 static __INLINE void sl_gpio_set_interrupts(uint32_t flags)
709 {
710 uint16_t intch, int_flag;
711 intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK);
712 int_flag = (uint16_t)(flags & INTERRUPT_MASK);
713 GPIO->INTR[intch].GPIO_INTR_CTRL = (GPIO->INTR[intch].GPIO_INTR_CTRL | int_flag);
714 }
715
716 /***************************************************************************/ /**
717 * @brief Get pending MCU HP Instance GPIO pin interrupts.
718 * @pre \ref sl_si91x_gpio_enable_clock() \n
719 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
720 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
721 * @pre \ref sl_gpio_set_pin_mode() \n
722 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
723 * @param[in] None
724 * @return GPIO interrupt sources pending.
725 ******************************************************************************/
sl_gpio_get_pending_interrupts(void)726 static __INLINE uint32_t sl_gpio_get_pending_interrupts(void)
727 {
728 uint32_t intflags = 0, tmp = 0;
729 for (uint8_t intch = 0; intch < MAX_GPIO_PIN_INT; intch++) {
730 tmp = (GPIO->INTR[intch].GPIO_INTR_STATUS & LSB_NIBBLE_MASK);
731 intflags |= (tmp << (NIBBLE_SHIFT * intch));
732 }
733 return intflags;
734 }
735
736 /***************************************************************************/ /**
737 * @brief Get enabled MCU HP Instance GPIO pin interrupts.
738 * @pre \ref sl_si91x_gpio_enable_clock() \n
739 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
740 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
741 * @pre \ref sl_gpio_set_pin_mode() \n
742 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
743 * @param[in] None
744 * @return Returns enabled GPIO interrupt sources.
745 ******************************************************************************/
sl_gpio_get_enabled_interrupts(void)746 static __INLINE uint32_t sl_gpio_get_enabled_interrupts(void)
747 {
748 uint32_t intflags = 0, tmp = 0;
749 for (uint8_t intch = 0; intch < MAX_GPIO_PIN_INT; intch++) {
750 tmp = (GPIO->INTR[intch].GPIO_INTR_CTRL & LSB_NIBBLE_MASK);
751 intflags |= (tmp << (NIBBLE_SHIFT * intch));
752 }
753 return intflags;
754 }
755
756 /***************************************************************************/ /**
757 * @brief Get enabled and pending GPIO pin interrupt of MCU HP Instance.
758 * Useful for handling more interrupt sources in the same interrupt handler.
759 * @pre \ref sl_si91x_gpio_enable_clock() \n
760 * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n
761 * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n
762 * @pre \ref sl_gpio_set_pin_mode() \n
763 * @pre \ref sl_si91x_gpio_set_pin_direction() \n
764 * @param[in] None
765 * @return Returns pending GPIO interrupt sources
766 ******************************************************************************/
sl_gpio_get_enabled_pending_interrupts(void)767 static __INLINE uint32_t sl_gpio_get_enabled_pending_interrupts(void)
768 {
769 uint32_t intflags = 0, tmp_ctrl = 0, tmp_sts = 0;
770 uint8_t intch = 0;
771 for (intch = 0; intch < MAX_GPIO_PIN_INT; intch++) {
772 tmp_ctrl = (GPIO->INTR[intch].GPIO_INTR_CTRL & INTERRUPT_MASK);
773 if (tmp_ctrl & MASK_CTRL) {
774 tmp_ctrl = (tmp_ctrl >> 1) | MASK_INTR;
775 }
776 tmp_sts = ((GPIO->INTR[intch].GPIO_INTR_STATUS) & (tmp_ctrl));
777 tmp_sts = (tmp_sts & LSB_NIBBLE_MASK);
778 intflags |= (tmp_sts << (NIBBLE_SHIFT * intch));
779 }
780 return intflags;
781 }
782
783 /**************************************************************************/ /**
784 * @brief This API is used set ulp soc gpio mode
785 * \n(Gpio pin mode,ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing )
786 * @param[in] ulp_gpio : ulp gpio number
787 * @param[in] mode : GPIO mode
788 * \n possible values for this parameter are the following
789 * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0
790 * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1
791 * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2
792 * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3
793 * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4
794 * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5
795 * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6
796 * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7
797 * @return None
798 ******************************************************************************/
sl_si91x_gpio_ulp_soc_mode(uint8_t ulp_gpio,uint8_t mode)799 static __INLINE void sl_si91x_gpio_ulp_soc_mode(uint8_t ulp_gpio, uint8_t mode)
800
801 {
802 ULPCLK->ULP_SOC_GPIO_MODE_REG[ulp_gpio].ULP_SOC_GPIO_MODE_REG_b.ULP_SOC_GPIO_MODE_REG = (unsigned int)(mode & 0x07);
803 }
804
805 /** @} (end addtogroup GPIO) */
806
807 #ifdef __cplusplus
808 }
809 #endif
810
811 #endif ///< GPIO_PRESENT
812 #endif ///< SL_PERIPHERAL_GPIO_H
813
