1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_USB_A_REGISTERS_H__ 27 #define __SI32_USB_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_USB_A_FADDR_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Function Address 42 volatile uint32_t FADDR_BITS: 7; 43 // Function Address Update 44 volatile uint32_t FADDRUPD: 1; 45 uint32_t reserved0: 24; 46 }; 47 volatile uint32_t U32; 48 }; 49 }; 50 51 #define SI32_USB_A_FADDR_FADDR_MASK 0x0000007F 52 #define SI32_USB_A_FADDR_FADDR_SHIFT 0 53 54 #define SI32_USB_A_FADDR_FADDRUPD_MASK 0x00000080 55 #define SI32_USB_A_FADDR_FADDRUPD_SHIFT 7 56 // The last address written to FADDR is in effect. 57 #define SI32_USB_A_FADDR_FADDRUPD_NOT_SET_VALUE 0 58 #define SI32_USB_A_FADDR_FADDRUPD_NOT_SET_U32 \ 59 (SI32_USB_A_FADDR_FADDRUPD_NOT_SET_VALUE << SI32_USB_A_FADDR_FADDRUPD_SHIFT) 60 // The last address written to FADDR is not yet in effect. 61 #define SI32_USB_A_FADDR_FADDRUPD_SET_VALUE 1 62 #define SI32_USB_A_FADDR_FADDRUPD_SET_U32 \ 63 (SI32_USB_A_FADDR_FADDRUPD_SET_VALUE << SI32_USB_A_FADDR_FADDRUPD_SHIFT) 64 65 66 67 struct SI32_USB_A_POWER_Struct 68 { 69 union 70 { 71 struct 72 { 73 // Suspend Detection Enable 74 volatile uint32_t SUSDEN: 1; 75 // Suspend Mode Flag 76 volatile uint32_t SUSMDF: 1; 77 // Force Resume 78 volatile uint32_t RESUME: 1; 79 // Reset Detect Flag 80 volatile uint32_t RSTDETF: 1; 81 // USB Inhibit 82 volatile uint32_t USBINH: 1; 83 // USB Dither Enable 84 volatile uint32_t DITHEN: 1; 85 uint32_t reserved0: 1; 86 // ISO Update Mode 87 volatile uint32_t ISOUPDMD: 1; 88 uint32_t reserved1: 24; 89 }; 90 volatile uint32_t U32; 91 }; 92 }; 93 94 #define SI32_USB_A_POWER_SUSDEN_MASK 0x00000001 95 #define SI32_USB_A_POWER_SUSDEN_SHIFT 0 96 // Disable suspend detection. The USB module will ignore suspend signaling on the 97 // bus. 98 #define SI32_USB_A_POWER_SUSDEN_DISABLED_VALUE 0 99 #define SI32_USB_A_POWER_SUSDEN_DISABLED_U32 \ 100 (SI32_USB_A_POWER_SUSDEN_DISABLED_VALUE << SI32_USB_A_POWER_SUSDEN_SHIFT) 101 // Enable suspend detection. The USB module will enter suspend mode if it detects 102 // suspend signalling on the bus. 103 #define SI32_USB_A_POWER_SUSDEN_ENABLED_VALUE 1 104 #define SI32_USB_A_POWER_SUSDEN_ENABLED_U32 \ 105 (SI32_USB_A_POWER_SUSDEN_ENABLED_VALUE << SI32_USB_A_POWER_SUSDEN_SHIFT) 106 107 #define SI32_USB_A_POWER_SUSMDF_MASK 0x00000002 108 #define SI32_USB_A_POWER_SUSMDF_SHIFT 1 109 // The USB module is not in suspend mode. 110 #define SI32_USB_A_POWER_SUSMDF_NOT_SET_VALUE 0 111 #define SI32_USB_A_POWER_SUSMDF_NOT_SET_U32 \ 112 (SI32_USB_A_POWER_SUSMDF_NOT_SET_VALUE << SI32_USB_A_POWER_SUSMDF_SHIFT) 113 // The USB module is in suspend mode. 114 #define SI32_USB_A_POWER_SUSMDF_SET_VALUE 1 115 #define SI32_USB_A_POWER_SUSMDF_SET_U32 \ 116 (SI32_USB_A_POWER_SUSMDF_SET_VALUE << SI32_USB_A_POWER_SUSMDF_SHIFT) 117 118 #define SI32_USB_A_POWER_RESUME_MASK 0x00000004 119 #define SI32_USB_A_POWER_RESUME_SHIFT 2 120 #define SI32_USB_A_POWER_RESUME_STOP_VALUE 0 121 #define SI32_USB_A_POWER_RESUME_STOP_U32 \ 122 (SI32_USB_A_POWER_RESUME_STOP_VALUE << SI32_USB_A_POWER_RESUME_SHIFT) 123 #define SI32_USB_A_POWER_RESUME_GENERATE_VALUE 1 124 #define SI32_USB_A_POWER_RESUME_GENERATE_U32 \ 125 (SI32_USB_A_POWER_RESUME_GENERATE_VALUE << SI32_USB_A_POWER_RESUME_SHIFT) 126 127 #define SI32_USB_A_POWER_RSTDETF_MASK 0x00000008 128 #define SI32_USB_A_POWER_RSTDETF_SHIFT 3 129 // Reset signaling is not present on the bus. 130 #define SI32_USB_A_POWER_RSTDETF_NOT_SET_VALUE 0 131 #define SI32_USB_A_POWER_RSTDETF_NOT_SET_U32 \ 132 (SI32_USB_A_POWER_RSTDETF_NOT_SET_VALUE << SI32_USB_A_POWER_RSTDETF_SHIFT) 133 // Reset signaling detected on the bus. 134 #define SI32_USB_A_POWER_RSTDETF_SET_VALUE 1 135 #define SI32_USB_A_POWER_RSTDETF_SET_U32 \ 136 (SI32_USB_A_POWER_RSTDETF_SET_VALUE << SI32_USB_A_POWER_RSTDETF_SHIFT) 137 138 #define SI32_USB_A_POWER_USBINH_MASK 0x00000010 139 #define SI32_USB_A_POWER_USBINH_SHIFT 4 140 // Enable the USB module. 141 #define SI32_USB_A_POWER_USBINH_INACTIVE_VALUE 0 142 #define SI32_USB_A_POWER_USBINH_INACTIVE_U32 \ 143 (SI32_USB_A_POWER_USBINH_INACTIVE_VALUE << SI32_USB_A_POWER_USBINH_SHIFT) 144 // USB module inhibited. All USB traffic is ignored. 145 #define SI32_USB_A_POWER_USBINH_ACTIVE_VALUE 1 146 #define SI32_USB_A_POWER_USBINH_ACTIVE_U32 \ 147 (SI32_USB_A_POWER_USBINH_ACTIVE_VALUE << SI32_USB_A_POWER_USBINH_SHIFT) 148 149 #define SI32_USB_A_POWER_DITHEN_MASK 0x00000020 150 #define SI32_USB_A_POWER_DITHEN_SHIFT 5 151 // Disable automatic USB dithering. 152 #define SI32_USB_A_POWER_DITHEN_DISABLED_VALUE 0 153 #define SI32_USB_A_POWER_DITHEN_DISABLED_U32 \ 154 (SI32_USB_A_POWER_DITHEN_DISABLED_VALUE << SI32_USB_A_POWER_DITHEN_SHIFT) 155 // Enable automatic USB dithering. 156 #define SI32_USB_A_POWER_DITHEN_ENABLED_VALUE 1 157 #define SI32_USB_A_POWER_DITHEN_ENABLED_U32 \ 158 (SI32_USB_A_POWER_DITHEN_ENABLED_VALUE << SI32_USB_A_POWER_DITHEN_SHIFT) 159 160 #define SI32_USB_A_POWER_ISOUPDMD_MASK 0x00000080 161 #define SI32_USB_A_POWER_ISOUPDMD_SHIFT 7 162 // When software writes IPRDYI = 1, USB will send the packet when the next IN token 163 // is received. 164 #define SI32_USB_A_POWER_ISOUPDMD_SEND_ON_IN_VALUE 0 165 #define SI32_USB_A_POWER_ISOUPDMD_SEND_ON_IN_U32 \ 166 (SI32_USB_A_POWER_ISOUPDMD_SEND_ON_IN_VALUE << SI32_USB_A_POWER_ISOUPDMD_SHIFT) 167 // When software writes IPRDYI = 1, USB will wait for a SOF token before sending 168 // the packet. If an IN token is received before a SOF token, USB will send a zero- 169 // length data packet. 170 #define SI32_USB_A_POWER_ISOUPDMD_SEND_ON_SOF_VALUE 1 171 #define SI32_USB_A_POWER_ISOUPDMD_SEND_ON_SOF_U32 \ 172 (SI32_USB_A_POWER_ISOUPDMD_SEND_ON_SOF_VALUE << SI32_USB_A_POWER_ISOUPDMD_SHIFT) 173 174 175 176 struct SI32_USB_A_IOINT_Struct 177 { 178 union 179 { 180 struct 181 { 182 // Endpoint 0 Interrupt Flag 183 volatile uint32_t EP0I: 1; 184 // IN Endpoint 1 Interrupt Flag 185 volatile uint32_t IN1I: 1; 186 // IN Endpoint 2 Interrupt Flag 187 volatile uint32_t IN2I: 1; 188 // IN Endpoint 3 Interrupt Flag 189 volatile uint32_t IN3I: 1; 190 // IN Endpoint 4 Interrupt Flag 191 volatile uint32_t IN4I: 1; 192 uint32_t reserved0: 12; 193 // OUT Endpoint 1 Interrupt Flag 194 volatile uint32_t OUT1I: 1; 195 // OUT Endpoint 2 Interrupt Flag 196 volatile uint32_t OUT2I: 1; 197 // OUT Endpoint 3 Interrupt Flag 198 volatile uint32_t OUT3I: 1; 199 // OUT Endpoint 4 Interrupt Flag 200 volatile uint32_t OUT4I: 1; 201 uint32_t reserved1: 11; 202 }; 203 volatile uint32_t U32; 204 }; 205 }; 206 207 #define SI32_USB_A_IOINT_EP0I_MASK 0x00000001 208 #define SI32_USB_A_IOINT_EP0I_SHIFT 0 209 // Read: Endpoint 0 interrupt has not occurred. Write: No effect. 210 #define SI32_USB_A_IOINT_EP0I_NOT_SET_VALUE 0 211 #define SI32_USB_A_IOINT_EP0I_NOT_SET_U32 \ 212 (SI32_USB_A_IOINT_EP0I_NOT_SET_VALUE << SI32_USB_A_IOINT_EP0I_SHIFT) 213 // Read: Endpoint 0 interrupt occurred. Write: Clear the interrupt. 214 #define SI32_USB_A_IOINT_EP0I_SET_VALUE 1 215 #define SI32_USB_A_IOINT_EP0I_SET_U32 \ 216 (SI32_USB_A_IOINT_EP0I_SET_VALUE << SI32_USB_A_IOINT_EP0I_SHIFT) 217 218 #define SI32_USB_A_IOINT_IN1I_MASK 0x00000002 219 #define SI32_USB_A_IOINT_IN1I_SHIFT 1 220 // Read: IN Endpoint 1 interrupt has not occurred. Write: No effect. 221 #define SI32_USB_A_IOINT_IN1I_NOT_SET_VALUE 0 222 #define SI32_USB_A_IOINT_IN1I_NOT_SET_U32 \ 223 (SI32_USB_A_IOINT_IN1I_NOT_SET_VALUE << SI32_USB_A_IOINT_IN1I_SHIFT) 224 // Read: IN Endpoint 1 interrupt occurred. Write: Clear the interrupt. 225 #define SI32_USB_A_IOINT_IN1I_SET_VALUE 1 226 #define SI32_USB_A_IOINT_IN1I_SET_U32 \ 227 (SI32_USB_A_IOINT_IN1I_SET_VALUE << SI32_USB_A_IOINT_IN1I_SHIFT) 228 229 #define SI32_USB_A_IOINT_IN2I_MASK 0x00000004 230 #define SI32_USB_A_IOINT_IN2I_SHIFT 2 231 // Read: IN Endpoint 2 interrupt has not occurred. Write: No effect. 232 #define SI32_USB_A_IOINT_IN2I_NOT_SET_VALUE 0 233 #define SI32_USB_A_IOINT_IN2I_NOT_SET_U32 \ 234 (SI32_USB_A_IOINT_IN2I_NOT_SET_VALUE << SI32_USB_A_IOINT_IN2I_SHIFT) 235 // Read: IN Endpoint 2 interrupt occurred. Write: Clear the interrupt. 236 #define SI32_USB_A_IOINT_IN2I_SET_VALUE 1 237 #define SI32_USB_A_IOINT_IN2I_SET_U32 \ 238 (SI32_USB_A_IOINT_IN2I_SET_VALUE << SI32_USB_A_IOINT_IN2I_SHIFT) 239 240 #define SI32_USB_A_IOINT_IN3I_MASK 0x00000008 241 #define SI32_USB_A_IOINT_IN3I_SHIFT 3 242 // Read: IN Endpoint 3 interrupt has not occurred. Write: No effect. 243 #define SI32_USB_A_IOINT_IN3I_NOT_SET_VALUE 0 244 #define SI32_USB_A_IOINT_IN3I_NOT_SET_U32 \ 245 (SI32_USB_A_IOINT_IN3I_NOT_SET_VALUE << SI32_USB_A_IOINT_IN3I_SHIFT) 246 // Read: IN Endpoint 3 interrupt occurred. Write: Clear the interrupt. 247 #define SI32_USB_A_IOINT_IN3I_SET_VALUE 1 248 #define SI32_USB_A_IOINT_IN3I_SET_U32 \ 249 (SI32_USB_A_IOINT_IN3I_SET_VALUE << SI32_USB_A_IOINT_IN3I_SHIFT) 250 251 #define SI32_USB_A_IOINT_IN4I_MASK 0x00000010 252 #define SI32_USB_A_IOINT_IN4I_SHIFT 4 253 // Read: IN Endpoint 4 interrupt has not occurred. Write: No effect. 254 #define SI32_USB_A_IOINT_IN4I_NOT_SET_VALUE 0 255 #define SI32_USB_A_IOINT_IN4I_NOT_SET_U32 \ 256 (SI32_USB_A_IOINT_IN4I_NOT_SET_VALUE << SI32_USB_A_IOINT_IN4I_SHIFT) 257 // Read: IN Endpoint 4 interrupt occurred. Write: Clear the interrupt. 258 #define SI32_USB_A_IOINT_IN4I_SET_VALUE 1 259 #define SI32_USB_A_IOINT_IN4I_SET_U32 \ 260 (SI32_USB_A_IOINT_IN4I_SET_VALUE << SI32_USB_A_IOINT_IN4I_SHIFT) 261 262 #define SI32_USB_A_IOINT_OUT1I_MASK 0x00020000 263 #define SI32_USB_A_IOINT_OUT1I_SHIFT 17 264 // Read: OUT Endpoint 1 interrupt has not occurred. Write: No effect. 265 #define SI32_USB_A_IOINT_OUT1I_NOT_SET_VALUE 0 266 #define SI32_USB_A_IOINT_OUT1I_NOT_SET_U32 \ 267 (SI32_USB_A_IOINT_OUT1I_NOT_SET_VALUE << SI32_USB_A_IOINT_OUT1I_SHIFT) 268 // Read: OUT Endpoint 1 interrupt occurred. Write: Clear the interrupt. 269 #define SI32_USB_A_IOINT_OUT1I_SET_VALUE 1 270 #define SI32_USB_A_IOINT_OUT1I_SET_U32 \ 271 (SI32_USB_A_IOINT_OUT1I_SET_VALUE << SI32_USB_A_IOINT_OUT1I_SHIFT) 272 273 #define SI32_USB_A_IOINT_OUT2I_MASK 0x00040000 274 #define SI32_USB_A_IOINT_OUT2I_SHIFT 18 275 // Read: OUT Endpoint 2 interrupt has not occurred. Write: No effect. 276 #define SI32_USB_A_IOINT_OUT2I_NOT_SET_VALUE 0 277 #define SI32_USB_A_IOINT_OUT2I_NOT_SET_U32 \ 278 (SI32_USB_A_IOINT_OUT2I_NOT_SET_VALUE << SI32_USB_A_IOINT_OUT2I_SHIFT) 279 // Read: OUT Endpoint 2 interrupt occurred. Write: Clear the interrupt. 280 #define SI32_USB_A_IOINT_OUT2I_SET_VALUE 1 281 #define SI32_USB_A_IOINT_OUT2I_SET_U32 \ 282 (SI32_USB_A_IOINT_OUT2I_SET_VALUE << SI32_USB_A_IOINT_OUT2I_SHIFT) 283 284 #define SI32_USB_A_IOINT_OUT3I_MASK 0x00080000 285 #define SI32_USB_A_IOINT_OUT3I_SHIFT 19 286 // Read: OUT Endpoint 3 interrupt has not occurred. Write: No effect. 287 #define SI32_USB_A_IOINT_OUT3I_NOT_SET_VALUE 0 288 #define SI32_USB_A_IOINT_OUT3I_NOT_SET_U32 \ 289 (SI32_USB_A_IOINT_OUT3I_NOT_SET_VALUE << SI32_USB_A_IOINT_OUT3I_SHIFT) 290 // Read: OUT Endpoint 3 interrupt occurred. Write: Clear the interrupt. 291 #define SI32_USB_A_IOINT_OUT3I_SET_VALUE 1 292 #define SI32_USB_A_IOINT_OUT3I_SET_U32 \ 293 (SI32_USB_A_IOINT_OUT3I_SET_VALUE << SI32_USB_A_IOINT_OUT3I_SHIFT) 294 295 #define SI32_USB_A_IOINT_OUT4I_MASK 0x00100000 296 #define SI32_USB_A_IOINT_OUT4I_SHIFT 20 297 // Read: OUT Endpoint 4 interrupt has not occurred. Write: No effect. 298 #define SI32_USB_A_IOINT_OUT4I_NOT_SET_VALUE 0 299 #define SI32_USB_A_IOINT_OUT4I_NOT_SET_U32 \ 300 (SI32_USB_A_IOINT_OUT4I_NOT_SET_VALUE << SI32_USB_A_IOINT_OUT4I_SHIFT) 301 // Read: OUT Endpoint 4 interrupt occurred. Write: Clear the interrupt. 302 #define SI32_USB_A_IOINT_OUT4I_SET_VALUE 1 303 #define SI32_USB_A_IOINT_OUT4I_SET_U32 \ 304 (SI32_USB_A_IOINT_OUT4I_SET_VALUE << SI32_USB_A_IOINT_OUT4I_SHIFT) 305 306 307 308 struct SI32_USB_A_CMINT_Struct 309 { 310 union 311 { 312 struct 313 { 314 // Suspend Interrupt Flag 315 volatile uint32_t SUSI: 1; 316 // Resume Interrupt Flag 317 volatile uint32_t RESI: 1; 318 // Reset Interrupt Flag 319 volatile uint32_t RSTI: 1; 320 // Start of Frame Interrupt Flag 321 volatile uint32_t SOFI: 1; 322 uint32_t reserved0: 28; 323 }; 324 volatile uint32_t U32; 325 }; 326 }; 327 328 #define SI32_USB_A_CMINT_SUSI_MASK 0x00000001 329 #define SI32_USB_A_CMINT_SUSI_SHIFT 0 330 // Read: Suspend interrupt has not occurred. Write: No effect. 331 #define SI32_USB_A_CMINT_SUSI_NOT_SET_VALUE 0 332 #define SI32_USB_A_CMINT_SUSI_NOT_SET_U32 \ 333 (SI32_USB_A_CMINT_SUSI_NOT_SET_VALUE << SI32_USB_A_CMINT_SUSI_SHIFT) 334 // Read: Suspend interrupt occurred. Write: Clear the interrupt. 335 #define SI32_USB_A_CMINT_SUSI_SET_VALUE 1 336 #define SI32_USB_A_CMINT_SUSI_SET_U32 \ 337 (SI32_USB_A_CMINT_SUSI_SET_VALUE << SI32_USB_A_CMINT_SUSI_SHIFT) 338 339 #define SI32_USB_A_CMINT_RESI_MASK 0x00000002 340 #define SI32_USB_A_CMINT_RESI_SHIFT 1 341 // Read: Resume interrupt has not occurred. Write: No effect. 342 #define SI32_USB_A_CMINT_RESI_NOT_SET_VALUE 0 343 #define SI32_USB_A_CMINT_RESI_NOT_SET_U32 \ 344 (SI32_USB_A_CMINT_RESI_NOT_SET_VALUE << SI32_USB_A_CMINT_RESI_SHIFT) 345 // Read: Resume interrupt occurred. Write: Clear the interrupt. 346 #define SI32_USB_A_CMINT_RESI_SET_VALUE 1 347 #define SI32_USB_A_CMINT_RESI_SET_U32 \ 348 (SI32_USB_A_CMINT_RESI_SET_VALUE << SI32_USB_A_CMINT_RESI_SHIFT) 349 350 #define SI32_USB_A_CMINT_RSTI_MASK 0x00000004 351 #define SI32_USB_A_CMINT_RSTI_SHIFT 2 352 // Read: Reset interrupt has not occurred. Write: No effect. 353 #define SI32_USB_A_CMINT_RSTI_NOT_SET_VALUE 0 354 #define SI32_USB_A_CMINT_RSTI_NOT_SET_U32 \ 355 (SI32_USB_A_CMINT_RSTI_NOT_SET_VALUE << SI32_USB_A_CMINT_RSTI_SHIFT) 356 // Read: Reset interrupt occurred. Write: Clear the interrupt. 357 #define SI32_USB_A_CMINT_RSTI_SET_VALUE 1 358 #define SI32_USB_A_CMINT_RSTI_SET_U32 \ 359 (SI32_USB_A_CMINT_RSTI_SET_VALUE << SI32_USB_A_CMINT_RSTI_SHIFT) 360 361 #define SI32_USB_A_CMINT_SOFI_MASK 0x00000008 362 #define SI32_USB_A_CMINT_SOFI_SHIFT 3 363 // Read: SOF interrupt has not occurred. Write: No effect. 364 #define SI32_USB_A_CMINT_SOFI_NOT_SET_VALUE 0 365 #define SI32_USB_A_CMINT_SOFI_NOT_SET_U32 \ 366 (SI32_USB_A_CMINT_SOFI_NOT_SET_VALUE << SI32_USB_A_CMINT_SOFI_SHIFT) 367 // Read: SOF interrupt occurred. Write: Clear the interrupt. 368 #define SI32_USB_A_CMINT_SOFI_SET_VALUE 1 369 #define SI32_USB_A_CMINT_SOFI_SET_U32 \ 370 (SI32_USB_A_CMINT_SOFI_SET_VALUE << SI32_USB_A_CMINT_SOFI_SHIFT) 371 372 373 374 struct SI32_USB_A_IOINTE_Struct 375 { 376 union 377 { 378 struct 379 { 380 // Endpoint 0 Interrupt Enable 381 volatile uint32_t EP0IEN: 1; 382 // IN Endpoint 1 Interrupt Enable 383 volatile uint32_t IN1IEN: 1; 384 // IN Endpoint 2 Interrupt Enable 385 volatile uint32_t IN2IEN: 1; 386 // IN Endpoint 3 Interrupt Enable 387 volatile uint32_t IN3IEN: 1; 388 // IN Endpoint 4 Interrupt Enable 389 volatile uint32_t IN4IEN: 1; 390 uint32_t reserved0: 12; 391 // OUT Endpoint 1 Interrupt Enable 392 volatile uint32_t OUT1IEN: 1; 393 // OUT Endpoint 2 Interrupt Enable 394 volatile uint32_t OUT2IEN: 1; 395 // OUT Endpoint 3 Interrupt Enable 396 volatile uint32_t OUT3IEN: 1; 397 // OUT Endpoint 4 Interrupt Enable 398 volatile uint32_t OUT4IEN: 1; 399 uint32_t reserved1: 11; 400 }; 401 volatile uint32_t U32; 402 }; 403 }; 404 405 #define SI32_USB_A_IOINTE_EP0IEN_MASK 0x00000001 406 #define SI32_USB_A_IOINTE_EP0IEN_SHIFT 0 407 // Disable the Endpoint 0 interrupt. 408 #define SI32_USB_A_IOINTE_EP0IEN_DISABLED_VALUE 0 409 #define SI32_USB_A_IOINTE_EP0IEN_DISABLED_U32 \ 410 (SI32_USB_A_IOINTE_EP0IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_EP0IEN_SHIFT) 411 // Enable the Endpoint 0 interrupt. 412 #define SI32_USB_A_IOINTE_EP0IEN_ENABLED_VALUE 1 413 #define SI32_USB_A_IOINTE_EP0IEN_ENABLED_U32 \ 414 (SI32_USB_A_IOINTE_EP0IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_EP0IEN_SHIFT) 415 416 #define SI32_USB_A_IOINTE_IN1IEN_MASK 0x00000002 417 #define SI32_USB_A_IOINTE_IN1IEN_SHIFT 1 418 // Disable the IN Endpoint 1 interrupt. 419 #define SI32_USB_A_IOINTE_IN1IEN_DISABLED_VALUE 0 420 #define SI32_USB_A_IOINTE_IN1IEN_DISABLED_U32 \ 421 (SI32_USB_A_IOINTE_IN1IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_IN1IEN_SHIFT) 422 // Enable the IN Endpoint 1 interrupt. 423 #define SI32_USB_A_IOINTE_IN1IEN_ENABLED_VALUE 1 424 #define SI32_USB_A_IOINTE_IN1IEN_ENABLED_U32 \ 425 (SI32_USB_A_IOINTE_IN1IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_IN1IEN_SHIFT) 426 427 #define SI32_USB_A_IOINTE_IN2IEN_MASK 0x00000004 428 #define SI32_USB_A_IOINTE_IN2IEN_SHIFT 2 429 // Disable the IN Endpoint 2 interrupt. 430 #define SI32_USB_A_IOINTE_IN2IEN_DISABLED_VALUE 0 431 #define SI32_USB_A_IOINTE_IN2IEN_DISABLED_U32 \ 432 (SI32_USB_A_IOINTE_IN2IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_IN2IEN_SHIFT) 433 // Enable the IN Endpoint 2 interrupt. 434 #define SI32_USB_A_IOINTE_IN2IEN_ENABLED_VALUE 1 435 #define SI32_USB_A_IOINTE_IN2IEN_ENABLED_U32 \ 436 (SI32_USB_A_IOINTE_IN2IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_IN2IEN_SHIFT) 437 438 #define SI32_USB_A_IOINTE_IN3IEN_MASK 0x00000008 439 #define SI32_USB_A_IOINTE_IN3IEN_SHIFT 3 440 // Disable the IN Endpoint 3 interrupt. 441 #define SI32_USB_A_IOINTE_IN3IEN_DISABLED_VALUE 0 442 #define SI32_USB_A_IOINTE_IN3IEN_DISABLED_U32 \ 443 (SI32_USB_A_IOINTE_IN3IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_IN3IEN_SHIFT) 444 // Enable the IN Endpoint 3 interrupt. 445 #define SI32_USB_A_IOINTE_IN3IEN_ENABLED_VALUE 1 446 #define SI32_USB_A_IOINTE_IN3IEN_ENABLED_U32 \ 447 (SI32_USB_A_IOINTE_IN3IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_IN3IEN_SHIFT) 448 449 #define SI32_USB_A_IOINTE_IN4IEN_MASK 0x00000010 450 #define SI32_USB_A_IOINTE_IN4IEN_SHIFT 4 451 // Disable the IN Endpoint 4 interrupt. 452 #define SI32_USB_A_IOINTE_IN4IEN_DISABLED_VALUE 0 453 #define SI32_USB_A_IOINTE_IN4IEN_DISABLED_U32 \ 454 (SI32_USB_A_IOINTE_IN4IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_IN4IEN_SHIFT) 455 // Enable the IN Endpoint 4 interrupt. 456 #define SI32_USB_A_IOINTE_IN4IEN_ENABLED_VALUE 1 457 #define SI32_USB_A_IOINTE_IN4IEN_ENABLED_U32 \ 458 (SI32_USB_A_IOINTE_IN4IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_IN4IEN_SHIFT) 459 460 #define SI32_USB_A_IOINTE_OUT1IEN_MASK 0x00020000 461 #define SI32_USB_A_IOINTE_OUT1IEN_SHIFT 17 462 // Disable the OUT Endpoint 1 interrupt. 463 #define SI32_USB_A_IOINTE_OUT1IEN_DISABLED_VALUE 0 464 #define SI32_USB_A_IOINTE_OUT1IEN_DISABLED_U32 \ 465 (SI32_USB_A_IOINTE_OUT1IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_OUT1IEN_SHIFT) 466 // Enable the OUT Endpoint 1 interrupt. 467 #define SI32_USB_A_IOINTE_OUT1IEN_ENABLED_VALUE 1 468 #define SI32_USB_A_IOINTE_OUT1IEN_ENABLED_U32 \ 469 (SI32_USB_A_IOINTE_OUT1IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_OUT1IEN_SHIFT) 470 471 #define SI32_USB_A_IOINTE_OUT2IEN_MASK 0x00040000 472 #define SI32_USB_A_IOINTE_OUT2IEN_SHIFT 18 473 // Disable the OUT Endpoint 2 interrupt. 474 #define SI32_USB_A_IOINTE_OUT2IEN_DISABLED_VALUE 0 475 #define SI32_USB_A_IOINTE_OUT2IEN_DISABLED_U32 \ 476 (SI32_USB_A_IOINTE_OUT2IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_OUT2IEN_SHIFT) 477 // Enable the OUT Endpoint 2 interrupt. 478 #define SI32_USB_A_IOINTE_OUT2IEN_ENABLED_VALUE 1 479 #define SI32_USB_A_IOINTE_OUT2IEN_ENABLED_U32 \ 480 (SI32_USB_A_IOINTE_OUT2IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_OUT2IEN_SHIFT) 481 482 #define SI32_USB_A_IOINTE_OUT3IEN_MASK 0x00080000 483 #define SI32_USB_A_IOINTE_OUT3IEN_SHIFT 19 484 // Disable the OUT Endpoint 3 interrupt. 485 #define SI32_USB_A_IOINTE_OUT3IEN_DISABLED_VALUE 0 486 #define SI32_USB_A_IOINTE_OUT3IEN_DISABLED_U32 \ 487 (SI32_USB_A_IOINTE_OUT3IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_OUT3IEN_SHIFT) 488 // Enable the OUT Endpoint 3 interrupt. 489 #define SI32_USB_A_IOINTE_OUT3IEN_ENABLED_VALUE 1 490 #define SI32_USB_A_IOINTE_OUT3IEN_ENABLED_U32 \ 491 (SI32_USB_A_IOINTE_OUT3IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_OUT3IEN_SHIFT) 492 493 #define SI32_USB_A_IOINTE_OUT4IEN_MASK 0x00100000 494 #define SI32_USB_A_IOINTE_OUT4IEN_SHIFT 20 495 // Disable the OUT Endpoint 4 interrupt. 496 #define SI32_USB_A_IOINTE_OUT4IEN_DISABLED_VALUE 0 497 #define SI32_USB_A_IOINTE_OUT4IEN_DISABLED_U32 \ 498 (SI32_USB_A_IOINTE_OUT4IEN_DISABLED_VALUE << SI32_USB_A_IOINTE_OUT4IEN_SHIFT) 499 // Enable the OUT Endpoint 4 interrupt. 500 #define SI32_USB_A_IOINTE_OUT4IEN_ENABLED_VALUE 1 501 #define SI32_USB_A_IOINTE_OUT4IEN_ENABLED_U32 \ 502 (SI32_USB_A_IOINTE_OUT4IEN_ENABLED_VALUE << SI32_USB_A_IOINTE_OUT4IEN_SHIFT) 503 504 505 506 struct SI32_USB_A_CMINTEPE_Struct 507 { 508 union 509 { 510 struct 511 { 512 // Suspend Interrupt Enable 513 volatile uint32_t SUSIEN: 1; 514 // Resume Interrupt Enable 515 volatile uint32_t RESIEN: 1; 516 // Reset Interrupt Enable 517 volatile uint32_t RSTIEN: 1; 518 // Start of Frame Interrupt Enable 519 volatile uint32_t SOFIEN: 1; 520 uint32_t reserved0: 12; 521 // Endpoint 0 Enable 522 volatile uint32_t EP0EN: 1; 523 // Endpoint 1 Enable 524 volatile uint32_t EP1EN: 1; 525 // Endpoint 2 Enable 526 volatile uint32_t EP2EN: 1; 527 // Endpoint 3 Enable 528 volatile uint32_t EP3EN: 1; 529 // Endpoint 4 Enable 530 volatile uint32_t EP4EN: 1; 531 uint32_t reserved1: 11; 532 }; 533 volatile uint32_t U32; 534 }; 535 }; 536 537 #define SI32_USB_A_CMINTEPE_SUSIEN_MASK 0x00000001 538 #define SI32_USB_A_CMINTEPE_SUSIEN_SHIFT 0 539 // Disable the Suspend interrupt. 540 #define SI32_USB_A_CMINTEPE_SUSIEN_DISABLED_VALUE 0 541 #define SI32_USB_A_CMINTEPE_SUSIEN_DISABLED_U32 \ 542 (SI32_USB_A_CMINTEPE_SUSIEN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_SUSIEN_SHIFT) 543 // Enable the Suspend interrupt. 544 #define SI32_USB_A_CMINTEPE_SUSIEN_ENABLED_VALUE 1 545 #define SI32_USB_A_CMINTEPE_SUSIEN_ENABLED_U32 \ 546 (SI32_USB_A_CMINTEPE_SUSIEN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_SUSIEN_SHIFT) 547 548 #define SI32_USB_A_CMINTEPE_RESIEN_MASK 0x00000002 549 #define SI32_USB_A_CMINTEPE_RESIEN_SHIFT 1 550 // Disable the Resume interrupt. 551 #define SI32_USB_A_CMINTEPE_RESIEN_DISABLED_VALUE 0 552 #define SI32_USB_A_CMINTEPE_RESIEN_DISABLED_U32 \ 553 (SI32_USB_A_CMINTEPE_RESIEN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_RESIEN_SHIFT) 554 // Enable the Resume interrupt. 555 #define SI32_USB_A_CMINTEPE_RESIEN_ENABLED_VALUE 1 556 #define SI32_USB_A_CMINTEPE_RESIEN_ENABLED_U32 \ 557 (SI32_USB_A_CMINTEPE_RESIEN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_RESIEN_SHIFT) 558 559 #define SI32_USB_A_CMINTEPE_RSTIEN_MASK 0x00000004 560 #define SI32_USB_A_CMINTEPE_RSTIEN_SHIFT 2 561 // Disable the Reset interrupt. 562 #define SI32_USB_A_CMINTEPE_RSTIEN_DISABLED_VALUE 0 563 #define SI32_USB_A_CMINTEPE_RSTIEN_DISABLED_U32 \ 564 (SI32_USB_A_CMINTEPE_RSTIEN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_RSTIEN_SHIFT) 565 // Enable the Reset interrupt. 566 #define SI32_USB_A_CMINTEPE_RSTIEN_ENABLED_VALUE 1 567 #define SI32_USB_A_CMINTEPE_RSTIEN_ENABLED_U32 \ 568 (SI32_USB_A_CMINTEPE_RSTIEN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_RSTIEN_SHIFT) 569 570 #define SI32_USB_A_CMINTEPE_SOFIEN_MASK 0x00000008 571 #define SI32_USB_A_CMINTEPE_SOFIEN_SHIFT 3 572 // Disable the SOF interrupt. 573 #define SI32_USB_A_CMINTEPE_SOFIEN_DISABLED_VALUE 0 574 #define SI32_USB_A_CMINTEPE_SOFIEN_DISABLED_U32 \ 575 (SI32_USB_A_CMINTEPE_SOFIEN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_SOFIEN_SHIFT) 576 // Enable the SOF interrupt. 577 #define SI32_USB_A_CMINTEPE_SOFIEN_ENABLED_VALUE 1 578 #define SI32_USB_A_CMINTEPE_SOFIEN_ENABLED_U32 \ 579 (SI32_USB_A_CMINTEPE_SOFIEN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_SOFIEN_SHIFT) 580 581 #define SI32_USB_A_CMINTEPE_EP0EN_MASK 0x00010000 582 #define SI32_USB_A_CMINTEPE_EP0EN_SHIFT 16 583 // Disable Endpoint 0 (no NACK, ACK, or STALL on the USB network). 584 #define SI32_USB_A_CMINTEPE_EP0EN_DISABLED_VALUE 0 585 #define SI32_USB_A_CMINTEPE_EP0EN_DISABLED_U32 \ 586 (SI32_USB_A_CMINTEPE_EP0EN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_EP0EN_SHIFT) 587 // Enable Endpoint 0 (normal). 588 #define SI32_USB_A_CMINTEPE_EP0EN_ENABLED_VALUE 1 589 #define SI32_USB_A_CMINTEPE_EP0EN_ENABLED_U32 \ 590 (SI32_USB_A_CMINTEPE_EP0EN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_EP0EN_SHIFT) 591 592 #define SI32_USB_A_CMINTEPE_EP1EN_MASK 0x00020000 593 #define SI32_USB_A_CMINTEPE_EP1EN_SHIFT 17 594 // Disable Endpoint 1 (no NACK, ACK, or STALL on the USB network). 595 #define SI32_USB_A_CMINTEPE_EP1EN_DISABLED_VALUE 0 596 #define SI32_USB_A_CMINTEPE_EP1EN_DISABLED_U32 \ 597 (SI32_USB_A_CMINTEPE_EP1EN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_EP1EN_SHIFT) 598 // Enable Endpoint 1 (normal). 599 #define SI32_USB_A_CMINTEPE_EP1EN_ENABLED_VALUE 1 600 #define SI32_USB_A_CMINTEPE_EP1EN_ENABLED_U32 \ 601 (SI32_USB_A_CMINTEPE_EP1EN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_EP1EN_SHIFT) 602 603 #define SI32_USB_A_CMINTEPE_EP2EN_MASK 0x00040000 604 #define SI32_USB_A_CMINTEPE_EP2EN_SHIFT 18 605 // Disable Endpoint 2 (no NACK, ACK, or STALL on the USB network). 606 #define SI32_USB_A_CMINTEPE_EP2EN_DISABLED_VALUE 0 607 #define SI32_USB_A_CMINTEPE_EP2EN_DISABLED_U32 \ 608 (SI32_USB_A_CMINTEPE_EP2EN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_EP2EN_SHIFT) 609 // Enable Endpoint 2 (normal). 610 #define SI32_USB_A_CMINTEPE_EP2EN_ENABLED_VALUE 1 611 #define SI32_USB_A_CMINTEPE_EP2EN_ENABLED_U32 \ 612 (SI32_USB_A_CMINTEPE_EP2EN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_EP2EN_SHIFT) 613 614 #define SI32_USB_A_CMINTEPE_EP3EN_MASK 0x00080000 615 #define SI32_USB_A_CMINTEPE_EP3EN_SHIFT 19 616 // Disable Endpoint 3 (no NACK, ACK, or STALL on the USB network). 617 #define SI32_USB_A_CMINTEPE_EP3EN_DISABLED_VALUE 0 618 #define SI32_USB_A_CMINTEPE_EP3EN_DISABLED_U32 \ 619 (SI32_USB_A_CMINTEPE_EP3EN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_EP3EN_SHIFT) 620 // Enable Endpoint 3 (normal). 621 #define SI32_USB_A_CMINTEPE_EP3EN_ENABLED_VALUE 1 622 #define SI32_USB_A_CMINTEPE_EP3EN_ENABLED_U32 \ 623 (SI32_USB_A_CMINTEPE_EP3EN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_EP3EN_SHIFT) 624 625 #define SI32_USB_A_CMINTEPE_EP4EN_MASK 0x00100000 626 #define SI32_USB_A_CMINTEPE_EP4EN_SHIFT 20 627 // Disable Endpoint 4 (no NACK, ACK, or STALL on the USB network). 628 #define SI32_USB_A_CMINTEPE_EP4EN_DISABLED_VALUE 0 629 #define SI32_USB_A_CMINTEPE_EP4EN_DISABLED_U32 \ 630 (SI32_USB_A_CMINTEPE_EP4EN_DISABLED_VALUE << SI32_USB_A_CMINTEPE_EP4EN_SHIFT) 631 // Enable Endpoint 4 (normal). 632 #define SI32_USB_A_CMINTEPE_EP4EN_ENABLED_VALUE 1 633 #define SI32_USB_A_CMINTEPE_EP4EN_ENABLED_U32 \ 634 (SI32_USB_A_CMINTEPE_EP4EN_ENABLED_VALUE << SI32_USB_A_CMINTEPE_EP4EN_SHIFT) 635 636 637 638 struct SI32_USB_A_CRCONTROL_Struct 639 { 640 union 641 { 642 struct 643 { 644 uint32_t reserved0: 4; 645 // Oscillator Open-Loop Mode Enable 646 volatile uint32_t OLEN: 1; 647 // Low Speed Clock Recovery Mode 648 volatile uint32_t LSCRMD: 1; 649 // Clock Recovery Single Step Enable 650 volatile uint32_t CRSSEN: 1; 651 // Clock Recovery Enable 652 volatile uint32_t CREN: 1; 653 uint32_t reserved1: 24; 654 }; 655 volatile uint32_t U32; 656 }; 657 }; 658 659 #define SI32_USB_A_CRCONTROL_OLEN_MASK 0x00000010 660 #define SI32_USB_A_CRCONTROL_OLEN_SHIFT 4 661 // Do not freeze the USB oscillator output frequency (closed loop mode). 662 #define SI32_USB_A_CRCONTROL_OLEN_DISABLED_VALUE 0 663 #define SI32_USB_A_CRCONTROL_OLEN_DISABLED_U32 \ 664 (SI32_USB_A_CRCONTROL_OLEN_DISABLED_VALUE << SI32_USB_A_CRCONTROL_OLEN_SHIFT) 665 // Freeze the USB oscillator output frequency (open loop mode). 666 #define SI32_USB_A_CRCONTROL_OLEN_ENABLED_VALUE 1 667 #define SI32_USB_A_CRCONTROL_OLEN_ENABLED_U32 \ 668 (SI32_USB_A_CRCONTROL_OLEN_ENABLED_VALUE << SI32_USB_A_CRCONTROL_OLEN_SHIFT) 669 670 #define SI32_USB_A_CRCONTROL_LSCRMD_MASK 0x00000020 671 #define SI32_USB_A_CRCONTROL_LSCRMD_SHIFT 5 672 // Full Speed Mode. 673 #define SI32_USB_A_CRCONTROL_LSCRMD_FULL_SPEED_VALUE 0 674 #define SI32_USB_A_CRCONTROL_LSCRMD_FULL_SPEED_U32 \ 675 (SI32_USB_A_CRCONTROL_LSCRMD_FULL_SPEED_VALUE << SI32_USB_A_CRCONTROL_LSCRMD_SHIFT) 676 // Low Speed Mode. 677 #define SI32_USB_A_CRCONTROL_LSCRMD_LOW_SPEED_VALUE 1 678 #define SI32_USB_A_CRCONTROL_LSCRMD_LOW_SPEED_U32 \ 679 (SI32_USB_A_CRCONTROL_LSCRMD_LOW_SPEED_VALUE << SI32_USB_A_CRCONTROL_LSCRMD_SHIFT) 680 681 #define SI32_USB_A_CRCONTROL_CRSSEN_MASK 0x00000040 682 #define SI32_USB_A_CRCONTROL_CRSSEN_SHIFT 6 683 // Normal calibration mode. 684 #define SI32_USB_A_CRCONTROL_CRSSEN_DISABLED_VALUE 0 685 #define SI32_USB_A_CRCONTROL_CRSSEN_DISABLED_U32 \ 686 (SI32_USB_A_CRCONTROL_CRSSEN_DISABLED_VALUE << SI32_USB_A_CRCONTROL_CRSSEN_SHIFT) 687 // Single step mode. 688 #define SI32_USB_A_CRCONTROL_CRSSEN_ENABLED_VALUE 1 689 #define SI32_USB_A_CRCONTROL_CRSSEN_ENABLED_U32 \ 690 (SI32_USB_A_CRCONTROL_CRSSEN_ENABLED_VALUE << SI32_USB_A_CRCONTROL_CRSSEN_SHIFT) 691 692 #define SI32_USB_A_CRCONTROL_CREN_MASK 0x00000080 693 #define SI32_USB_A_CRCONTROL_CREN_SHIFT 7 694 // Disable clock recovery. 695 #define SI32_USB_A_CRCONTROL_CREN_DISABLED_VALUE 0 696 #define SI32_USB_A_CRCONTROL_CREN_DISABLED_U32 \ 697 (SI32_USB_A_CRCONTROL_CREN_DISABLED_VALUE << SI32_USB_A_CRCONTROL_CREN_SHIFT) 698 // Enable clock recovery. 699 #define SI32_USB_A_CRCONTROL_CREN_ENABLED_VALUE 1 700 #define SI32_USB_A_CRCONTROL_CREN_ENABLED_U32 \ 701 (SI32_USB_A_CRCONTROL_CREN_ENABLED_VALUE << SI32_USB_A_CRCONTROL_CREN_SHIFT) 702 703 704 705 struct SI32_USB_A_FRAME_Struct 706 { 707 union 708 { 709 struct 710 { 711 // Frame Number 712 volatile uint32_t FRAMENUM: 11; 713 uint32_t reserved0: 21; 714 }; 715 volatile uint32_t U32; 716 }; 717 }; 718 719 #define SI32_USB_A_FRAME_FRAMENUM_MASK 0x000007FF 720 #define SI32_USB_A_FRAME_FRAMENUM_SHIFT 0 721 722 723 724 struct SI32_USB_A_TCONTROL_Struct 725 { 726 union 727 { 728 struct 729 { 730 // D- Signal State 731 volatile uint32_t DN: 1; 732 // D+ Signal State 733 volatile uint32_t DP: 1; 734 // Differential Receiver State 735 volatile uint32_t DFREC: 1; 736 // Physical Layer Test 737 volatile uint32_t PHYTST: 2; 738 // USB Speed Select 739 volatile uint32_t SSEL: 1; 740 // Physical Layer Enable 741 volatile uint32_t PHYEN: 1; 742 // Internal Pull-up Resistor Enable 743 volatile uint32_t PUEN: 1; 744 uint32_t reserved0: 24; 745 }; 746 volatile uint32_t U32; 747 }; 748 }; 749 750 #define SI32_USB_A_TCONTROL_DN_MASK 0x00000001 751 #define SI32_USB_A_TCONTROL_DN_SHIFT 0 752 // D- signal currently at logic 0. 753 #define SI32_USB_A_TCONTROL_DN_LOGIC_0_VALUE 0 754 #define SI32_USB_A_TCONTROL_DN_LOGIC_0_U32 \ 755 (SI32_USB_A_TCONTROL_DN_LOGIC_0_VALUE << SI32_USB_A_TCONTROL_DN_SHIFT) 756 // D- signal currently at logic 1. 757 #define SI32_USB_A_TCONTROL_DN_LOGIC_1_VALUE 1 758 #define SI32_USB_A_TCONTROL_DN_LOGIC_1_U32 \ 759 (SI32_USB_A_TCONTROL_DN_LOGIC_1_VALUE << SI32_USB_A_TCONTROL_DN_SHIFT) 760 761 #define SI32_USB_A_TCONTROL_DP_MASK 0x00000002 762 #define SI32_USB_A_TCONTROL_DP_SHIFT 1 763 // D+ signal currently at logic 0. 764 #define SI32_USB_A_TCONTROL_DP_LOGIC_0_VALUE 0 765 #define SI32_USB_A_TCONTROL_DP_LOGIC_0_U32 \ 766 (SI32_USB_A_TCONTROL_DP_LOGIC_0_VALUE << SI32_USB_A_TCONTROL_DP_SHIFT) 767 // D+ signal currently at logic 1. 768 #define SI32_USB_A_TCONTROL_DP_LOGIC_1_VALUE 1 769 #define SI32_USB_A_TCONTROL_DP_LOGIC_1_U32 \ 770 (SI32_USB_A_TCONTROL_DP_LOGIC_1_VALUE << SI32_USB_A_TCONTROL_DP_SHIFT) 771 772 #define SI32_USB_A_TCONTROL_DFREC_MASK 0x00000004 773 #define SI32_USB_A_TCONTROL_DFREC_SHIFT 2 774 // Differential 0 signalling is present on the bus. 775 #define SI32_USB_A_TCONTROL_DFREC_DIFF_0_VALUE 0 776 #define SI32_USB_A_TCONTROL_DFREC_DIFF_0_U32 \ 777 (SI32_USB_A_TCONTROL_DFREC_DIFF_0_VALUE << SI32_USB_A_TCONTROL_DFREC_SHIFT) 778 // Differential 1 signalling is present on the bus. 779 #define SI32_USB_A_TCONTROL_DFREC_DIFF_1_VALUE 1 780 #define SI32_USB_A_TCONTROL_DFREC_DIFF_1_U32 \ 781 (SI32_USB_A_TCONTROL_DFREC_DIFF_1_VALUE << SI32_USB_A_TCONTROL_DFREC_SHIFT) 782 783 #define SI32_USB_A_TCONTROL_PHYTST_MASK 0x00000018 784 #define SI32_USB_A_TCONTROL_PHYTST_SHIFT 3 785 // Mode 0: Normal (non-test mode) (D+ = X, D- = X). 786 #define SI32_USB_A_TCONTROL_PHYTST_MODE0_VALUE 0 787 #define SI32_USB_A_TCONTROL_PHYTST_MODE0_U32 \ 788 (SI32_USB_A_TCONTROL_PHYTST_MODE0_VALUE << SI32_USB_A_TCONTROL_PHYTST_SHIFT) 789 // Mode 1: Differential 1 Forced (D+ = 1, D- = 0). 790 #define SI32_USB_A_TCONTROL_PHYTST_MODE1_VALUE 1 791 #define SI32_USB_A_TCONTROL_PHYTST_MODE1_U32 \ 792 (SI32_USB_A_TCONTROL_PHYTST_MODE1_VALUE << SI32_USB_A_TCONTROL_PHYTST_SHIFT) 793 // Mode 2: Differential 0 Forced (D+ = 0, D- = 1). 794 #define SI32_USB_A_TCONTROL_PHYTST_MODE2_VALUE 2 795 #define SI32_USB_A_TCONTROL_PHYTST_MODE2_U32 \ 796 (SI32_USB_A_TCONTROL_PHYTST_MODE2_VALUE << SI32_USB_A_TCONTROL_PHYTST_SHIFT) 797 // Mode 3: Single-Ended 0 Forced (D+ = 0, D- = 0). 798 #define SI32_USB_A_TCONTROL_PHYTST_MODE3_VALUE 3 799 #define SI32_USB_A_TCONTROL_PHYTST_MODE3_U32 \ 800 (SI32_USB_A_TCONTROL_PHYTST_MODE3_VALUE << SI32_USB_A_TCONTROL_PHYTST_SHIFT) 801 802 #define SI32_USB_A_TCONTROL_SSEL_MASK 0x00000020 803 #define SI32_USB_A_TCONTROL_SSEL_SHIFT 5 804 // USB operates as a Low Speed device. If enabled, the internal pull-up resistor 805 // appears on the D- line. 806 #define SI32_USB_A_TCONTROL_SSEL_LOW_SPEED_VALUE 0 807 #define SI32_USB_A_TCONTROL_SSEL_LOW_SPEED_U32 \ 808 (SI32_USB_A_TCONTROL_SSEL_LOW_SPEED_VALUE << SI32_USB_A_TCONTROL_SSEL_SHIFT) 809 // USB operates as a Full Speed device. If enabled, the internal pull-up resistor 810 // appears on the D+ line. 811 #define SI32_USB_A_TCONTROL_SSEL_FULL_SPEED_VALUE 1 812 #define SI32_USB_A_TCONTROL_SSEL_FULL_SPEED_U32 \ 813 (SI32_USB_A_TCONTROL_SSEL_FULL_SPEED_VALUE << SI32_USB_A_TCONTROL_SSEL_SHIFT) 814 815 #define SI32_USB_A_TCONTROL_PHYEN_MASK 0x00000040 816 #define SI32_USB_A_TCONTROL_PHYEN_SHIFT 6 817 // Disable the USB physical layer Transceiver (suspend). 818 #define SI32_USB_A_TCONTROL_PHYEN_DISABLED_VALUE 0 819 #define SI32_USB_A_TCONTROL_PHYEN_DISABLED_U32 \ 820 (SI32_USB_A_TCONTROL_PHYEN_DISABLED_VALUE << SI32_USB_A_TCONTROL_PHYEN_SHIFT) 821 // Enable the USB physical layer Transceiver (normal). 822 #define SI32_USB_A_TCONTROL_PHYEN_ENABLED_VALUE 1 823 #define SI32_USB_A_TCONTROL_PHYEN_ENABLED_U32 \ 824 (SI32_USB_A_TCONTROL_PHYEN_ENABLED_VALUE << SI32_USB_A_TCONTROL_PHYEN_SHIFT) 825 826 #define SI32_USB_A_TCONTROL_PUEN_MASK 0x00000080 827 #define SI32_USB_A_TCONTROL_PUEN_SHIFT 7 828 // Disable the internal pull-up resistor (device effectively detached from the USB 829 // network). 830 #define SI32_USB_A_TCONTROL_PUEN_DISABLED_VALUE 0 831 #define SI32_USB_A_TCONTROL_PUEN_DISABLED_U32 \ 832 (SI32_USB_A_TCONTROL_PUEN_DISABLED_VALUE << SI32_USB_A_TCONTROL_PUEN_SHIFT) 833 // Enable the internal pull-up resistor when VBUS is present (device is attached to 834 // the USB network). 835 #define SI32_USB_A_TCONTROL_PUEN_ENABLED_VALUE 1 836 #define SI32_USB_A_TCONTROL_PUEN_ENABLED_U32 \ 837 (SI32_USB_A_TCONTROL_PUEN_ENABLED_VALUE << SI32_USB_A_TCONTROL_PUEN_SHIFT) 838 839 840 841 struct SI32_USB_A_CLKSEL_Struct 842 { 843 union 844 { 845 struct 846 { 847 // USB Clock Select 848 volatile uint32_t CLKSEL_BITS: 2; 849 uint32_t reserved0: 2; 850 // USB Clock Divider 851 volatile uint32_t CLKDIV: 2; 852 // USB Reset 853 volatile uint32_t RESET: 1; 854 uint32_t reserved1: 25; 855 }; 856 volatile uint32_t U32; 857 }; 858 }; 859 860 #define SI32_USB_A_CLKSEL_CLKSEL_MASK 0x00000003 861 #define SI32_USB_A_CLKSEL_CLKSEL_SHIFT 0 862 // Select the USB Oscillator as the USB clock. 863 #define SI32_USB_A_CLKSEL_CLKSEL_USBNOSC_VALUE 0 864 #define SI32_USB_A_CLKSEL_CLKSEL_USBNOSC_U32 \ 865 (SI32_USB_A_CLKSEL_CLKSEL_USBNOSC_VALUE << SI32_USB_A_CLKSEL_CLKSEL_SHIFT) 866 // Select the PLL output as the USB clock. 867 #define SI32_USB_A_CLKSEL_CLKSEL_PLLNOSC_VALUE 1 868 #define SI32_USB_A_CLKSEL_CLKSEL_PLLNOSC_U32 \ 869 (SI32_USB_A_CLKSEL_CLKSEL_PLLNOSC_VALUE << SI32_USB_A_CLKSEL_CLKSEL_SHIFT) 870 // Select the External Oscillator output (EXTOSCn) as the USB clock. 871 #define SI32_USB_A_CLKSEL_CLKSEL_EXTOSCN_VALUE 2 872 #define SI32_USB_A_CLKSEL_CLKSEL_EXTOSCN_U32 \ 873 (SI32_USB_A_CLKSEL_CLKSEL_EXTOSCN_VALUE << SI32_USB_A_CLKSEL_CLKSEL_SHIFT) 874 875 #define SI32_USB_A_CLKSEL_CLKDIV_MASK 0x00000030 876 #define SI32_USB_A_CLKSEL_CLKDIV_SHIFT 4 877 // The USB module uses the selected input clock divided by 1. 878 #define SI32_USB_A_CLKSEL_CLKDIV_DIV1_VALUE 0 879 #define SI32_USB_A_CLKSEL_CLKDIV_DIV1_U32 \ 880 (SI32_USB_A_CLKSEL_CLKDIV_DIV1_VALUE << SI32_USB_A_CLKSEL_CLKDIV_SHIFT) 881 // The USB module uses the selected input clock divided by 2. 882 #define SI32_USB_A_CLKSEL_CLKDIV_DIV2_VALUE 1 883 #define SI32_USB_A_CLKSEL_CLKDIV_DIV2_U32 \ 884 (SI32_USB_A_CLKSEL_CLKDIV_DIV2_VALUE << SI32_USB_A_CLKSEL_CLKDIV_SHIFT) 885 // The USB module uses the selected input clock divided by 4. 886 #define SI32_USB_A_CLKSEL_CLKDIV_DIV4_VALUE 2 887 #define SI32_USB_A_CLKSEL_CLKDIV_DIV4_U32 \ 888 (SI32_USB_A_CLKSEL_CLKDIV_DIV4_VALUE << SI32_USB_A_CLKSEL_CLKDIV_SHIFT) 889 // The USB module uses the selected input clock divided by 8. 890 #define SI32_USB_A_CLKSEL_CLKDIV_DIV8_VALUE 3 891 #define SI32_USB_A_CLKSEL_CLKDIV_DIV8_U32 \ 892 (SI32_USB_A_CLKSEL_CLKDIV_DIV8_VALUE << SI32_USB_A_CLKSEL_CLKDIV_SHIFT) 893 894 #define SI32_USB_A_CLKSEL_RESET_MASK 0x00000040 895 #define SI32_USB_A_CLKSEL_RESET_SHIFT 6 896 // Do not reset the USB module. 897 #define SI32_USB_A_CLKSEL_RESET_NOT_SET_VALUE 0 898 #define SI32_USB_A_CLKSEL_RESET_NOT_SET_U32 \ 899 (SI32_USB_A_CLKSEL_RESET_NOT_SET_VALUE << SI32_USB_A_CLKSEL_RESET_SHIFT) 900 // Reset the USB module. 901 #define SI32_USB_A_CLKSEL_RESET_SET_VALUE 1 902 #define SI32_USB_A_CLKSEL_RESET_SET_U32 \ 903 (SI32_USB_A_CLKSEL_RESET_SET_VALUE << SI32_USB_A_CLKSEL_RESET_SHIFT) 904 905 906 907 struct SI32_USB_A_OSCCONTROL_Struct 908 { 909 union 910 { 911 struct 912 { 913 uint32_t reserved0: 5; 914 // USB Oscillator Suspend 915 volatile uint32_t SUSPEND: 1; 916 uint32_t reserved1: 1; 917 // USB Oscillator Enable 918 volatile uint32_t OSCEN: 1; 919 uint32_t reserved2: 24; 920 }; 921 volatile uint32_t U32; 922 }; 923 }; 924 925 #define SI32_USB_A_OSCCONTROL_SUSPEND_MASK 0x00000020 926 #define SI32_USB_A_OSCCONTROL_SUSPEND_SHIFT 5 927 // The USB oscillator is not suspended. 928 #define SI32_USB_A_OSCCONTROL_SUSPEND_DISABLED_VALUE 0 929 #define SI32_USB_A_OSCCONTROL_SUSPEND_DISABLED_U32 \ 930 (SI32_USB_A_OSCCONTROL_SUSPEND_DISABLED_VALUE << SI32_USB_A_OSCCONTROL_SUSPEND_SHIFT) 931 // Suspend the USB oscillator. 932 #define SI32_USB_A_OSCCONTROL_SUSPEND_ENABLED_VALUE 1 933 #define SI32_USB_A_OSCCONTROL_SUSPEND_ENABLED_U32 \ 934 (SI32_USB_A_OSCCONTROL_SUSPEND_ENABLED_VALUE << SI32_USB_A_OSCCONTROL_SUSPEND_SHIFT) 935 936 #define SI32_USB_A_OSCCONTROL_OSCEN_MASK 0x00000080 937 #define SI32_USB_A_OSCCONTROL_OSCEN_SHIFT 7 938 // Disable the USB oscillator. 939 #define SI32_USB_A_OSCCONTROL_OSCEN_DISABLED_VALUE 0 940 #define SI32_USB_A_OSCCONTROL_OSCEN_DISABLED_U32 \ 941 (SI32_USB_A_OSCCONTROL_OSCEN_DISABLED_VALUE << SI32_USB_A_OSCCONTROL_OSCEN_SHIFT) 942 // Enable the USB oscillator. 943 #define SI32_USB_A_OSCCONTROL_OSCEN_ENABLED_VALUE 1 944 #define SI32_USB_A_OSCCONTROL_OSCEN_ENABLED_U32 \ 945 (SI32_USB_A_OSCCONTROL_OSCEN_ENABLED_VALUE << SI32_USB_A_OSCCONTROL_OSCEN_SHIFT) 946 947 948 949 struct SI32_USB_A_AFADJUST_Struct 950 { 951 union 952 { 953 struct 954 { 955 // USB Oscillator Fine Output Frequency Adjust 956 volatile uint32_t FINEFADJ: 6; 957 // USB Oscillator Dithering Enable 958 volatile uint32_t DITHEN: 1; 959 uint32_t reserved0: 25; 960 }; 961 volatile uint32_t U32; 962 }; 963 }; 964 965 #define SI32_USB_A_AFADJUST_FINEFADJ_MASK 0x0000003F 966 #define SI32_USB_A_AFADJUST_FINEFADJ_SHIFT 0 967 968 #define SI32_USB_A_AFADJUST_DITHEN_MASK 0x00000040 969 #define SI32_USB_A_AFADJUST_DITHEN_SHIFT 6 970 // Disable USB oscillator dithering. 971 #define SI32_USB_A_AFADJUST_DITHEN_DISABLED_VALUE 0 972 #define SI32_USB_A_AFADJUST_DITHEN_DISABLED_U32 \ 973 (SI32_USB_A_AFADJUST_DITHEN_DISABLED_VALUE << SI32_USB_A_AFADJUST_DITHEN_SHIFT) 974 // Enable USB oscillator dithering. 975 #define SI32_USB_A_AFADJUST_DITHEN_ENABLED_VALUE 1 976 #define SI32_USB_A_AFADJUST_DITHEN_ENABLED_U32 \ 977 (SI32_USB_A_AFADJUST_DITHEN_ENABLED_VALUE << SI32_USB_A_AFADJUST_DITHEN_SHIFT) 978 979 980 981 struct SI32_USB_A_FADJUST_Struct 982 { 983 union 984 { 985 struct 986 { 987 // Oscillator Output Frequency Adjust 988 volatile uint32_t FADJ: 7; 989 uint32_t reserved0: 25; 990 }; 991 volatile uint32_t U32; 992 }; 993 }; 994 995 #define SI32_USB_A_FADJUST_FADJ_MASK 0x0000007F 996 #define SI32_USB_A_FADJUST_FADJ_SHIFT 0 997 998 999 1000 struct SI32_USB_A_DMAFIFO_Struct 1001 { 1002 union 1003 { 1004 // This is a FIFO register 1005 volatile uint8_t U8; 1006 volatile uint16_t U16; 1007 volatile uint32_t U32; 1008 }; 1009 }; 1010 1011 #define SI32_USB_A_DMAFIFO_DMAFIFO_MASK 0xFFFFFFFF 1012 #define SI32_USB_A_DMAFIFO_DMAFIFO_SHIFT 0 1013 1014 1015 1016 struct SI32_USB_A_DMACONTROL_Struct 1017 { 1018 union 1019 { 1020 struct 1021 { 1022 uint32_t reserved0: 4; 1023 // USB DMA Debug Mode 1024 volatile uint32_t DBGMD: 1; 1025 // Timeout Error Flag 1026 volatile uint32_t TERRF: 1; 1027 // USB DMA Busy Flag 1028 volatile uint32_t DBUSYF: 1; 1029 // USB DMA Buffer Flush Control 1030 volatile uint32_t DFIFOFL: 1; 1031 uint32_t reserved1: 24; 1032 }; 1033 volatile uint32_t U32; 1034 }; 1035 }; 1036 1037 #define SI32_USB_A_DMACONTROL_DBGMD_MASK 0x00000010 1038 #define SI32_USB_A_DMACONTROL_DBGMD_SHIFT 4 1039 // The USB module will continue to operate while the core is halted in debug mode. 1040 #define SI32_USB_A_DMACONTROL_DBGMD_RUN_VALUE 0 1041 #define SI32_USB_A_DMACONTROL_DBGMD_RUN_U32 \ 1042 (SI32_USB_A_DMACONTROL_DBGMD_RUN_VALUE << SI32_USB_A_DMACONTROL_DBGMD_SHIFT) 1043 // A debug breakpoint will prevent the USB DMA buffer from transferring data to and 1044 // from the USB FIFOs when the core is halted. 1045 #define SI32_USB_A_DMACONTROL_DBGMD_HALT_VALUE 1 1046 #define SI32_USB_A_DMACONTROL_DBGMD_HALT_U32 \ 1047 (SI32_USB_A_DMACONTROL_DBGMD_HALT_VALUE << SI32_USB_A_DMACONTROL_DBGMD_SHIFT) 1048 1049 #define SI32_USB_A_DMACONTROL_TERRF_MASK 0x00000020 1050 #define SI32_USB_A_DMACONTROL_TERRF_SHIFT 5 1051 // A timeout error has not occurred. 1052 #define SI32_USB_A_DMACONTROL_TERRF_NOT_SET_VALUE 0 1053 #define SI32_USB_A_DMACONTROL_TERRF_NOT_SET_U32 \ 1054 (SI32_USB_A_DMACONTROL_TERRF_NOT_SET_VALUE << SI32_USB_A_DMACONTROL_TERRF_SHIFT) 1055 // A timeout error occurred. 1056 #define SI32_USB_A_DMACONTROL_TERRF_SET_VALUE 1 1057 #define SI32_USB_A_DMACONTROL_TERRF_SET_U32 \ 1058 (SI32_USB_A_DMACONTROL_TERRF_SET_VALUE << SI32_USB_A_DMACONTROL_TERRF_SHIFT) 1059 1060 #define SI32_USB_A_DMACONTROL_DBUSYF_MASK 0x00000040 1061 #define SI32_USB_A_DMACONTROL_DBUSYF_SHIFT 6 1062 // The DMA buffer is not busy. 1063 #define SI32_USB_A_DMACONTROL_DBUSYF_NOT_SET_VALUE 0 1064 #define SI32_USB_A_DMACONTROL_DBUSYF_NOT_SET_U32 \ 1065 (SI32_USB_A_DMACONTROL_DBUSYF_NOT_SET_VALUE << SI32_USB_A_DMACONTROL_DBUSYF_SHIFT) 1066 // The DMA buffer is busy reading or writing an 8-word packet. 1067 #define SI32_USB_A_DMACONTROL_DBUSYF_SET_VALUE 1 1068 #define SI32_USB_A_DMACONTROL_DBUSYF_SET_U32 \ 1069 (SI32_USB_A_DMACONTROL_DBUSYF_SET_VALUE << SI32_USB_A_DMACONTROL_DBUSYF_SHIFT) 1070 1071 #define SI32_USB_A_DMACONTROL_DFIFOFL_MASK 0x00000080 1072 #define SI32_USB_A_DMACONTROL_DFIFOFL_SHIFT 7 1073 // Flush the USB DMA buffer. 1074 #define SI32_USB_A_DMACONTROL_DFIFOFL_SET_VALUE 1 1075 #define SI32_USB_A_DMACONTROL_DFIFOFL_SET_U32 \ 1076 (SI32_USB_A_DMACONTROL_DFIFOFL_SET_VALUE << SI32_USB_A_DMACONTROL_DFIFOFL_SHIFT) 1077 1078 1079 1080 struct SI32_USB_A_EP0CONTROL_Struct 1081 { 1082 union 1083 { 1084 struct 1085 { 1086 // OUT Packet Ready Interrupt Flag 1087 volatile uint32_t OPRDYI: 1; 1088 // IN Packet Ready Indicator 1089 volatile uint32_t IPRDYI: 1; 1090 // Sent Stall Interrupt Flag 1091 volatile uint32_t STSTLI: 1; 1092 // Data End 1093 volatile uint32_t DEND: 1; 1094 // Setup End Interrupt Flag 1095 volatile uint32_t SUENDI: 1; 1096 // Send Stall 1097 volatile uint32_t SDSTL: 1; 1098 // Serviced Out Packet Ready Interrupt Flag 1099 volatile uint32_t OPRDYIS: 1; 1100 // Serviced Setup End Interrupt Flag 1101 volatile uint32_t SUENDIS: 1; 1102 uint32_t reserved0: 24; 1103 }; 1104 volatile uint32_t U32; 1105 }; 1106 }; 1107 1108 #define SI32_USB_A_EP0CONTROL_OPRDYI_MASK 0x00000001 1109 #define SI32_USB_A_EP0CONTROL_OPRDYI_SHIFT 0 1110 // A packet is not available. 1111 #define SI32_USB_A_EP0CONTROL_OPRDYI_NOT_SET_VALUE 0 1112 #define SI32_USB_A_EP0CONTROL_OPRDYI_NOT_SET_U32 \ 1113 (SI32_USB_A_EP0CONTROL_OPRDYI_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_OPRDYI_SHIFT) 1114 // A packet is available. 1115 #define SI32_USB_A_EP0CONTROL_OPRDYI_SET_VALUE 1 1116 #define SI32_USB_A_EP0CONTROL_OPRDYI_SET_U32 \ 1117 (SI32_USB_A_EP0CONTROL_OPRDYI_SET_VALUE << SI32_USB_A_EP0CONTROL_OPRDYI_SHIFT) 1118 1119 #define SI32_USB_A_EP0CONTROL_IPRDYI_MASK 0x00000002 1120 #define SI32_USB_A_EP0CONTROL_IPRDYI_SHIFT 1 1121 // A packet is not ready for transmission to host. 1122 #define SI32_USB_A_EP0CONTROL_IPRDYI_NOT_SET_VALUE 0 1123 #define SI32_USB_A_EP0CONTROL_IPRDYI_NOT_SET_U32 \ 1124 (SI32_USB_A_EP0CONTROL_IPRDYI_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_IPRDYI_SHIFT) 1125 // A packet is ready for transmission to host. 1126 #define SI32_USB_A_EP0CONTROL_IPRDYI_SET_VALUE 1 1127 #define SI32_USB_A_EP0CONTROL_IPRDYI_SET_U32 \ 1128 (SI32_USB_A_EP0CONTROL_IPRDYI_SET_VALUE << SI32_USB_A_EP0CONTROL_IPRDYI_SHIFT) 1129 1130 #define SI32_USB_A_EP0CONTROL_STSTLI_MASK 0x00000004 1131 #define SI32_USB_A_EP0CONTROL_STSTLI_SHIFT 2 1132 // Read: A STALL handshake has not been sent or is cleared. Write: Clear the 1133 // interrupt. 1134 #define SI32_USB_A_EP0CONTROL_STSTLI_NOT_SET_VALUE 0 1135 #define SI32_USB_A_EP0CONTROL_STSTLI_NOT_SET_U32 \ 1136 (SI32_USB_A_EP0CONTROL_STSTLI_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_STSTLI_SHIFT) 1137 // Read: STALL handshake sent. Write: No effect. 1138 #define SI32_USB_A_EP0CONTROL_STSTLI_SET_VALUE 1 1139 #define SI32_USB_A_EP0CONTROL_STSTLI_SET_U32 \ 1140 (SI32_USB_A_EP0CONTROL_STSTLI_SET_VALUE << SI32_USB_A_EP0CONTROL_STSTLI_SHIFT) 1141 1142 #define SI32_USB_A_EP0CONTROL_DEND_MASK 0x00000008 1143 #define SI32_USB_A_EP0CONTROL_DEND_SHIFT 3 1144 // The current packet is not the last packet of the transfer. 1145 #define SI32_USB_A_EP0CONTROL_DEND_NOT_SET_VALUE 0 1146 #define SI32_USB_A_EP0CONTROL_DEND_NOT_SET_U32 \ 1147 (SI32_USB_A_EP0CONTROL_DEND_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_DEND_SHIFT) 1148 // The current packet is the last packet of the transfer. 1149 #define SI32_USB_A_EP0CONTROL_DEND_SET_VALUE 1 1150 #define SI32_USB_A_EP0CONTROL_DEND_SET_U32 \ 1151 (SI32_USB_A_EP0CONTROL_DEND_SET_VALUE << SI32_USB_A_EP0CONTROL_DEND_SHIFT) 1152 1153 #define SI32_USB_A_EP0CONTROL_SUENDI_MASK 0x00000010 1154 #define SI32_USB_A_EP0CONTROL_SUENDI_SHIFT 4 1155 // The current packet is not the last packet of setup. 1156 #define SI32_USB_A_EP0CONTROL_SUENDI_NOT_SET_VALUE 0 1157 #define SI32_USB_A_EP0CONTROL_SUENDI_NOT_SET_U32 \ 1158 (SI32_USB_A_EP0CONTROL_SUENDI_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_SUENDI_SHIFT) 1159 // The current packet is the last packet of setup. 1160 #define SI32_USB_A_EP0CONTROL_SUENDI_SET_VALUE 1 1161 #define SI32_USB_A_EP0CONTROL_SUENDI_SET_U32 \ 1162 (SI32_USB_A_EP0CONTROL_SUENDI_SET_VALUE << SI32_USB_A_EP0CONTROL_SUENDI_SHIFT) 1163 1164 #define SI32_USB_A_EP0CONTROL_SDSTL_MASK 0x00000020 1165 #define SI32_USB_A_EP0CONTROL_SDSTL_SHIFT 5 1166 // The STALL handshake has been transmitted or not triggered. 1167 #define SI32_USB_A_EP0CONTROL_SDSTL_NOT_SET_VALUE 0 1168 #define SI32_USB_A_EP0CONTROL_SDSTL_NOT_SET_U32 \ 1169 (SI32_USB_A_EP0CONTROL_SDSTL_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_SDSTL_SHIFT) 1170 // Initiate a STALL condition. 1171 #define SI32_USB_A_EP0CONTROL_SDSTL_SET_VALUE 1 1172 #define SI32_USB_A_EP0CONTROL_SDSTL_SET_U32 \ 1173 (SI32_USB_A_EP0CONTROL_SDSTL_SET_VALUE << SI32_USB_A_EP0CONTROL_SDSTL_SHIFT) 1174 1175 #define SI32_USB_A_EP0CONTROL_OPRDYIS_MASK 0x00000040 1176 #define SI32_USB_A_EP0CONTROL_OPRDYIS_SHIFT 6 1177 // The out packet has not been processed. 1178 #define SI32_USB_A_EP0CONTROL_OPRDYIS_NOT_SET_VALUE 0 1179 #define SI32_USB_A_EP0CONTROL_OPRDYIS_NOT_SET_U32 \ 1180 (SI32_USB_A_EP0CONTROL_OPRDYIS_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_OPRDYIS_SHIFT) 1181 // The out packet has been received and accepted. 1182 #define SI32_USB_A_EP0CONTROL_OPRDYIS_SET_VALUE 1 1183 #define SI32_USB_A_EP0CONTROL_OPRDYIS_SET_U32 \ 1184 (SI32_USB_A_EP0CONTROL_OPRDYIS_SET_VALUE << SI32_USB_A_EP0CONTROL_OPRDYIS_SHIFT) 1185 1186 #define SI32_USB_A_EP0CONTROL_SUENDIS_MASK 0x00000080 1187 #define SI32_USB_A_EP0CONTROL_SUENDIS_SHIFT 7 1188 // Setup end has not been serviced. 1189 #define SI32_USB_A_EP0CONTROL_SUENDIS_NOT_SET_VALUE 0 1190 #define SI32_USB_A_EP0CONTROL_SUENDIS_NOT_SET_U32 \ 1191 (SI32_USB_A_EP0CONTROL_SUENDIS_NOT_SET_VALUE << SI32_USB_A_EP0CONTROL_SUENDIS_SHIFT) 1192 // Setup end has been serviced. 1193 #define SI32_USB_A_EP0CONTROL_SUENDIS_SET_VALUE 1 1194 #define SI32_USB_A_EP0CONTROL_SUENDIS_SET_U32 \ 1195 (SI32_USB_A_EP0CONTROL_SUENDIS_SET_VALUE << SI32_USB_A_EP0CONTROL_SUENDIS_SHIFT) 1196 1197 1198 1199 struct SI32_USB_A_EP0COUNT_Struct 1200 { 1201 union 1202 { 1203 struct 1204 { 1205 // Endpoint 0 OUT Data Count 1206 volatile uint32_t COUNT: 7; 1207 uint32_t reserved0: 25; 1208 }; 1209 volatile uint32_t U32; 1210 }; 1211 }; 1212 1213 #define SI32_USB_A_EP0COUNT_COUNT_MASK 0x0000007F 1214 #define SI32_USB_A_EP0COUNT_COUNT_SHIFT 0 1215 1216 1217 1218 struct SI32_USB_A_EP0FIFO_Struct 1219 { 1220 union 1221 { 1222 // This is a FIFO register 1223 volatile uint8_t U8; 1224 volatile uint16_t U16; 1225 volatile uint32_t U32; 1226 }; 1227 }; 1228 1229 #define SI32_USB_A_EP0FIFO_FIFO_MASK 0xFFFFFFFF 1230 #define SI32_USB_A_EP0FIFO_FIFO_SHIFT 0 1231 1232 1233 1234 typedef struct SI32_USB_A_Struct 1235 { 1236 struct SI32_USB_A_FADDR_Struct FADDR ; // Base Address + 0x0 1237 uint32_t reserved0; 1238 uint32_t reserved1; 1239 uint32_t reserved2; 1240 struct SI32_USB_A_POWER_Struct POWER ; // Base Address + 0x10 1241 uint32_t reserved3; 1242 uint32_t reserved4; 1243 uint32_t reserved5; 1244 struct SI32_USB_A_IOINT_Struct IOINT ; // Base Address + 0x20 1245 uint32_t reserved6; 1246 volatile uint32_t IOINT_CLR; 1247 uint32_t reserved7; 1248 struct SI32_USB_A_CMINT_Struct CMINT ; // Base Address + 0x30 1249 uint32_t reserved8; 1250 volatile uint32_t CMINT_CLR; 1251 uint32_t reserved9; 1252 struct SI32_USB_A_IOINTE_Struct IOINTE ; // Base Address + 0x40 1253 uint32_t reserved10; 1254 uint32_t reserved11; 1255 uint32_t reserved12; 1256 struct SI32_USB_A_CMINTEPE_Struct CMINTEPE ; // Base Address + 0x50 1257 uint32_t reserved13; 1258 uint32_t reserved14; 1259 uint32_t reserved15; 1260 struct SI32_USB_A_CRCONTROL_Struct CRCONTROL ; // Base Address + 0x60 1261 uint32_t reserved16; 1262 uint32_t reserved17; 1263 uint32_t reserved18; 1264 struct SI32_USB_A_FRAME_Struct FRAME ; // Base Address + 0x70 1265 uint32_t reserved19; 1266 uint32_t reserved20; 1267 uint32_t reserved21; 1268 uint32_t reserved22[96]; 1269 struct SI32_USB_A_TCONTROL_Struct TCONTROL ; // Base Address + 0x200 1270 uint32_t reserved23; 1271 uint32_t reserved24; 1272 uint32_t reserved25; 1273 uint32_t reserved26[60]; 1274 struct SI32_USB_A_CLKSEL_Struct CLKSEL ; // Base Address + 0x300 1275 uint32_t reserved27; 1276 uint32_t reserved28; 1277 uint32_t reserved29; 1278 struct SI32_USB_A_OSCCONTROL_Struct OSCCONTROL ; // Base Address + 0x310 1279 volatile uint32_t OSCCONTROL_SET; 1280 volatile uint32_t OSCCONTROL_CLR; 1281 uint32_t reserved30; 1282 struct SI32_USB_A_AFADJUST_Struct AFADJUST ; // Base Address + 0x320 1283 volatile uint32_t AFADJUST_SET; 1284 volatile uint32_t AFADJUST_CLR; 1285 uint32_t reserved31; 1286 struct SI32_USB_A_FADJUST_Struct FADJUST ; // Base Address + 0x330 1287 uint32_t reserved32; 1288 uint32_t reserved33; 1289 uint32_t reserved34; 1290 uint32_t reserved35[4]; 1291 uint32_t reserved36[4]; 1292 uint32_t reserved37[40]; 1293 struct SI32_USB_A_DMAFIFO_Struct DMAFIFO ; // Base Address + 0x400 1294 uint32_t reserved38; 1295 uint32_t reserved39; 1296 uint32_t reserved40; 1297 struct SI32_USB_A_DMACONTROL_Struct DMACONTROL ; // Base Address + 0x410 1298 uint32_t reserved41; 1299 uint32_t reserved42; 1300 uint32_t reserved43; 1301 uint32_t reserved44[252]; 1302 struct SI32_USB_A_EP0CONTROL_Struct EP0CONTROL ; // Base Address + 0x810 1303 uint32_t reserved45; 1304 uint32_t reserved46; 1305 uint32_t reserved47; 1306 struct SI32_USB_A_EP0COUNT_Struct EP0COUNT ; // Base Address + 0x820 1307 uint32_t reserved48; 1308 uint32_t reserved49; 1309 uint32_t reserved50; 1310 struct SI32_USB_A_EP0FIFO_Struct EP0FIFO ; // Base Address + 0x830 1311 uint32_t reserved51; 1312 uint32_t reserved52; 1313 uint32_t reserved53; 1314 } SI32_USB_A_Type; 1315 1316 #ifdef __cplusplus 1317 } 1318 #endif 1319 1320 #endif // __SI32_USB_A_REGISTERS_H__ 1321 1322 //-eof-------------------------------------------------------------------------- 1323 1324
