1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_UART_B_REGISTERS_H__ 27 #define __SI32_UART_B_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_UART_B_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Receiver Start Enable 42 volatile uint32_t RSTRTEN: 1; 43 // Receiver Parity Enable 44 volatile uint32_t RPAREN: 1; 45 // Receiver Stop Enable 46 volatile uint32_t RSTPEN: 1; 47 // Receiver Stop Mode 48 volatile uint32_t RSTPMD: 2; 49 // Receiver Parity Mode 50 volatile uint32_t RPARMD: 2; 51 uint32_t reserved0: 1; 52 // Receiver Data Length 53 volatile uint32_t RDATLN: 3; 54 uint32_t reserved1: 2; 55 // Receiver IrDA Enable 56 volatile uint32_t RIRDAEN: 1; 57 // Receiver Invert Enable 58 volatile uint32_t RINVEN: 1; 59 uint32_t reserved2: 1; 60 // Transmitter Start Enable 61 volatile uint32_t TSTRTEN: 1; 62 // Transmitter Parity Enable 63 volatile uint32_t TPAREN: 1; 64 // Transmitter Stop Enable 65 volatile uint32_t TSTPEN: 1; 66 // Transmitter Stop Mode 67 volatile uint32_t TSTPMD: 2; 68 // Transmitter Parity Mode 69 volatile uint32_t TPARMD: 2; 70 uint32_t reserved3: 1; 71 // Transmitter Data Length 72 volatile uint32_t TDATLN: 3; 73 uint32_t reserved4: 2; 74 // Transmitter IrDA Enable 75 volatile uint32_t TIRDAEN: 1; 76 // Transmitter Invert Enable 77 volatile uint32_t TINVEN: 1; 78 uint32_t reserved5: 1; 79 }; 80 volatile uint32_t U32; 81 }; 82 }; 83 84 #define SI32_UART_B_CONFIG_RSTRTEN_MASK 0x00000001 85 #define SI32_UART_B_CONFIG_RSTRTEN_SHIFT 0 86 // Do not expect a start bit during receptions. 87 #define SI32_UART_B_CONFIG_RSTRTEN_DISABLED_VALUE 0 88 #define SI32_UART_B_CONFIG_RSTRTEN_DISABLED_U32 \ 89 (SI32_UART_B_CONFIG_RSTRTEN_DISABLED_VALUE << SI32_UART_B_CONFIG_RSTRTEN_SHIFT) 90 // Expect a start bit during receptions. 91 #define SI32_UART_B_CONFIG_RSTRTEN_ENABLED_VALUE 1 92 #define SI32_UART_B_CONFIG_RSTRTEN_ENABLED_U32 \ 93 (SI32_UART_B_CONFIG_RSTRTEN_ENABLED_VALUE << SI32_UART_B_CONFIG_RSTRTEN_SHIFT) 94 95 #define SI32_UART_B_CONFIG_RPAREN_MASK 0x00000002 96 #define SI32_UART_B_CONFIG_RPAREN_SHIFT 1 97 // Do not expect a parity bit during receptions. 98 #define SI32_UART_B_CONFIG_RPAREN_DISABLED_VALUE 0 99 #define SI32_UART_B_CONFIG_RPAREN_DISABLED_U32 \ 100 (SI32_UART_B_CONFIG_RPAREN_DISABLED_VALUE << SI32_UART_B_CONFIG_RPAREN_SHIFT) 101 // Expect a parity bit during receptions. 102 #define SI32_UART_B_CONFIG_RPAREN_ENABLED_VALUE 1 103 #define SI32_UART_B_CONFIG_RPAREN_ENABLED_U32 \ 104 (SI32_UART_B_CONFIG_RPAREN_ENABLED_VALUE << SI32_UART_B_CONFIG_RPAREN_SHIFT) 105 106 #define SI32_UART_B_CONFIG_RSTPEN_MASK 0x00000004 107 #define SI32_UART_B_CONFIG_RSTPEN_SHIFT 2 108 // Do not expect stop bits during receptions. 109 #define SI32_UART_B_CONFIG_RSTPEN_DISABLED_VALUE 0 110 #define SI32_UART_B_CONFIG_RSTPEN_DISABLED_U32 \ 111 (SI32_UART_B_CONFIG_RSTPEN_DISABLED_VALUE << SI32_UART_B_CONFIG_RSTPEN_SHIFT) 112 // Expect stop bits during receptions. 113 #define SI32_UART_B_CONFIG_RSTPEN_ENABLED_VALUE 1 114 #define SI32_UART_B_CONFIG_RSTPEN_ENABLED_U32 \ 115 (SI32_UART_B_CONFIG_RSTPEN_ENABLED_VALUE << SI32_UART_B_CONFIG_RSTPEN_SHIFT) 116 117 #define SI32_UART_B_CONFIG_RSTPMD_MASK 0x00000018 118 #define SI32_UART_B_CONFIG_RSTPMD_SHIFT 3 119 // 0.5 stop bit. 120 #define SI32_UART_B_CONFIG_RSTPMD_0P5_STOP_VALUE 0 121 #define SI32_UART_B_CONFIG_RSTPMD_0P5_STOP_U32 \ 122 (SI32_UART_B_CONFIG_RSTPMD_0P5_STOP_VALUE << SI32_UART_B_CONFIG_RSTPMD_SHIFT) 123 // 1 stop bit. 124 #define SI32_UART_B_CONFIG_RSTPMD_1_STOP_VALUE 1 125 #define SI32_UART_B_CONFIG_RSTPMD_1_STOP_U32 \ 126 (SI32_UART_B_CONFIG_RSTPMD_1_STOP_VALUE << SI32_UART_B_CONFIG_RSTPMD_SHIFT) 127 // 1.5 stop bits. 128 #define SI32_UART_B_CONFIG_RSTPMD_1P5_STOP_VALUE 2 129 #define SI32_UART_B_CONFIG_RSTPMD_1P5_STOP_U32 \ 130 (SI32_UART_B_CONFIG_RSTPMD_1P5_STOP_VALUE << SI32_UART_B_CONFIG_RSTPMD_SHIFT) 131 // 2 stop bits. 132 #define SI32_UART_B_CONFIG_RSTPMD_2_STOP_VALUE 3 133 #define SI32_UART_B_CONFIG_RSTPMD_2_STOP_U32 \ 134 (SI32_UART_B_CONFIG_RSTPMD_2_STOP_VALUE << SI32_UART_B_CONFIG_RSTPMD_SHIFT) 135 136 #define SI32_UART_B_CONFIG_RPARMD_MASK 0x00000060 137 #define SI32_UART_B_CONFIG_RPARMD_SHIFT 5 138 // Odd Parity. 139 #define SI32_UART_B_CONFIG_RPARMD_ODD_VALUE 0 140 #define SI32_UART_B_CONFIG_RPARMD_ODD_U32 \ 141 (SI32_UART_B_CONFIG_RPARMD_ODD_VALUE << SI32_UART_B_CONFIG_RPARMD_SHIFT) 142 // Even Parity. 143 #define SI32_UART_B_CONFIG_RPARMD_EVEN_VALUE 1 144 #define SI32_UART_B_CONFIG_RPARMD_EVEN_U32 \ 145 (SI32_UART_B_CONFIG_RPARMD_EVEN_VALUE << SI32_UART_B_CONFIG_RPARMD_SHIFT) 146 // Set (Parity = 1). 147 #define SI32_UART_B_CONFIG_RPARMD_MARK_VALUE 2 148 #define SI32_UART_B_CONFIG_RPARMD_MARK_U32 \ 149 (SI32_UART_B_CONFIG_RPARMD_MARK_VALUE << SI32_UART_B_CONFIG_RPARMD_SHIFT) 150 // Clear (Parity = 0). 151 #define SI32_UART_B_CONFIG_RPARMD_SPACE_VALUE 3 152 #define SI32_UART_B_CONFIG_RPARMD_SPACE_U32 \ 153 (SI32_UART_B_CONFIG_RPARMD_SPACE_VALUE << SI32_UART_B_CONFIG_RPARMD_SHIFT) 154 155 #define SI32_UART_B_CONFIG_RDATLN_MASK 0x00000700 156 #define SI32_UART_B_CONFIG_RDATLN_SHIFT 8 157 // 5 bits. 158 #define SI32_UART_B_CONFIG_RDATLN_5_BITS_VALUE 0 159 #define SI32_UART_B_CONFIG_RDATLN_5_BITS_U32 \ 160 (SI32_UART_B_CONFIG_RDATLN_5_BITS_VALUE << SI32_UART_B_CONFIG_RDATLN_SHIFT) 161 // 6 bits. 162 #define SI32_UART_B_CONFIG_RDATLN_6_BITS_VALUE 1 163 #define SI32_UART_B_CONFIG_RDATLN_6_BITS_U32 \ 164 (SI32_UART_B_CONFIG_RDATLN_6_BITS_VALUE << SI32_UART_B_CONFIG_RDATLN_SHIFT) 165 // 7 bits. 166 #define SI32_UART_B_CONFIG_RDATLN_7_BITS_VALUE 2 167 #define SI32_UART_B_CONFIG_RDATLN_7_BITS_U32 \ 168 (SI32_UART_B_CONFIG_RDATLN_7_BITS_VALUE << SI32_UART_B_CONFIG_RDATLN_SHIFT) 169 // 8 bits. 170 #define SI32_UART_B_CONFIG_RDATLN_8_BITS_VALUE 3 171 #define SI32_UART_B_CONFIG_RDATLN_8_BITS_U32 \ 172 (SI32_UART_B_CONFIG_RDATLN_8_BITS_VALUE << SI32_UART_B_CONFIG_RDATLN_SHIFT) 173 // 9 bits. The 9th bit is stored in the FIFO (normal mode). 174 #define SI32_UART_B_CONFIG_RDATLN_9_BITS_STORED_VALUE 4 175 #define SI32_UART_B_CONFIG_RDATLN_9_BITS_STORED_U32 \ 176 (SI32_UART_B_CONFIG_RDATLN_9_BITS_STORED_VALUE << SI32_UART_B_CONFIG_RDATLN_SHIFT) 177 // 9 bits. The 9th bit is not stored in the FIFO (fixed mode). This mode is used 178 // when the 9th bit is only used for match operations (see MATMD). 179 #define SI32_UART_B_CONFIG_RDATLN_9_BITS_MATCH_VALUE 5 180 #define SI32_UART_B_CONFIG_RDATLN_9_BITS_MATCH_U32 \ 181 (SI32_UART_B_CONFIG_RDATLN_9_BITS_MATCH_VALUE << SI32_UART_B_CONFIG_RDATLN_SHIFT) 182 183 #define SI32_UART_B_CONFIG_RIRDAEN_MASK 0x00002000 184 #define SI32_UART_B_CONFIG_RIRDAEN_SHIFT 13 185 // The receiver does not operate in IrDA mode. 186 #define SI32_UART_B_CONFIG_RIRDAEN_DISABLED_VALUE 0 187 #define SI32_UART_B_CONFIG_RIRDAEN_DISABLED_U32 \ 188 (SI32_UART_B_CONFIG_RIRDAEN_DISABLED_VALUE << SI32_UART_B_CONFIG_RIRDAEN_SHIFT) 189 // The receiver operates in IrDA mode. 190 #define SI32_UART_B_CONFIG_RIRDAEN_ENABLED_VALUE 1 191 #define SI32_UART_B_CONFIG_RIRDAEN_ENABLED_U32 \ 192 (SI32_UART_B_CONFIG_RIRDAEN_ENABLED_VALUE << SI32_UART_B_CONFIG_RIRDAEN_SHIFT) 193 194 #define SI32_UART_B_CONFIG_RINVEN_MASK 0x00004000 195 #define SI32_UART_B_CONFIG_RINVEN_SHIFT 14 196 // Do not invert the RX pin signals (the RX idle state is high). 197 #define SI32_UART_B_CONFIG_RINVEN_DISABLED_VALUE 0 198 #define SI32_UART_B_CONFIG_RINVEN_DISABLED_U32 \ 199 (SI32_UART_B_CONFIG_RINVEN_DISABLED_VALUE << SI32_UART_B_CONFIG_RINVEN_SHIFT) 200 // Invert the RX pin signals (the RX idle state is low). 201 #define SI32_UART_B_CONFIG_RINVEN_ENABLED_VALUE 1 202 #define SI32_UART_B_CONFIG_RINVEN_ENABLED_U32 \ 203 (SI32_UART_B_CONFIG_RINVEN_ENABLED_VALUE << SI32_UART_B_CONFIG_RINVEN_SHIFT) 204 205 #define SI32_UART_B_CONFIG_TSTRTEN_MASK 0x00010000 206 #define SI32_UART_B_CONFIG_TSTRTEN_SHIFT 16 207 // Do not generate a start bit during transmissions. 208 #define SI32_UART_B_CONFIG_TSTRTEN_DISABLED_VALUE 0 209 #define SI32_UART_B_CONFIG_TSTRTEN_DISABLED_U32 \ 210 (SI32_UART_B_CONFIG_TSTRTEN_DISABLED_VALUE << SI32_UART_B_CONFIG_TSTRTEN_SHIFT) 211 // Generate a start bit during transmissions. 212 #define SI32_UART_B_CONFIG_TSTRTEN_ENABLED_VALUE 1 213 #define SI32_UART_B_CONFIG_TSTRTEN_ENABLED_U32 \ 214 (SI32_UART_B_CONFIG_TSTRTEN_ENABLED_VALUE << SI32_UART_B_CONFIG_TSTRTEN_SHIFT) 215 216 #define SI32_UART_B_CONFIG_TPAREN_MASK 0x00020000 217 #define SI32_UART_B_CONFIG_TPAREN_SHIFT 17 218 // Do not send a parity bit during transmissions. 219 #define SI32_UART_B_CONFIG_TPAREN_DISABLED_VALUE 0 220 #define SI32_UART_B_CONFIG_TPAREN_DISABLED_U32 \ 221 (SI32_UART_B_CONFIG_TPAREN_DISABLED_VALUE << SI32_UART_B_CONFIG_TPAREN_SHIFT) 222 // Send a parity bit during transmissions. 223 #define SI32_UART_B_CONFIG_TPAREN_ENABLED_VALUE 1 224 #define SI32_UART_B_CONFIG_TPAREN_ENABLED_U32 \ 225 (SI32_UART_B_CONFIG_TPAREN_ENABLED_VALUE << SI32_UART_B_CONFIG_TPAREN_SHIFT) 226 227 #define SI32_UART_B_CONFIG_TSTPEN_MASK 0x00040000 228 #define SI32_UART_B_CONFIG_TSTPEN_SHIFT 18 229 // Do not send stop bits during transmissions. 230 #define SI32_UART_B_CONFIG_TSTPEN_DISABLED_VALUE 0 231 #define SI32_UART_B_CONFIG_TSTPEN_DISABLED_U32 \ 232 (SI32_UART_B_CONFIG_TSTPEN_DISABLED_VALUE << SI32_UART_B_CONFIG_TSTPEN_SHIFT) 233 // Send stop bits during transmissions. 234 #define SI32_UART_B_CONFIG_TSTPEN_ENABLED_VALUE 1 235 #define SI32_UART_B_CONFIG_TSTPEN_ENABLED_U32 \ 236 (SI32_UART_B_CONFIG_TSTPEN_ENABLED_VALUE << SI32_UART_B_CONFIG_TSTPEN_SHIFT) 237 238 #define SI32_UART_B_CONFIG_TSTPMD_MASK 0x00180000 239 #define SI32_UART_B_CONFIG_TSTPMD_SHIFT 19 240 // 0.5 stop bit. 241 #define SI32_UART_B_CONFIG_TSTPMD_0P5_STOP_VALUE 0 242 #define SI32_UART_B_CONFIG_TSTPMD_0P5_STOP_U32 \ 243 (SI32_UART_B_CONFIG_TSTPMD_0P5_STOP_VALUE << SI32_UART_B_CONFIG_TSTPMD_SHIFT) 244 // 1 stop bit. 245 #define SI32_UART_B_CONFIG_TSTPMD_1_STOP_VALUE 1 246 #define SI32_UART_B_CONFIG_TSTPMD_1_STOP_U32 \ 247 (SI32_UART_B_CONFIG_TSTPMD_1_STOP_VALUE << SI32_UART_B_CONFIG_TSTPMD_SHIFT) 248 // 1.5 stop bits. 249 #define SI32_UART_B_CONFIG_TSTPMD_1P5_STOP_VALUE 2 250 #define SI32_UART_B_CONFIG_TSTPMD_1P5_STOP_U32 \ 251 (SI32_UART_B_CONFIG_TSTPMD_1P5_STOP_VALUE << SI32_UART_B_CONFIG_TSTPMD_SHIFT) 252 // 2 stop bits. 253 #define SI32_UART_B_CONFIG_TSTPMD_2_STOP_VALUE 3 254 #define SI32_UART_B_CONFIG_TSTPMD_2_STOP_U32 \ 255 (SI32_UART_B_CONFIG_TSTPMD_2_STOP_VALUE << SI32_UART_B_CONFIG_TSTPMD_SHIFT) 256 257 #define SI32_UART_B_CONFIG_TPARMD_MASK 0x00600000 258 #define SI32_UART_B_CONFIG_TPARMD_SHIFT 21 259 // Odd Parity. 260 #define SI32_UART_B_CONFIG_TPARMD_ODD_VALUE 0 261 #define SI32_UART_B_CONFIG_TPARMD_ODD_U32 \ 262 (SI32_UART_B_CONFIG_TPARMD_ODD_VALUE << SI32_UART_B_CONFIG_TPARMD_SHIFT) 263 // Even Parity. 264 #define SI32_UART_B_CONFIG_TPARMD_EVEN_VALUE 1 265 #define SI32_UART_B_CONFIG_TPARMD_EVEN_U32 \ 266 (SI32_UART_B_CONFIG_TPARMD_EVEN_VALUE << SI32_UART_B_CONFIG_TPARMD_SHIFT) 267 // Set (Parity = 1). 268 #define SI32_UART_B_CONFIG_TPARMD_MARK_VALUE 2 269 #define SI32_UART_B_CONFIG_TPARMD_MARK_U32 \ 270 (SI32_UART_B_CONFIG_TPARMD_MARK_VALUE << SI32_UART_B_CONFIG_TPARMD_SHIFT) 271 // Clear (Parity = 0). 272 #define SI32_UART_B_CONFIG_TPARMD_SPACE_VALUE 3 273 #define SI32_UART_B_CONFIG_TPARMD_SPACE_U32 \ 274 (SI32_UART_B_CONFIG_TPARMD_SPACE_VALUE << SI32_UART_B_CONFIG_TPARMD_SHIFT) 275 276 #define SI32_UART_B_CONFIG_TDATLN_MASK 0x07000000 277 #define SI32_UART_B_CONFIG_TDATLN_SHIFT 24 278 // 5 bits. 279 #define SI32_UART_B_CONFIG_TDATLN_5_BITS_VALUE 0 280 #define SI32_UART_B_CONFIG_TDATLN_5_BITS_U32 \ 281 (SI32_UART_B_CONFIG_TDATLN_5_BITS_VALUE << SI32_UART_B_CONFIG_TDATLN_SHIFT) 282 // 6 bits. 283 #define SI32_UART_B_CONFIG_TDATLN_6_BITS_VALUE 1 284 #define SI32_UART_B_CONFIG_TDATLN_6_BITS_U32 \ 285 (SI32_UART_B_CONFIG_TDATLN_6_BITS_VALUE << SI32_UART_B_CONFIG_TDATLN_SHIFT) 286 // 7 bits. 287 #define SI32_UART_B_CONFIG_TDATLN_7_BITS_VALUE 2 288 #define SI32_UART_B_CONFIG_TDATLN_7_BITS_U32 \ 289 (SI32_UART_B_CONFIG_TDATLN_7_BITS_VALUE << SI32_UART_B_CONFIG_TDATLN_SHIFT) 290 // 8 bits. 291 #define SI32_UART_B_CONFIG_TDATLN_8_BITS_VALUE 3 292 #define SI32_UART_B_CONFIG_TDATLN_8_BITS_U32 \ 293 (SI32_UART_B_CONFIG_TDATLN_8_BITS_VALUE << SI32_UART_B_CONFIG_TDATLN_SHIFT) 294 // 9 bits. The 9th bit is taken from the FIFO data (normal mode). 295 #define SI32_UART_B_CONFIG_TDATLN_9_BITS_FIFO_VALUE 4 296 #define SI32_UART_B_CONFIG_TDATLN_9_BITS_FIFO_U32 \ 297 (SI32_UART_B_CONFIG_TDATLN_9_BITS_FIFO_VALUE << SI32_UART_B_CONFIG_TDATLN_SHIFT) 298 // 9 bits. The 9th bit is set by the value of TBIT (fixed mode). 299 #define SI32_UART_B_CONFIG_TDATLN_9_BITS_TBIT_VALUE 5 300 #define SI32_UART_B_CONFIG_TDATLN_9_BITS_TBIT_U32 \ 301 (SI32_UART_B_CONFIG_TDATLN_9_BITS_TBIT_VALUE << SI32_UART_B_CONFIG_TDATLN_SHIFT) 302 303 #define SI32_UART_B_CONFIG_TIRDAEN_MASK 0x20000000 304 #define SI32_UART_B_CONFIG_TIRDAEN_SHIFT 29 305 // Disable IrDA transmit mode. 306 #define SI32_UART_B_CONFIG_TIRDAEN_DISABLED_VALUE 0 307 #define SI32_UART_B_CONFIG_TIRDAEN_DISABLED_U32 \ 308 (SI32_UART_B_CONFIG_TIRDAEN_DISABLED_VALUE << SI32_UART_B_CONFIG_TIRDAEN_SHIFT) 309 // Enable IrDA transmit mode. 310 #define SI32_UART_B_CONFIG_TIRDAEN_ENABLED_VALUE 1 311 #define SI32_UART_B_CONFIG_TIRDAEN_ENABLED_U32 \ 312 (SI32_UART_B_CONFIG_TIRDAEN_ENABLED_VALUE << SI32_UART_B_CONFIG_TIRDAEN_SHIFT) 313 314 #define SI32_UART_B_CONFIG_TINVEN_MASK 0x40000000 315 #define SI32_UART_B_CONFIG_TINVEN_SHIFT 30 316 // Do not invert the TX pin signals (the TX idle state is high). 317 #define SI32_UART_B_CONFIG_TINVEN_DISABLED_VALUE 0 318 #define SI32_UART_B_CONFIG_TINVEN_DISABLED_U32 \ 319 (SI32_UART_B_CONFIG_TINVEN_DISABLED_VALUE << SI32_UART_B_CONFIG_TINVEN_SHIFT) 320 // Invert the TX pin signals (the TX idle state is low). 321 #define SI32_UART_B_CONFIG_TINVEN_ENABLED_VALUE 1 322 #define SI32_UART_B_CONFIG_TINVEN_ENABLED_U32 \ 323 (SI32_UART_B_CONFIG_TINVEN_ENABLED_VALUE << SI32_UART_B_CONFIG_TINVEN_SHIFT) 324 325 326 327 struct SI32_UART_B_MODE_Struct 328 { 329 union 330 { 331 struct 332 { 333 uint32_t reserved0: 8; 334 // RTC Clock Mode 335 volatile uint32_t RTCCKMD: 1; 336 // RTC Baud Rate Mode 337 volatile uint32_t RTCBDMD: 1; 338 // Force Clock On 339 volatile uint32_t FORCECLK: 1; 340 // Clock Switch Busy Status 341 volatile uint32_t CLKBUSY: 1; 342 // Receive Automatic Clock Switch 343 volatile uint32_t RXCLKSW: 1; 344 // Transmit Automatic Clock Switch 345 volatile uint32_t TXCLKSW: 1; 346 uint32_t reserved1: 2; 347 // UART Debug Mode 348 volatile uint32_t DBGMD: 1; 349 uint32_t reserved2: 1; 350 // Loop Back Mode 351 volatile uint32_t LBMD: 2; 352 uint32_t reserved3: 7; 353 // Duplex Mode 354 volatile uint32_t DUPLEXMD: 1; 355 uint32_t reserved4: 2; 356 // Idle TX Tristate Enable 357 volatile uint32_t ITSEN: 1; 358 uint32_t reserved5: 1; 359 }; 360 volatile uint32_t U32; 361 }; 362 }; 363 364 #define SI32_UART_B_MODE_RTCCKMD_MASK 0x00000100 365 #define SI32_UART_B_MODE_RTCCKMD_SHIFT 8 366 // UART clocked from the APB clock. The RBAUD and TBAUD controls will use the APB 367 // clock mode to determine the baudrate unless RTCBDMD = 1. 368 #define SI32_UART_B_MODE_RTCCKMD_APBCLK_VALUE 0 369 #define SI32_UART_B_MODE_RTCCKMD_APBCLK_U32 \ 370 (SI32_UART_B_MODE_RTCCKMD_APBCLK_VALUE << SI32_UART_B_MODE_RTCCKMD_SHIFT) 371 // UART clocked from RTC0TCLK. The RBAUD and TBAUD controls will use the RTC0TCLK 372 // mode to determine the baudrate. Software should only set this bit to one when 373 // the UART is idle. 374 #define SI32_UART_B_MODE_RTCCKMD_RTC0TCLK_VALUE 1 375 #define SI32_UART_B_MODE_RTCCKMD_RTC0TCLK_U32 \ 376 (SI32_UART_B_MODE_RTCCKMD_RTC0TCLK_VALUE << SI32_UART_B_MODE_RTCCKMD_SHIFT) 377 378 #define SI32_UART_B_MODE_RTCBDMD_MASK 0x00000200 379 #define SI32_UART_B_MODE_RTCBDMD_SHIFT 9 380 // The RBAUD and TBAUD controls use the RTCCKMD setting to determine whether to use 381 // APB clock mode (RTCCKMD = 0) or the RTC0TCLK mode (RTCCKMD = 1). Use this 382 // setting when APB clock != RTC0TCLK. 383 #define SI32_UART_B_MODE_RTCBDMD_DISABLED_VALUE 0 384 #define SI32_UART_B_MODE_RTCBDMD_DISABLED_U32 \ 385 (SI32_UART_B_MODE_RTCBDMD_DISABLED_VALUE << SI32_UART_B_MODE_RTCBDMD_SHIFT) 386 // The RBAUD and TBAUD controls use RTC0TCLK mode. Use this setting when APB clock 387 // = RTC0TCLK and RTCCKMD = 0 to force the RBAUD and TBAUD controls into RTC0TCLK 388 // mode. 389 #define SI32_UART_B_MODE_RTCBDMD_ENABLED_VALUE 1 390 #define SI32_UART_B_MODE_RTCBDMD_ENABLED_U32 \ 391 (SI32_UART_B_MODE_RTCBDMD_ENABLED_VALUE << SI32_UART_B_MODE_RTCBDMD_SHIFT) 392 393 #define SI32_UART_B_MODE_FORCECLK_MASK 0x00000400 394 #define SI32_UART_B_MODE_FORCECLK_SHIFT 10 395 // UART clock is only on when necessary. 396 #define SI32_UART_B_MODE_FORCECLK_DISABLED_VALUE 0 397 #define SI32_UART_B_MODE_FORCECLK_DISABLED_U32 \ 398 (SI32_UART_B_MODE_FORCECLK_DISABLED_VALUE << SI32_UART_B_MODE_FORCECLK_SHIFT) 399 // Force the UART clock to always be on. 400 #define SI32_UART_B_MODE_FORCECLK_ENABLED_VALUE 1 401 #define SI32_UART_B_MODE_FORCECLK_ENABLED_U32 \ 402 (SI32_UART_B_MODE_FORCECLK_ENABLED_VALUE << SI32_UART_B_MODE_FORCECLK_SHIFT) 403 404 #define SI32_UART_B_MODE_CLKBUSY_MASK 0x00000800 405 #define SI32_UART_B_MODE_CLKBUSY_SHIFT 11 406 // Clock switch completed. 407 #define SI32_UART_B_MODE_CLKBUSY_IDLE_VALUE 0 408 #define SI32_UART_B_MODE_CLKBUSY_IDLE_U32 \ 409 (SI32_UART_B_MODE_CLKBUSY_IDLE_VALUE << SI32_UART_B_MODE_CLKBUSY_SHIFT) 410 // Clock switch in progress. 411 #define SI32_UART_B_MODE_CLKBUSY_BUSY_VALUE 1 412 #define SI32_UART_B_MODE_CLKBUSY_BUSY_U32 \ 413 (SI32_UART_B_MODE_CLKBUSY_BUSY_VALUE << SI32_UART_B_MODE_CLKBUSY_SHIFT) 414 415 #define SI32_UART_B_MODE_RXCLKSW_MASK 0x00001000 416 #define SI32_UART_B_MODE_RXCLKSW_SHIFT 12 417 // UART will always use the selected clock for receive operations. 418 #define SI32_UART_B_MODE_RXCLKSW_DISABLED_VALUE 0 419 #define SI32_UART_B_MODE_RXCLKSW_DISABLED_U32 \ 420 (SI32_UART_B_MODE_RXCLKSW_DISABLED_VALUE << SI32_UART_B_MODE_RXCLKSW_SHIFT) 421 // UART will automatically switch from RTC0TCLK to the APB clock when a receive 422 // interrupt is pending. 423 #define SI32_UART_B_MODE_RXCLKSW_ENABLED_VALUE 1 424 #define SI32_UART_B_MODE_RXCLKSW_ENABLED_U32 \ 425 (SI32_UART_B_MODE_RXCLKSW_ENABLED_VALUE << SI32_UART_B_MODE_RXCLKSW_SHIFT) 426 427 #define SI32_UART_B_MODE_TXCLKSW_MASK 0x00002000 428 #define SI32_UART_B_MODE_TXCLKSW_SHIFT 13 429 // UART will always use the selected clock for transmit operations. 430 #define SI32_UART_B_MODE_TXCLKSW_DISABLED_VALUE 0 431 #define SI32_UART_B_MODE_TXCLKSW_DISABLED_U32 \ 432 (SI32_UART_B_MODE_TXCLKSW_DISABLED_VALUE << SI32_UART_B_MODE_TXCLKSW_SHIFT) 433 // UART will automatically switch from RTC0TCLK to the APB clock when a transmit 434 // interrupt is pending. 435 #define SI32_UART_B_MODE_TXCLKSW_ENABLED_VALUE 1 436 #define SI32_UART_B_MODE_TXCLKSW_ENABLED_U32 \ 437 (SI32_UART_B_MODE_TXCLKSW_ENABLED_VALUE << SI32_UART_B_MODE_TXCLKSW_SHIFT) 438 439 #define SI32_UART_B_MODE_DBGMD_MASK 0x00010000 440 #define SI32_UART_B_MODE_DBGMD_SHIFT 16 441 // The UART module will continue to operate while the core is halted in debug mode. 442 #define SI32_UART_B_MODE_DBGMD_RUN_VALUE 0 443 #define SI32_UART_B_MODE_DBGMD_RUN_U32 \ 444 (SI32_UART_B_MODE_DBGMD_RUN_VALUE << SI32_UART_B_MODE_DBGMD_SHIFT) 445 // A debug breakpoint will cause the UART module to halt. Any active transmissions 446 // and receptions will complete first. 447 #define SI32_UART_B_MODE_DBGMD_HALT_VALUE 1 448 #define SI32_UART_B_MODE_DBGMD_HALT_U32 \ 449 (SI32_UART_B_MODE_DBGMD_HALT_VALUE << SI32_UART_B_MODE_DBGMD_SHIFT) 450 451 #define SI32_UART_B_MODE_LBMD_MASK 0x000C0000 452 #define SI32_UART_B_MODE_LBMD_SHIFT 18 453 // Loop back is disabled and the TX and RX signals are connected to the 454 // corresponding external pins. 455 #define SI32_UART_B_MODE_LBMD_DISABLED_VALUE 0 456 #define SI32_UART_B_MODE_LBMD_DISABLED_U32 \ 457 (SI32_UART_B_MODE_LBMD_DISABLED_VALUE << SI32_UART_B_MODE_LBMD_SHIFT) 458 // Receive loop back. The receiver input path is disconnected from the RX pin and 459 // internally connected to the transmitter. Data transmitted will be sent out on TX 460 // and also received by the device. 461 #define SI32_UART_B_MODE_LBMD_RXONLY_VALUE 1 462 #define SI32_UART_B_MODE_LBMD_RXONLY_U32 \ 463 (SI32_UART_B_MODE_LBMD_RXONLY_VALUE << SI32_UART_B_MODE_LBMD_SHIFT) 464 // Transmit loop back. The transmitter output path is disconnected from the TX pin 465 // and the RX input pin is internally looped back out to the TX pin. Data received 466 // at RX will be received by the device and also sent directly back out on TX. 467 #define SI32_UART_B_MODE_LBMD_TXONLY_VALUE 2 468 #define SI32_UART_B_MODE_LBMD_TXONLY_U32 \ 469 (SI32_UART_B_MODE_LBMD_TXONLY_VALUE << SI32_UART_B_MODE_LBMD_SHIFT) 470 // Full loop back. Internally, the transmitter output is routed back to the 471 // receiver input. Neither the transmitter nor receiver are connected to external 472 // device pins. The device pin RX is looped back to TX in a similar fashion. Data 473 // transmitted on TX will be sent directly back in on RX. 474 #define SI32_UART_B_MODE_LBMD_BOTH_VALUE 3 475 #define SI32_UART_B_MODE_LBMD_BOTH_U32 \ 476 (SI32_UART_B_MODE_LBMD_BOTH_VALUE << SI32_UART_B_MODE_LBMD_SHIFT) 477 478 #define SI32_UART_B_MODE_DUPLEXMD_MASK 0x08000000 479 #define SI32_UART_B_MODE_DUPLEXMD_SHIFT 27 480 // Full-duplex mode. The transmitter and receiver can operate simultaneously. 481 #define SI32_UART_B_MODE_DUPLEXMD_FULL_DUPLEX_VALUE 0 482 #define SI32_UART_B_MODE_DUPLEXMD_FULL_DUPLEX_U32 \ 483 (SI32_UART_B_MODE_DUPLEXMD_FULL_DUPLEX_VALUE << SI32_UART_B_MODE_DUPLEXMD_SHIFT) 484 // Half-duplex mode. The transmitter automatically inhibits when the receiver is 485 // active and the receiver automatically inhibits when the transmitter is active. 486 #define SI32_UART_B_MODE_DUPLEXMD_HALF_DUPLEX_VALUE 1 487 #define SI32_UART_B_MODE_DUPLEXMD_HALF_DUPLEX_U32 \ 488 (SI32_UART_B_MODE_DUPLEXMD_HALF_DUPLEX_VALUE << SI32_UART_B_MODE_DUPLEXMD_SHIFT) 489 490 #define SI32_UART_B_MODE_ITSEN_MASK 0x40000000 491 #define SI32_UART_B_MODE_ITSEN_SHIFT 30 492 // The TX pin is always an output in this mode, even when idle. 493 #define SI32_UART_B_MODE_ITSEN_DISABLED_VALUE 0 494 #define SI32_UART_B_MODE_ITSEN_DISABLED_U32 \ 495 (SI32_UART_B_MODE_ITSEN_DISABLED_VALUE << SI32_UART_B_MODE_ITSEN_SHIFT) 496 // The TX pin is tristated when idle. 497 #define SI32_UART_B_MODE_ITSEN_ENABLED_VALUE 1 498 #define SI32_UART_B_MODE_ITSEN_ENABLED_U32 \ 499 (SI32_UART_B_MODE_ITSEN_ENABLED_VALUE << SI32_UART_B_MODE_ITSEN_SHIFT) 500 501 502 503 struct SI32_UART_B_FLOWCN_Struct 504 { 505 union 506 { 507 struct 508 { 509 uint32_t reserved0: 1; 510 // RX Pin Status 511 volatile uint32_t RX: 1; 512 uint32_t reserved1: 10; 513 // TX Output Enable 514 volatile uint32_t TXOEN: 1; 515 uint32_t reserved2: 4; 516 // TX State 517 volatile uint32_t TX: 1; 518 uint32_t reserved3: 10; 519 // Transmit IrDA Pulse Width 520 volatile uint32_t TIRDAPW: 2; 521 uint32_t reserved4: 2; 522 }; 523 volatile uint32_t U32; 524 }; 525 }; 526 527 #define SI32_UART_B_FLOWCN_RX_MASK 0x00000002 528 #define SI32_UART_B_FLOWCN_RX_SHIFT 1 529 // RX pin (after optional inversion) is low. 530 #define SI32_UART_B_FLOWCN_RX_LOW_VALUE 0 531 #define SI32_UART_B_FLOWCN_RX_LOW_U32 \ 532 (SI32_UART_B_FLOWCN_RX_LOW_VALUE << SI32_UART_B_FLOWCN_RX_SHIFT) 533 // RX pin (after optional inversion) is high. 534 #define SI32_UART_B_FLOWCN_RX_HIGH_VALUE 1 535 #define SI32_UART_B_FLOWCN_RX_HIGH_U32 \ 536 (SI32_UART_B_FLOWCN_RX_HIGH_VALUE << SI32_UART_B_FLOWCN_RX_SHIFT) 537 538 #define SI32_UART_B_FLOWCN_TXOEN_MASK 0x00001000 539 #define SI32_UART_B_FLOWCN_TXOEN_SHIFT 12 540 // The pin assigned to TX is controlled by the direct port output value. 541 #define SI32_UART_B_FLOWCN_TXOEN_DISABLED_VALUE 0 542 #define SI32_UART_B_FLOWCN_TXOEN_DISABLED_U32 \ 543 (SI32_UART_B_FLOWCN_TXOEN_DISABLED_VALUE << SI32_UART_B_FLOWCN_TXOEN_SHIFT) 544 // The pin assigned to TX is controlled by the UART. 545 #define SI32_UART_B_FLOWCN_TXOEN_ENABLED_VALUE 1 546 #define SI32_UART_B_FLOWCN_TXOEN_ENABLED_U32 \ 547 (SI32_UART_B_FLOWCN_TXOEN_ENABLED_VALUE << SI32_UART_B_FLOWCN_TXOEN_SHIFT) 548 549 #define SI32_UART_B_FLOWCN_TX_MASK 0x00020000 550 #define SI32_UART_B_FLOWCN_TX_SHIFT 17 551 // The TX pin (before optional inversion) is low. 552 #define SI32_UART_B_FLOWCN_TX_LOW_VALUE 0 553 #define SI32_UART_B_FLOWCN_TX_LOW_U32 \ 554 (SI32_UART_B_FLOWCN_TX_LOW_VALUE << SI32_UART_B_FLOWCN_TX_SHIFT) 555 // The TX pin (before optional inversion) is high. 556 #define SI32_UART_B_FLOWCN_TX_HIGH_VALUE 1 557 #define SI32_UART_B_FLOWCN_TX_HIGH_U32 \ 558 (SI32_UART_B_FLOWCN_TX_HIGH_VALUE << SI32_UART_B_FLOWCN_TX_SHIFT) 559 560 #define SI32_UART_B_FLOWCN_TIRDAPW_MASK 0x30000000 561 #define SI32_UART_B_FLOWCN_TIRDAPW_SHIFT 28 562 // The IrDA pulse width is 1/16th of a bit period. 563 #define SI32_UART_B_FLOWCN_TIRDAPW_1_16TH_VALUE 0 564 #define SI32_UART_B_FLOWCN_TIRDAPW_1_16TH_U32 \ 565 (SI32_UART_B_FLOWCN_TIRDAPW_1_16TH_VALUE << SI32_UART_B_FLOWCN_TIRDAPW_SHIFT) 566 // The IrDA pulse width is 1/8th of a bit period. 567 #define SI32_UART_B_FLOWCN_TIRDAPW_1_8TH_VALUE 1 568 #define SI32_UART_B_FLOWCN_TIRDAPW_1_8TH_U32 \ 569 (SI32_UART_B_FLOWCN_TIRDAPW_1_8TH_VALUE << SI32_UART_B_FLOWCN_TIRDAPW_SHIFT) 570 // The IrDA pulse width is 3/16th of a bit period. 571 #define SI32_UART_B_FLOWCN_TIRDAPW_3_16TH_VALUE 2 572 #define SI32_UART_B_FLOWCN_TIRDAPW_3_16TH_U32 \ 573 (SI32_UART_B_FLOWCN_TIRDAPW_3_16TH_VALUE << SI32_UART_B_FLOWCN_TIRDAPW_SHIFT) 574 // The IrDA pulse width is 1/4th of a bit period. 575 #define SI32_UART_B_FLOWCN_TIRDAPW_1_4TH_VALUE 3 576 #define SI32_UART_B_FLOWCN_TIRDAPW_1_4TH_U32 \ 577 (SI32_UART_B_FLOWCN_TIRDAPW_1_4TH_VALUE << SI32_UART_B_FLOWCN_TIRDAPW_SHIFT) 578 579 580 581 struct SI32_UART_B_CONTROL_Struct 582 { 583 union 584 { 585 struct 586 { 587 // Receive Frame Error Interrupt Flag 588 volatile uint32_t RFRMERI: 1; 589 // Receive Parity Error Interrupt Flag 590 volatile uint32_t RPARERI: 1; 591 // Receive Overrun Error Interrupt Flag 592 volatile uint32_t ROREI: 1; 593 // Receive Data Request Interrupt Flag 594 volatile uint32_t RDREQI: 1; 595 uint32_t reserved0: 1; 596 // Receive Error Interrupt Enable 597 volatile uint32_t RERIEN: 1; 598 // Receive Data Request Interrupt Enable 599 volatile uint32_t RDREQIEN: 1; 600 uint32_t reserved1: 1; 601 // Match Mode 602 volatile uint32_t MATMD: 2; 603 // Receiver Auto-Baud Enable 604 volatile uint32_t RABDEN: 1; 605 // Receiver Busy Flag 606 volatile uint32_t RBUSYF: 1; 607 // Last Receive Bit 608 volatile uint32_t RBIT: 1; 609 // Receiver One-Shot Enable 610 volatile uint32_t ROSEN: 1; 611 // Receiver Inhibit 612 volatile uint32_t RINH: 1; 613 // Receiver Enable 614 volatile uint32_t REN: 1; 615 uint32_t reserved2: 2; 616 // Transmit Data Request Interrupt Flag 617 volatile uint32_t TDREQI: 1; 618 // Transmit Complete Interrupt Flag 619 volatile uint32_t TCPTI: 1; 620 // Transmit Complete Threshold 621 volatile uint32_t TCPTTH: 1; 622 uint32_t reserved3: 1; 623 // Transmit Data Request Interrupt Enable 624 volatile uint32_t TDREQIEN: 1; 625 // Transmit Complete Interrupt Enable 626 volatile uint32_t TCPTIEN: 1; 627 uint32_t reserved4: 3; 628 // Transmitter Busy Flag 629 volatile uint32_t TBUSYF: 1; 630 // Last Transmit Bit 631 volatile uint32_t TBIT: 1; 632 uint32_t reserved5: 1; 633 // Transmit Inhibit 634 volatile uint32_t TINH: 1; 635 // Transmitter Enable 636 volatile uint32_t TEN: 1; 637 }; 638 volatile uint32_t U32; 639 }; 640 }; 641 642 #define SI32_UART_B_CONTROL_RFRMERI_MASK 0x00000001 643 #define SI32_UART_B_CONTROL_RFRMERI_SHIFT 0 644 // Read: A frame error has not occurred since RFRMERI was last cleared. Write: 645 // Clear the interrupt. 646 #define SI32_UART_B_CONTROL_RFRMERI_NOT_SET_VALUE 0 647 #define SI32_UART_B_CONTROL_RFRMERI_NOT_SET_U32 \ 648 (SI32_UART_B_CONTROL_RFRMERI_NOT_SET_VALUE << SI32_UART_B_CONTROL_RFRMERI_SHIFT) 649 // Read: A frame error occurred. Write: Force a frame error interrupt. 650 #define SI32_UART_B_CONTROL_RFRMERI_SET_VALUE 1 651 #define SI32_UART_B_CONTROL_RFRMERI_SET_U32 \ 652 (SI32_UART_B_CONTROL_RFRMERI_SET_VALUE << SI32_UART_B_CONTROL_RFRMERI_SHIFT) 653 654 #define SI32_UART_B_CONTROL_RPARERI_MASK 0x00000002 655 #define SI32_UART_B_CONTROL_RPARERI_SHIFT 1 656 // Read: An invalid parity bit has not been received since RPARERI was last 657 // cleared. Write: Clear the interrupt. 658 #define SI32_UART_B_CONTROL_RPARERI_NOT_SET_VALUE 0 659 #define SI32_UART_B_CONTROL_RPARERI_NOT_SET_U32 \ 660 (SI32_UART_B_CONTROL_RPARERI_NOT_SET_VALUE << SI32_UART_B_CONTROL_RPARERI_SHIFT) 661 // Read: An invalid parity bit has been received since RPARERI was last cleared. 662 // Write: Force a parity error interrupt. 663 #define SI32_UART_B_CONTROL_RPARERI_SET_VALUE 1 664 #define SI32_UART_B_CONTROL_RPARERI_SET_U32 \ 665 (SI32_UART_B_CONTROL_RPARERI_SET_VALUE << SI32_UART_B_CONTROL_RPARERI_SHIFT) 666 667 #define SI32_UART_B_CONTROL_ROREI_MASK 0x00000004 668 #define SI32_UART_B_CONTROL_ROREI_SHIFT 2 669 // Read: A receiver overrun has not occurred since ROREI was last cleared. Write: 670 // Clear the interrupt. 671 #define SI32_UART_B_CONTROL_ROREI_NOT_SET_VALUE 0 672 #define SI32_UART_B_CONTROL_ROREI_NOT_SET_U32 \ 673 (SI32_UART_B_CONTROL_ROREI_NOT_SET_VALUE << SI32_UART_B_CONTROL_ROREI_SHIFT) 674 // Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. 675 #define SI32_UART_B_CONTROL_ROREI_SET_VALUE 1 676 #define SI32_UART_B_CONTROL_ROREI_SET_U32 \ 677 (SI32_UART_B_CONTROL_ROREI_SET_VALUE << SI32_UART_B_CONTROL_ROREI_SHIFT) 678 679 #define SI32_UART_B_CONTROL_RDREQI_MASK 0x00000008 680 #define SI32_UART_B_CONTROL_RDREQI_SHIFT 3 681 // Fewer than RFTH FIFO entries are filled with data. 682 #define SI32_UART_B_CONTROL_RDREQI_NOT_SET_VALUE 0 683 #define SI32_UART_B_CONTROL_RDREQI_NOT_SET_U32 \ 684 (SI32_UART_B_CONTROL_RDREQI_NOT_SET_VALUE << SI32_UART_B_CONTROL_RDREQI_SHIFT) 685 // At least RFTH FIFO entries are filled with data. 686 #define SI32_UART_B_CONTROL_RDREQI_SET_VALUE 1 687 #define SI32_UART_B_CONTROL_RDREQI_SET_U32 \ 688 (SI32_UART_B_CONTROL_RDREQI_SET_VALUE << SI32_UART_B_CONTROL_RDREQI_SHIFT) 689 690 #define SI32_UART_B_CONTROL_RERIEN_MASK 0x00000020 691 #define SI32_UART_B_CONTROL_RERIEN_SHIFT 5 692 // Disable the receive error interrupt. 693 #define SI32_UART_B_CONTROL_RERIEN_DISABLED_VALUE 0 694 #define SI32_UART_B_CONTROL_RERIEN_DISABLED_U32 \ 695 (SI32_UART_B_CONTROL_RERIEN_DISABLED_VALUE << SI32_UART_B_CONTROL_RERIEN_SHIFT) 696 // Enable the receive error interrupt. A receive interrupt is asserted when ROREI, 697 // RFRMERI, or RPARERI is set to 1. 698 #define SI32_UART_B_CONTROL_RERIEN_ENABLED_VALUE 1 699 #define SI32_UART_B_CONTROL_RERIEN_ENABLED_U32 \ 700 (SI32_UART_B_CONTROL_RERIEN_ENABLED_VALUE << SI32_UART_B_CONTROL_RERIEN_SHIFT) 701 702 #define SI32_UART_B_CONTROL_RDREQIEN_MASK 0x00000040 703 #define SI32_UART_B_CONTROL_RDREQIEN_SHIFT 6 704 // Disable the read data request interrupt. 705 #define SI32_UART_B_CONTROL_RDREQIEN_DISABLED_VALUE 0 706 #define SI32_UART_B_CONTROL_RDREQIEN_DISABLED_U32 \ 707 (SI32_UART_B_CONTROL_RDREQIEN_DISABLED_VALUE << SI32_UART_B_CONTROL_RDREQIEN_SHIFT) 708 // Enable the read data request interrupt. A receive interrupt is generated when 709 // RDREQI is set to 1. 710 #define SI32_UART_B_CONTROL_RDREQIEN_ENABLED_VALUE 1 711 #define SI32_UART_B_CONTROL_RDREQIEN_ENABLED_U32 \ 712 (SI32_UART_B_CONTROL_RDREQIEN_ENABLED_VALUE << SI32_UART_B_CONTROL_RDREQIEN_SHIFT) 713 714 #define SI32_UART_B_CONTROL_MATMD_MASK 0x00000300 715 #define SI32_UART_B_CONTROL_MATMD_SHIFT 8 716 // Disable the match function. 717 #define SI32_UART_B_CONTROL_MATMD_OFF_VALUE 0 718 #define SI32_UART_B_CONTROL_MATMD_OFF_U32 \ 719 (SI32_UART_B_CONTROL_MATMD_OFF_VALUE << SI32_UART_B_CONTROL_MATMD_SHIFT) 720 // (MCE) Data whose last data bit equals RBIT is accepted and stored. 721 #define SI32_UART_B_CONTROL_MATMD_MCE_VALUE 1 722 #define SI32_UART_B_CONTROL_MATMD_MCE_U32 \ 723 (SI32_UART_B_CONTROL_MATMD_MCE_VALUE << SI32_UART_B_CONTROL_MATMD_SHIFT) 724 // (Frame) A framing error is asserted if the last received data bit matches RBIT. 725 #define SI32_UART_B_CONTROL_MATMD_FRAME_VALUE 2 726 #define SI32_UART_B_CONTROL_MATMD_FRAME_U32 \ 727 (SI32_UART_B_CONTROL_MATMD_FRAME_VALUE << SI32_UART_B_CONTROL_MATMD_SHIFT) 728 // (Store) Store the last incoming data bit in RBIT. This mode can be used 729 // inconjunction with the RDATLN setting. 730 #define SI32_UART_B_CONTROL_MATMD_STORE_VALUE 3 731 #define SI32_UART_B_CONTROL_MATMD_STORE_U32 \ 732 (SI32_UART_B_CONTROL_MATMD_STORE_VALUE << SI32_UART_B_CONTROL_MATMD_SHIFT) 733 734 #define SI32_UART_B_CONTROL_RABDEN_MASK 0x00000400 735 #define SI32_UART_B_CONTROL_RABDEN_SHIFT 10 736 // Disable receiver auto-baud. 737 #define SI32_UART_B_CONTROL_RABDEN_DISABLED_VALUE 0 738 #define SI32_UART_B_CONTROL_RABDEN_DISABLED_U32 \ 739 (SI32_UART_B_CONTROL_RABDEN_DISABLED_VALUE << SI32_UART_B_CONTROL_RABDEN_SHIFT) 740 // Enable receiver auto-baud. 741 #define SI32_UART_B_CONTROL_RABDEN_ENABLED_VALUE 1 742 #define SI32_UART_B_CONTROL_RABDEN_ENABLED_U32 \ 743 (SI32_UART_B_CONTROL_RABDEN_ENABLED_VALUE << SI32_UART_B_CONTROL_RABDEN_SHIFT) 744 745 #define SI32_UART_B_CONTROL_RBUSYF_MASK 0x00000800 746 #define SI32_UART_B_CONTROL_RBUSYF_SHIFT 11 747 // The UART receiver is idle. 748 #define SI32_UART_B_CONTROL_RBUSYF_NOT_SET_VALUE 0 749 #define SI32_UART_B_CONTROL_RBUSYF_NOT_SET_U32 \ 750 (SI32_UART_B_CONTROL_RBUSYF_NOT_SET_VALUE << SI32_UART_B_CONTROL_RBUSYF_SHIFT) 751 // The UART receiver is receiving data. 752 #define SI32_UART_B_CONTROL_RBUSYF_SET_VALUE 1 753 #define SI32_UART_B_CONTROL_RBUSYF_SET_U32 \ 754 (SI32_UART_B_CONTROL_RBUSYF_SET_VALUE << SI32_UART_B_CONTROL_RBUSYF_SHIFT) 755 756 #define SI32_UART_B_CONTROL_RBIT_MASK 0x00001000 757 #define SI32_UART_B_CONTROL_RBIT_SHIFT 12 758 #define SI32_UART_B_CONTROL_RBIT_NOT_SET_VALUE 0 759 #define SI32_UART_B_CONTROL_RBIT_NOT_SET_U32 \ 760 (SI32_UART_B_CONTROL_RBIT_NOT_SET_VALUE << SI32_UART_B_CONTROL_RBIT_SHIFT) 761 #define SI32_UART_B_CONTROL_RBIT_SET_VALUE 1 762 #define SI32_UART_B_CONTROL_RBIT_SET_U32 \ 763 (SI32_UART_B_CONTROL_RBIT_SET_VALUE << SI32_UART_B_CONTROL_RBIT_SHIFT) 764 765 #define SI32_UART_B_CONTROL_ROSEN_MASK 0x00002000 766 #define SI32_UART_B_CONTROL_ROSEN_SHIFT 13 767 // Disable one-shot receive mode. 768 #define SI32_UART_B_CONTROL_ROSEN_DISABLED_VALUE 0 769 #define SI32_UART_B_CONTROL_ROSEN_DISABLED_U32 \ 770 (SI32_UART_B_CONTROL_ROSEN_DISABLED_VALUE << SI32_UART_B_CONTROL_ROSEN_SHIFT) 771 // Enable one-shot receive mode. 772 #define SI32_UART_B_CONTROL_ROSEN_ENABLED_VALUE 1 773 #define SI32_UART_B_CONTROL_ROSEN_ENABLED_U32 \ 774 (SI32_UART_B_CONTROL_ROSEN_ENABLED_VALUE << SI32_UART_B_CONTROL_ROSEN_SHIFT) 775 776 #define SI32_UART_B_CONTROL_RINH_MASK 0x00004000 777 #define SI32_UART_B_CONTROL_RINH_SHIFT 14 778 // The receiver operates normally. 779 #define SI32_UART_B_CONTROL_RINH_INACTIVE_VALUE 0 780 #define SI32_UART_B_CONTROL_RINH_INACTIVE_U32 \ 781 (SI32_UART_B_CONTROL_RINH_INACTIVE_VALUE << SI32_UART_B_CONTROL_RINH_SHIFT) 782 // The receiver will complete any ongoing reception, but ignore all traffic after 783 // that. 784 #define SI32_UART_B_CONTROL_RINH_ACTIVE_VALUE 1 785 #define SI32_UART_B_CONTROL_RINH_ACTIVE_U32 \ 786 (SI32_UART_B_CONTROL_RINH_ACTIVE_VALUE << SI32_UART_B_CONTROL_RINH_SHIFT) 787 788 #define SI32_UART_B_CONTROL_REN_MASK 0x00008000 789 #define SI32_UART_B_CONTROL_REN_SHIFT 15 790 // Disable the receiver. The receiver can receive one data transaction only if 791 // ROSEN is set. 792 #define SI32_UART_B_CONTROL_REN_DISABLED_VALUE 0 793 #define SI32_UART_B_CONTROL_REN_DISABLED_U32 \ 794 (SI32_UART_B_CONTROL_REN_DISABLED_VALUE << SI32_UART_B_CONTROL_REN_SHIFT) 795 // Enable the receiver. 796 #define SI32_UART_B_CONTROL_REN_ENABLED_VALUE 1 797 #define SI32_UART_B_CONTROL_REN_ENABLED_U32 \ 798 (SI32_UART_B_CONTROL_REN_ENABLED_VALUE << SI32_UART_B_CONTROL_REN_SHIFT) 799 800 #define SI32_UART_B_CONTROL_TDREQI_MASK 0x00040000 801 #define SI32_UART_B_CONTROL_TDREQI_SHIFT 18 802 // The transmitter is not requesting more FIFO data. 803 #define SI32_UART_B_CONTROL_TDREQI_NOT_SET_VALUE 0 804 #define SI32_UART_B_CONTROL_TDREQI_NOT_SET_U32 \ 805 (SI32_UART_B_CONTROL_TDREQI_NOT_SET_VALUE << SI32_UART_B_CONTROL_TDREQI_SHIFT) 806 // The transmitter is requesting more FIFO data. 807 #define SI32_UART_B_CONTROL_TDREQI_SET_VALUE 1 808 #define SI32_UART_B_CONTROL_TDREQI_SET_U32 \ 809 (SI32_UART_B_CONTROL_TDREQI_SET_VALUE << SI32_UART_B_CONTROL_TDREQI_SHIFT) 810 811 #define SI32_UART_B_CONTROL_TCPTI_MASK 0x00080000 812 #define SI32_UART_B_CONTROL_TCPTI_SHIFT 19 813 // Read: A transmit has not completed since TCPTI was last cleared. Write: Clear 814 // the interrupt. 815 #define SI32_UART_B_CONTROL_TCPTI_NOT_SET_VALUE 0 816 #define SI32_UART_B_CONTROL_TCPTI_NOT_SET_U32 \ 817 (SI32_UART_B_CONTROL_TCPTI_NOT_SET_VALUE << SI32_UART_B_CONTROL_TCPTI_SHIFT) 818 // Read: A byte was transmitted (TCCPTH = 0) or the last available byte was 819 // transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. 820 #define SI32_UART_B_CONTROL_TCPTI_SET_VALUE 1 821 #define SI32_UART_B_CONTROL_TCPTI_SET_U32 \ 822 (SI32_UART_B_CONTROL_TCPTI_SET_VALUE << SI32_UART_B_CONTROL_TCPTI_SHIFT) 823 824 #define SI32_UART_B_CONTROL_TCPTTH_MASK 0x00100000 825 #define SI32_UART_B_CONTROL_TCPTTH_SHIFT 20 826 // The TCPTI flag is set after each data transmission. 827 #define SI32_UART_B_CONTROL_TCPTTH_SET_ON_TX_VALUE 0 828 #define SI32_UART_B_CONTROL_TCPTTH_SET_ON_TX_U32 \ 829 (SI32_UART_B_CONTROL_TCPTTH_SET_ON_TX_VALUE << SI32_UART_B_CONTROL_TCPTTH_SHIFT) 830 // The TCPTI flag is set after transmission of the last available data. 831 #define SI32_UART_B_CONTROL_TCPTTH_SET_ON_EMPTY_VALUE 1 832 #define SI32_UART_B_CONTROL_TCPTTH_SET_ON_EMPTY_U32 \ 833 (SI32_UART_B_CONTROL_TCPTTH_SET_ON_EMPTY_VALUE << SI32_UART_B_CONTROL_TCPTTH_SHIFT) 834 835 #define SI32_UART_B_CONTROL_TDREQIEN_MASK 0x00400000 836 #define SI32_UART_B_CONTROL_TDREQIEN_SHIFT 22 837 // Disable the transmit data request interrupt. 838 #define SI32_UART_B_CONTROL_TDREQIEN_DISABLED_VALUE 0 839 #define SI32_UART_B_CONTROL_TDREQIEN_DISABLED_U32 \ 840 (SI32_UART_B_CONTROL_TDREQIEN_DISABLED_VALUE << SI32_UART_B_CONTROL_TDREQIEN_SHIFT) 841 // Enable the transmit data request interrupt. A transmit interrupt is asserted 842 // when TDREQI is set to 1. 843 #define SI32_UART_B_CONTROL_TDREQIEN_ENABLED_VALUE 1 844 #define SI32_UART_B_CONTROL_TDREQIEN_ENABLED_U32 \ 845 (SI32_UART_B_CONTROL_TDREQIEN_ENABLED_VALUE << SI32_UART_B_CONTROL_TDREQIEN_SHIFT) 846 847 #define SI32_UART_B_CONTROL_TCPTIEN_MASK 0x00800000 848 #define SI32_UART_B_CONTROL_TCPTIEN_SHIFT 23 849 // Disable the transmit complete interrupt. 850 #define SI32_UART_B_CONTROL_TCPTIEN_DISABLED_VALUE 0 851 #define SI32_UART_B_CONTROL_TCPTIEN_DISABLED_U32 \ 852 (SI32_UART_B_CONTROL_TCPTIEN_DISABLED_VALUE << SI32_UART_B_CONTROL_TCPTIEN_SHIFT) 853 // Enable the transmit complete interrupt. A transmit interrupt is generated when 854 // TCPTI is set to 1. 855 #define SI32_UART_B_CONTROL_TCPTIEN_ENABLED_VALUE 1 856 #define SI32_UART_B_CONTROL_TCPTIEN_ENABLED_U32 \ 857 (SI32_UART_B_CONTROL_TCPTIEN_ENABLED_VALUE << SI32_UART_B_CONTROL_TCPTIEN_SHIFT) 858 859 #define SI32_UART_B_CONTROL_TBUSYF_MASK 0x08000000 860 #define SI32_UART_B_CONTROL_TBUSYF_SHIFT 27 861 // The UART transmitter is idle. 862 #define SI32_UART_B_CONTROL_TBUSYF_NOT_SET_VALUE 0 863 #define SI32_UART_B_CONTROL_TBUSYF_NOT_SET_U32 \ 864 (SI32_UART_B_CONTROL_TBUSYF_NOT_SET_VALUE << SI32_UART_B_CONTROL_TBUSYF_SHIFT) 865 // The UART transmitter is active and transmitting. 866 #define SI32_UART_B_CONTROL_TBUSYF_SET_VALUE 1 867 #define SI32_UART_B_CONTROL_TBUSYF_SET_U32 \ 868 (SI32_UART_B_CONTROL_TBUSYF_SET_VALUE << SI32_UART_B_CONTROL_TBUSYF_SHIFT) 869 870 #define SI32_UART_B_CONTROL_TBIT_MASK 0x10000000 871 #define SI32_UART_B_CONTROL_TBIT_SHIFT 28 872 #define SI32_UART_B_CONTROL_TBIT_NOT_SET_VALUE 0 873 #define SI32_UART_B_CONTROL_TBIT_NOT_SET_U32 \ 874 (SI32_UART_B_CONTROL_TBIT_NOT_SET_VALUE << SI32_UART_B_CONTROL_TBIT_SHIFT) 875 #define SI32_UART_B_CONTROL_TBIT_SET_VALUE 1 876 #define SI32_UART_B_CONTROL_TBIT_SET_U32 \ 877 (SI32_UART_B_CONTROL_TBIT_SET_VALUE << SI32_UART_B_CONTROL_TBIT_SHIFT) 878 879 #define SI32_UART_B_CONTROL_TINH_MASK 0x40000000 880 #define SI32_UART_B_CONTROL_TINH_SHIFT 30 881 // The transmitter operates normally. 882 #define SI32_UART_B_CONTROL_TINH_INACTIVE_VALUE 0 883 #define SI32_UART_B_CONTROL_TINH_INACTIVE_U32 \ 884 (SI32_UART_B_CONTROL_TINH_INACTIVE_VALUE << SI32_UART_B_CONTROL_TINH_SHIFT) 885 // Transmissions are inhibited. The transmitter will stall after any current 886 // transmission is complete. 887 #define SI32_UART_B_CONTROL_TINH_ACTIVE_VALUE 1 888 #define SI32_UART_B_CONTROL_TINH_ACTIVE_U32 \ 889 (SI32_UART_B_CONTROL_TINH_ACTIVE_VALUE << SI32_UART_B_CONTROL_TINH_SHIFT) 890 891 #define SI32_UART_B_CONTROL_TEN_MASK 0x80000000 892 #define SI32_UART_B_CONTROL_TEN_SHIFT 31 893 // Disable the transmitter. When cleared, the transmitter immediately aborts any 894 // active transmission. Clearing this bit does not automatically flush the transmit 895 // FIFO. 896 #define SI32_UART_B_CONTROL_TEN_DISABLED_VALUE 0U 897 #define SI32_UART_B_CONTROL_TEN_DISABLED_U32 \ 898 (SI32_UART_B_CONTROL_TEN_DISABLED_VALUE << SI32_UART_B_CONTROL_TEN_SHIFT) 899 // Enable the transmitter. The transmitter will initiate a transmission when data 900 // becomes available in the transmit FIFO. 901 #define SI32_UART_B_CONTROL_TEN_ENABLED_VALUE 1U 902 #define SI32_UART_B_CONTROL_TEN_ENABLED_U32 \ 903 (SI32_UART_B_CONTROL_TEN_ENABLED_VALUE << SI32_UART_B_CONTROL_TEN_SHIFT) 904 905 906 907 struct SI32_UART_B_IPDELAY_Struct 908 { 909 union 910 { 911 struct 912 { 913 uint32_t reserved0: 16; 914 // Inter-Packet Delay 915 volatile uint8_t IPDELAY_BITS; 916 uint32_t reserved1: 8; 917 }; 918 volatile uint32_t U32; 919 }; 920 }; 921 922 #define SI32_UART_B_IPDELAY_IPDELAY_MASK 0x00FF0000 923 #define SI32_UART_B_IPDELAY_IPDELAY_SHIFT 16 924 925 926 927 struct SI32_UART_B_BAUDRATE_Struct 928 { 929 union 930 { 931 struct 932 { 933 // Receiver Baud Rate Control 934 volatile uint16_t RBAUD; 935 // Transmitter Baud Rate Control 936 volatile uint16_t TBAUD; 937 }; 938 volatile uint32_t U32; 939 }; 940 }; 941 942 #define SI32_UART_B_BAUDRATE_RBAUD_MASK 0x0000FFFF 943 #define SI32_UART_B_BAUDRATE_RBAUD_SHIFT 0 944 945 #define SI32_UART_B_BAUDRATE_TBAUD_MASK 0xFFFF0000 946 #define SI32_UART_B_BAUDRATE_TBAUD_SHIFT 16 947 948 949 950 struct SI32_UART_B_FIFOCN_Struct 951 { 952 union 953 { 954 struct 955 { 956 // Receive FIFO Count 957 volatile uint32_t RCNT: 3; 958 uint32_t reserved0: 1; 959 // Receive FIFO Threshold 960 volatile uint32_t RFTH: 2; 961 uint32_t reserved1: 2; 962 // Receive FIFO Flush 963 volatile uint32_t RFIFOFL: 1; 964 // Receive FIFO Error Interrupt Flag 965 volatile uint32_t RFERI: 1; 966 // Receive Shift Register Full Flag 967 volatile uint32_t RSRFULLF: 1; 968 uint32_t reserved2: 5; 969 // Transmit FIFO Count 970 volatile uint32_t TCNT: 3; 971 uint32_t reserved3: 1; 972 // Transmit FIFO Threshold 973 volatile uint32_t TFTH: 2; 974 uint32_t reserved4: 2; 975 // Transmit FIFO Flush 976 volatile uint32_t TFIFOFL: 1; 977 // Transmit FIFO Error Interrupt Flag 978 volatile uint32_t TFERI: 1; 979 // Transmit Shift Register Full Flag 980 volatile uint32_t TSRFULLF: 1; 981 uint32_t reserved5: 5; 982 }; 983 volatile uint32_t U32; 984 }; 985 }; 986 987 #define SI32_UART_B_FIFOCN_RCNT_MASK 0x00000007 988 #define SI32_UART_B_FIFOCN_RCNT_SHIFT 0 989 990 #define SI32_UART_B_FIFOCN_RFTH_MASK 0x00000030 991 #define SI32_UART_B_FIFOCN_RFTH_SHIFT 4 992 // A read data request interrupt (RDREQI) is asserted when >= 1 FIFO entry is full. 993 #define SI32_UART_B_FIFOCN_RFTH_ONE_VALUE 0 994 #define SI32_UART_B_FIFOCN_RFTH_ONE_U32 \ 995 (SI32_UART_B_FIFOCN_RFTH_ONE_VALUE << SI32_UART_B_FIFOCN_RFTH_SHIFT) 996 // A read data request interrupt (RDREQI) is asserted when >= 2 FIFO entries are 997 // full. 998 #define SI32_UART_B_FIFOCN_RFTH_TWO_VALUE 1 999 #define SI32_UART_B_FIFOCN_RFTH_TWO_U32 \ 1000 (SI32_UART_B_FIFOCN_RFTH_TWO_VALUE << SI32_UART_B_FIFOCN_RFTH_SHIFT) 1001 // A read data request interrupt (RDREQI) is asserted when >= 3 FIFO entries are 1002 // full. 1003 #define SI32_UART_B_FIFOCN_RFTH_THREE_VALUE 2 1004 #define SI32_UART_B_FIFOCN_RFTH_THREE_U32 \ 1005 (SI32_UART_B_FIFOCN_RFTH_THREE_VALUE << SI32_UART_B_FIFOCN_RFTH_SHIFT) 1006 // A read data request interrupt (RDREQI) is asserted when >= 4 FIFO entries are 1007 // full. 1008 #define SI32_UART_B_FIFOCN_RFTH_FOUR_VALUE 3 1009 #define SI32_UART_B_FIFOCN_RFTH_FOUR_U32 \ 1010 (SI32_UART_B_FIFOCN_RFTH_FOUR_VALUE << SI32_UART_B_FIFOCN_RFTH_SHIFT) 1011 1012 #define SI32_UART_B_FIFOCN_RFIFOFL_MASK 0x00000100 1013 #define SI32_UART_B_FIFOCN_RFIFOFL_SHIFT 8 1014 // Flush the contents of the receive FIFO and any data in the receive shift 1015 // register. 1016 #define SI32_UART_B_FIFOCN_RFIFOFL_SET_VALUE 1 1017 #define SI32_UART_B_FIFOCN_RFIFOFL_SET_U32 \ 1018 (SI32_UART_B_FIFOCN_RFIFOFL_SET_VALUE << SI32_UART_B_FIFOCN_RFIFOFL_SHIFT) 1019 1020 #define SI32_UART_B_FIFOCN_RFERI_MASK 0x00000200 1021 #define SI32_UART_B_FIFOCN_RFERI_SHIFT 9 1022 // A receive FIFO error has not occurred since RFERI was last cleared. 1023 #define SI32_UART_B_FIFOCN_RFERI_NOT_SET_VALUE 0 1024 #define SI32_UART_B_FIFOCN_RFERI_NOT_SET_U32 \ 1025 (SI32_UART_B_FIFOCN_RFERI_NOT_SET_VALUE << SI32_UART_B_FIFOCN_RFERI_SHIFT) 1026 // A receive FIFO error occurred. 1027 #define SI32_UART_B_FIFOCN_RFERI_SET_VALUE 1 1028 #define SI32_UART_B_FIFOCN_RFERI_SET_U32 \ 1029 (SI32_UART_B_FIFOCN_RFERI_SET_VALUE << SI32_UART_B_FIFOCN_RFERI_SHIFT) 1030 1031 #define SI32_UART_B_FIFOCN_RSRFULLF_MASK 0x00000400 1032 #define SI32_UART_B_FIFOCN_RSRFULLF_SHIFT 10 1033 // The receive data shift register is not full. 1034 #define SI32_UART_B_FIFOCN_RSRFULLF_NOT_SET_VALUE 0 1035 #define SI32_UART_B_FIFOCN_RSRFULLF_NOT_SET_U32 \ 1036 (SI32_UART_B_FIFOCN_RSRFULLF_NOT_SET_VALUE << SI32_UART_B_FIFOCN_RSRFULLF_SHIFT) 1037 // The receive data shift register is full. 1038 #define SI32_UART_B_FIFOCN_RSRFULLF_SET_VALUE 1 1039 #define SI32_UART_B_FIFOCN_RSRFULLF_SET_U32 \ 1040 (SI32_UART_B_FIFOCN_RSRFULLF_SET_VALUE << SI32_UART_B_FIFOCN_RSRFULLF_SHIFT) 1041 1042 #define SI32_UART_B_FIFOCN_TCNT_MASK 0x00070000 1043 #define SI32_UART_B_FIFOCN_TCNT_SHIFT 16 1044 1045 #define SI32_UART_B_FIFOCN_TFTH_MASK 0x00300000 1046 #define SI32_UART_B_FIFOCN_TFTH_SHIFT 20 1047 // A transmit data request interrupt (TDREQI) is asserted when >= 1 FIFO entry is 1048 // empty. 1049 #define SI32_UART_B_FIFOCN_TFTH_ONE_VALUE 0 1050 #define SI32_UART_B_FIFOCN_TFTH_ONE_U32 \ 1051 (SI32_UART_B_FIFOCN_TFTH_ONE_VALUE << SI32_UART_B_FIFOCN_TFTH_SHIFT) 1052 // A transmit data request interrupt (TDREQI) is asserted when >= 2 FIFO entries 1053 // are empty. 1054 #define SI32_UART_B_FIFOCN_TFTH_TWO_VALUE 1 1055 #define SI32_UART_B_FIFOCN_TFTH_TWO_U32 \ 1056 (SI32_UART_B_FIFOCN_TFTH_TWO_VALUE << SI32_UART_B_FIFOCN_TFTH_SHIFT) 1057 // A transmit data request interrupt (TDREQI) is asserted when >= 3 FIFO entries 1058 // are empty. 1059 #define SI32_UART_B_FIFOCN_TFTH_THREE_VALUE 2 1060 #define SI32_UART_B_FIFOCN_TFTH_THREE_U32 \ 1061 (SI32_UART_B_FIFOCN_TFTH_THREE_VALUE << SI32_UART_B_FIFOCN_TFTH_SHIFT) 1062 // A transmit data request interrupt (TDREQI) is asserted when >= 4 FIFO entries 1063 // are empty. 1064 #define SI32_UART_B_FIFOCN_TFTH_FOUR_VALUE 3 1065 #define SI32_UART_B_FIFOCN_TFTH_FOUR_U32 \ 1066 (SI32_UART_B_FIFOCN_TFTH_FOUR_VALUE << SI32_UART_B_FIFOCN_TFTH_SHIFT) 1067 1068 #define SI32_UART_B_FIFOCN_TFIFOFL_MASK 0x01000000 1069 #define SI32_UART_B_FIFOCN_TFIFOFL_SHIFT 24 1070 // Flush the contents of the transmit FIFO. If data is pending in the transmit 1071 // shift register but a transmit has not begun, the shift register is also flushed. 1072 #define SI32_UART_B_FIFOCN_TFIFOFL_SET_VALUE 1 1073 #define SI32_UART_B_FIFOCN_TFIFOFL_SET_U32 \ 1074 (SI32_UART_B_FIFOCN_TFIFOFL_SET_VALUE << SI32_UART_B_FIFOCN_TFIFOFL_SHIFT) 1075 1076 #define SI32_UART_B_FIFOCN_TFERI_MASK 0x02000000 1077 #define SI32_UART_B_FIFOCN_TFERI_SHIFT 25 1078 // A transmit FIFO error has not occurred since TFERI was last cleared. 1079 #define SI32_UART_B_FIFOCN_TFERI_NOT_SET_VALUE 0 1080 #define SI32_UART_B_FIFOCN_TFERI_NOT_SET_U32 \ 1081 (SI32_UART_B_FIFOCN_TFERI_NOT_SET_VALUE << SI32_UART_B_FIFOCN_TFERI_SHIFT) 1082 // A transmit FIFO error occurred. 1083 #define SI32_UART_B_FIFOCN_TFERI_SET_VALUE 1 1084 #define SI32_UART_B_FIFOCN_TFERI_SET_U32 \ 1085 (SI32_UART_B_FIFOCN_TFERI_SET_VALUE << SI32_UART_B_FIFOCN_TFERI_SHIFT) 1086 1087 #define SI32_UART_B_FIFOCN_TSRFULLF_MASK 0x04000000 1088 #define SI32_UART_B_FIFOCN_TSRFULLF_SHIFT 26 1089 // The transmit shift register is not full. 1090 #define SI32_UART_B_FIFOCN_TSRFULLF_NOT_SET_VALUE 0 1091 #define SI32_UART_B_FIFOCN_TSRFULLF_NOT_SET_U32 \ 1092 (SI32_UART_B_FIFOCN_TSRFULLF_NOT_SET_VALUE << SI32_UART_B_FIFOCN_TSRFULLF_SHIFT) 1093 // The transmit shift register is full. 1094 #define SI32_UART_B_FIFOCN_TSRFULLF_SET_VALUE 1 1095 #define SI32_UART_B_FIFOCN_TSRFULLF_SET_U32 \ 1096 (SI32_UART_B_FIFOCN_TSRFULLF_SET_VALUE << SI32_UART_B_FIFOCN_TSRFULLF_SHIFT) 1097 1098 1099 1100 struct SI32_UART_B_DATA_Struct 1101 { 1102 union 1103 { 1104 // This is a FIFO register 1105 volatile uint8_t U8; 1106 volatile uint16_t U16; 1107 volatile uint32_t U32; 1108 }; 1109 }; 1110 1111 #define SI32_UART_B_DATA_DATA_MASK 0xFFFFFFFF 1112 #define SI32_UART_B_DATA_DATA_SHIFT 0 1113 1114 1115 1116 struct SI32_UART_B_CLKDIV_Struct 1117 { 1118 union 1119 { 1120 struct 1121 { 1122 // Clock Divider 1123 volatile uint32_t CLKDIV_BITS: 2; 1124 uint32_t reserved0: 30; 1125 }; 1126 volatile uint32_t U32; 1127 }; 1128 }; 1129 1130 #define SI32_UART_B_CLKDIV_CLKDIV_MASK 0x00000003 1131 #define SI32_UART_B_CLKDIV_CLKDIV_SHIFT 0 1132 // Divide by 1. 1133 #define SI32_UART_B_CLKDIV_CLKDIV_DIV1_VALUE 0 1134 #define SI32_UART_B_CLKDIV_CLKDIV_DIV1_U32 \ 1135 (SI32_UART_B_CLKDIV_CLKDIV_DIV1_VALUE << SI32_UART_B_CLKDIV_CLKDIV_SHIFT) 1136 // Divide by 2. 1137 #define SI32_UART_B_CLKDIV_CLKDIV_DIV2_VALUE 1 1138 #define SI32_UART_B_CLKDIV_CLKDIV_DIV2_U32 \ 1139 (SI32_UART_B_CLKDIV_CLKDIV_DIV2_VALUE << SI32_UART_B_CLKDIV_CLKDIV_SHIFT) 1140 // Divide by 4. 1141 #define SI32_UART_B_CLKDIV_CLKDIV_DIV4_VALUE 2 1142 #define SI32_UART_B_CLKDIV_CLKDIV_DIV4_U32 \ 1143 (SI32_UART_B_CLKDIV_CLKDIV_DIV4_VALUE << SI32_UART_B_CLKDIV_CLKDIV_SHIFT) 1144 1145 1146 1147 typedef struct SI32_UART_B_Struct 1148 { 1149 struct SI32_UART_B_CONFIG_Struct CONFIG ; // Base Address + 0x0 1150 volatile uint32_t CONFIG_SET; 1151 volatile uint32_t CONFIG_CLR; 1152 uint32_t reserved0; 1153 struct SI32_UART_B_MODE_Struct MODE ; // Base Address + 0x10 1154 volatile uint32_t MODE_SET; 1155 volatile uint32_t MODE_CLR; 1156 uint32_t reserved1; 1157 struct SI32_UART_B_FLOWCN_Struct FLOWCN ; // Base Address + 0x20 1158 volatile uint32_t FLOWCN_SET; 1159 volatile uint32_t FLOWCN_CLR; 1160 uint32_t reserved2; 1161 struct SI32_UART_B_CONTROL_Struct CONTROL ; // Base Address + 0x30 1162 volatile uint32_t CONTROL_SET; 1163 volatile uint32_t CONTROL_CLR; 1164 uint32_t reserved3; 1165 struct SI32_UART_B_IPDELAY_Struct IPDELAY ; // Base Address + 0x40 1166 uint32_t reserved4; 1167 uint32_t reserved5; 1168 uint32_t reserved6; 1169 struct SI32_UART_B_BAUDRATE_Struct BAUDRATE ; // Base Address + 0x50 1170 uint32_t reserved7; 1171 uint32_t reserved8; 1172 uint32_t reserved9; 1173 struct SI32_UART_B_FIFOCN_Struct FIFOCN ; // Base Address + 0x60 1174 volatile uint32_t FIFOCN_SET; 1175 volatile uint32_t FIFOCN_CLR; 1176 uint32_t reserved10; 1177 struct SI32_UART_B_DATA_Struct DATA ; // Base Address + 0x70 1178 uint32_t reserved11; 1179 uint32_t reserved12; 1180 uint32_t reserved13; 1181 struct SI32_UART_B_CLKDIV_Struct CLKDIV ; // Base Address + 0x80 1182 uint32_t reserved14; 1183 uint32_t reserved15; 1184 uint32_t reserved16; 1185 } SI32_UART_B_Type; 1186 1187 #ifdef __cplusplus 1188 } 1189 #endif 1190 1191 #endif // __SI32_UART_B_REGISTERS_H__ 1192 1193 //-eof-------------------------------------------------------------------------- 1194 1195
