1 2 //------------------------------------------------------------------------------ 3 // Copyright 2012 (c) Silicon Laboratories Inc. 4 // 5 // SPDX-License-Identifier: Zlib 6 // 7 // This siHAL software is provided 'as-is', without any express or implied 8 // warranty. In no event will the authors be held liable for any damages 9 // arising from the use of this software. 10 // 11 // Permission is granted to anyone to use this software for any purpose, 12 // including commercial applications, and to alter it and redistribute it 13 // freely, subject to the following restrictions: 14 // 15 // 1. The origin of this software must not be misrepresented; you must not 16 // claim that you wrote the original software. If you use this software 17 // in a product, an acknowledgment in the product documentation would be 18 // appreciated but is not required. 19 // 2. Altered source versions must be plainly marked as such, and must not be 20 // misrepresented as being the original software. 21 // 3. This notice may not be removed or altered from any source distribution. 22 //------------------------------------------------------------------------------ 23 24 #ifndef __SIM3L1XX_H__ 25 #define __SIM3L1XX_H__ 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #define __MPU_PRESENT 0 32 #define __NVIC_PRIO_BITS 4 33 #define __Vendor_SysTickConfig 0 34 35 typedef enum IRQn 36 { 37 // CPU 38 NonMaskableInt_IRQn = -14, // 2 39 MemoryManagement_IRQn = -12, // 4 40 BusFault_IRQn = -11, // 5 41 UsageFault_IRQn = -10, // 6 42 SVCall_IRQn = -5, // 11 43 DebugMonitor_IRQn = -4, // 12 44 PendSV_IRQn = -2, // 14 45 SysTick_IRQn = -1, // 15 46 // MCU 47 WDTIMER0_IRQn = 0, 48 PBEXT0_IRQn = 1, 49 PBEXT1_IRQn = 2, 50 RTC0ALRM_IRQn = 3, 51 LPTIMER0_IRQn = 4, 52 DMAERR_IRQn = 5, 53 DMACH0_IRQn = 6, 54 DMACH1_IRQn = 7, 55 DMACH2_IRQn = 8, 56 DMACH3_IRQn = 9, 57 DMACH4_IRQn = 10, 58 DMACH5_IRQn = 11, 59 DMACH6_IRQn = 12, 60 DMACH7_IRQn = 13, 61 DMACH8_IRQn = 14, 62 DMACH9_IRQn = 15, 63 TIMER0L_IRQn = 16, 64 TIMER0H_IRQn = 17, 65 TIMER1L_IRQn = 18, 66 TIMER1H_IRQn = 19, 67 TIMER2L_IRQn = 20, 68 TIMER2H_IRQn = 21, 69 ACCTR0_IRQn = 22, 70 EPCA0_IRQn = 23, 71 USART0_IRQn = 24, 72 UART0_IRQn = 25, 73 SPI0_IRQn = 26, 74 SPI1_IRQn = 27, 75 I2C0_IRQn = 28, 76 SARADC0_IRQn = 29, 77 CMP0_IRQn = 30, 78 CMP1_IRQn = 31, 79 DTM0_IRQn = 32, 80 DTM1_IRQn = 33, 81 DTM2_IRQn = 34, 82 AES0_IRQn = 35, 83 ENCDEC0_IRQn = 36, 84 RTC0FAIL_IRQn = 37, 85 VDDLOW_IRQn = 38, 86 CPFAIL_IRQn = 39, 87 DCDC0_IRQn = 40, 88 PMATCH_IRQn = 41, 89 IDAC0_IRQn = 42, 90 PLL0_IRQn = 43, 91 } IRQn_Type; 92 93 //---------------------------------------------------------------------------- 94 // WARNING: DCDC_IRQn IS DEPRECATED AS OF si32-1.1.1. NOT FOR NEW DESIGN. 95 // SUPERCEDED BY DCDC0_IRQn 96 //----------------------------------------------------------------------------- 97 #define DCDC_IRQn DCDC0_IRQn 98 99 100 #include <core_cm3.h> 101 #include <system_sim3l1xx.h> 102 103 //----------------------------------------------------------------------------- 104 105 #include <SI32_ACCTR_A_Registers.h> 106 #include <SI32_AES_B_Registers.h> 107 #include <SI32_CMP_A_Registers.h> 108 #include <SI32_ECRC_A_Registers.h> 109 #include <SI32_DCDC_A_Registers.h> 110 #include <SI32_DMACTRL_A_Registers.h> 111 #include <SI32_DMADESC_A_Registers.h> 112 #include <SI32_DTM_A_Registers.h> 113 #include <SI32_ENCDEC_A_Registers.h> 114 #include <SI32_EPCA_A_Registers.h> 115 #include <SI32_EPCACH_A_Registers.h> 116 #include <SI32_EXTOSC_A_Registers.h> 117 #include <SI32_FLASHCTRL_A_Registers.h> 118 #include <SI32_I2C_A_Registers.h> 119 #include <SI32_IDAC_A_Registers.h> 120 #include <SI32_LCD_A_Registers.h> 121 #include <SI32_LPTIMER_B_Registers.h> 122 #include <SI32_PLL_A_Registers.h> 123 #include <SI32_PVTOSC_A_Registers.h> 124 #include <SI32_RTC_B_Registers.h> 125 #include <SI32_SARADC_A_Registers.h> 126 #include <SI32_SPI_B_Registers.h> 127 #include <SI32_TIMER_A_Registers.h> 128 #include <SI32_UART_B_Registers.h> 129 #include <SI32_USART_B_Registers.h> 130 #include <SI32_VMON_B_Registers.h> 131 #include <SI32_VREF_B_Registers.h> 132 #include <SI32_WDTIMER_A_Registers.h> 133 134 #include <SI32_SIM3L1XX_CLKCTRL_A_Registers.h> 135 #include <SI32_SIM3L1XX_DEVICEID_A_Registers.h> 136 #include <SI32_SIM3L1XX_DMAXBAR_A_Registers.h> 137 #include <SI32_SIM3L1XX_LDO_A_Registers.h> 138 #include <SI32_SIM3L1XX_LOCK_A_Registers.h> 139 #include <SI32_SIM3L1XX_PBCFG_A_Registers.h> 140 #include <SI32_SIM3L1XX_PBSTD_A_Registers.h> 141 #include <SI32_SIM3L1XX_PBGP_A_Registers.h> 142 #include <SI32_SIM3L1XX_PMU_A_Registers.h> 143 #include <SI32_SIM3L1XX_RSTSRC_A_Registers.h> 144 #include <SI32_SIM3L1XX_SCONFIG_A_Registers.h> 145 146 //----------------------------------------------------------------------------- 147 // Define constants for the chip's memory regions. 148 #define SI32_MCU_FLASH_BASE 0x00000000 149 #define SI32_MCU_RAM_BASE 0x20000000 150 151 #if defined(SI32_MCU_SIM3L16X) 152 # define SI32_MCU_FLASH_SIZE 0x0003FFFC 153 # define SI32_MCU_RAM_SIZE 0x00008000 154 #elif defined(SI32_MCU_SIM3L15X) 155 # define SI32_MCU_FLASH_SIZE 0x00020000 156 # define SI32_MCU_RAM_SIZE 0x00004000 157 #elif defined(SI32_MCU_SIM3L14X) 158 # define SI32_MCU_FLASH_SIZE 0x00010000 159 # define SI32_MCU_RAM_SIZE 0x00002000 160 #else //defined(SI32_MCU_SIM3L13X) 161 # define SI32_MCU_FLASH_SIZE 0x00008000 162 # define SI32_MCU_RAM_SIZE 0x00002000 163 #endif 164 165 #define SI32_MCU_RETENTION_RAM_BASE SI32_MCU_RAM_BASE 166 #define SI32_MCU_RETENTION_RAM_SIZE SI32_MCU_RAM_SIZE 167 168 //------------------------------------------------------------------------------ 169 // ARM RealView 170 #if defined (__CC_ARM) 171 172 #define __SI32_RETENTION_REGION __attribute__ ((section(".SI32.RETENTION"), zero_init)) 173 174 //------------------------------------------------------------------------------ 175 // IAR 176 #elif defined (__ICCARM__) 177 178 #define __SI32_RETENTION_REGION _Pragma("location=\".SI32.RETENTION\"") 179 180 //------------------------------------------------------------------------------ 181 // GCC 182 #elif defined (__GNUC__) 183 184 #define __SI32_RETENTION_REGION __attribute__ ((section(".bss.$RESERVED"))) 185 186 #endif 187 188 //----------------------------------------------------------------------------- 189 // Define the instances of the peripherals 190 191 // USART 192 #define SI32_USART_0 ((SI32_USART_B_Type*)0x40000000) 193 // UART 194 #define SI32_UART_0 ((SI32_UART_B_Type*)0x40001000) 195 196 // SPI 197 #define SI32_SPI_0 ((SI32_SPI_B_Type*)0x40004000) 198 #define SI32_SPI_1 ((SI32_SPI_B_Type*)0x40005000) 199 200 // I2C 201 #define SI32_I2C_0 ((SI32_I2C_A_Type*)0x40009000) 202 203 // PCAE 204 #define SI32_EPCA_0 ((SI32_EPCA_A_Type*) 0x4000E180) 205 #define SI32_EPCA_0_CH0 ((SI32_EPCACH_A_Type*)0x4000E000) 206 #define SI32_EPCA_0_CH1 ((SI32_EPCACH_A_Type*)0x4000E040) 207 #define SI32_EPCA_0_CH2 ((SI32_EPCACH_A_Type*)0x4000E080) 208 #define SI32_EPCA_0_CH3 ((SI32_EPCACH_A_Type*)0x4000E0C0) 209 #define SI32_EPCA_0_CH4 ((SI32_EPCACH_A_Type*)0x4000E100) 210 #define SI32_EPCA_0_CH5 ((SI32_EPCACH_A_Type*)0x4000E140) 211 212 // Timers 213 #define SI32_TIMER_0 ((SI32_TIMER_A_Type*)0x40014000) 214 #define SI32_TIMER_1 ((SI32_TIMER_A_Type*)0x40015000) 215 #define SI32_TIMER_2 ((SI32_TIMER_A_Type*)0x40016000) 216 217 // ADCs 218 #define SI32_SARADC_0 ((SI32_SARADC_A_Type*)0x4001A000) 219 220 // Comparator 221 #define SI32_CMP_0 ((SI32_CMP_A_Type*)0x4001F000) 222 #define SI32_CMP_1 ((SI32_CMP_A_Type*)0x40020000) 223 224 // AES 225 #define SI32_AES_0 ((SI32_AES_B_Type*)0x40027000) 226 227 // ECRC 228 #define SI32_ECRC_0 ((SI32_ECRC_A_Type*)0x40028000) 229 230 // RTC and LFO 231 #define SI32_RTC_0 ((SI32_RTC_B_Type*)0x40029000) 232 233 // Port I/O 234 #define SI32_PBCFG_0 ((SI32_PBCFG_A_Type*)0x4002A000) 235 #define SI32_PBSTD_0 ((SI32_PBSTD_A_Type*)0x4002A0A0) 236 #define SI32_PBSTD_1 ((SI32_PBSTD_A_Type*)0x4002A140) 237 #define SI32_PBSTD_2 ((SI32_PBSTD_A_Type*)0x4002A1E0) 238 #define SI32_PBSTD_3 ((SI32_PBSTD_A_Type*)0x4002A280) 239 #define SI32_PBGP_4 ((SI32_PBGP_A_Type*)0x4002A320) 240 241 // Reset Sources 242 #define SI32_RSTSRC_0 ((SI32_RSTSRC_A_Type*)0x4002C000) 243 244 // Clock Control 245 #define SI32_CLKCTRL_0 ((SI32_CLKCTRL_A_Type*)0x4002D000) 246 247 // Flash Interface 248 #define SI32_FLASHCTRL_0 ((SI32_FLASHCTRL_A_Type*)0x4002E000) 249 250 // VDD Monitor 251 #define SI32_VMON_0 ((SI32_VMON_B_Type*)0x4002F000) 252 253 // Watchdog Timer 254 #define SI32_WDTIMER_0 ((SI32_WDTIMER_A_Type*)0x40030000) 255 256 // DACs 257 #define SI32_IDAC_0 ((SI32_IDAC_A_Type*)0x40031000) 258 259 // DMA Controller 260 #define SI32_DMACTRL_0 ((SI32_DMACTRL_A_Type*)0x40036000) 261 262 // DMA Crossbar 263 #define SI32_DMAXBAR_0 ((SI32_DMAXBAR_A_Type*)0x40037000) 264 265 // Low Power Timer 266 #define SI32_LPTIMER_0 ((SI32_LPTIMER_B_Type*)0x40038000) 267 268 // LDO 269 #define SI32_LDO_0 ((SI32_LDO_A_Type*)0x40039000) 270 271 // VREF 272 #define SI32_VREF_0 ((SI32_VREF_B_Type*)0x40039010) 273 274 // Sleep Control 275 #define SI32_SLEEPCTRL_0 ((SI32_SLEEPCTRL_A_Type*)0x4003A000) 276 277 // PLL 278 #define SI32_PLL_0 ((SI32_PLL_A_Type*)0x4003B000) 279 280 // Advanced Capture Counter 281 #define SI32_ACCTR_0 ((SI32_ACCTR_A_Type*)0x40042000) 282 283 // Oscillators 284 #define SI32_EXTOSC_0 ((SI32_EXTOSC_A_Type*)0x4003C000) 285 #define SI32_LPOSC_0 ((SI32_LPOSC_A_Type*) 0x40041000) 286 #define SI32_PVTOSC_0 ((SI32_PVTOSC_A_Type*)0x4003D000) 287 288 // PMU 289 #define SI32_PMU_0 ((SI32_PMU_A_Type*)0x40048000) 290 291 // Lock 292 #define SI32_LOCK_0 ((SI32_LOCK_A_Type*)0x40049000) 293 294 // System Configuration 295 #define SI32_SCONFIG_0 ((SI32_SCONFIG_A_Type*)0x400490B0) 296 297 // Device ID 298 #define SI32_DEVICEID_0 ((SI32_DEVICEID_A_Type*)0x400490C0) 299 300 // Data Transfer Manager 301 #define SI32_DTM_0 ((SI32_DTM_A_Type*)0x4004A000) 302 #define SI32_DTM_1 ((SI32_DTM_A_Type*)0x4004B000) 303 #define SI32_DTM_2 ((SI32_DTM_A_Type*)0x4004C000) 304 305 // LCD 306 #define SI32_LCD_0 ((SI32_LCD_A_Type*)0x4004D000) 307 308 // DC DC Converter 309 #define SI32_DCDC_0 ((SI32_DCDC_A_Type*)0x4004E000) 310 311 // Encoder Decoder 312 #define SI32_ENCDEC_0 ((SI32_ENCDEC_A_Type*)0x4004F000) 313 314 //----------------------------------------------------------------------------- 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif // __SIM3L1XX_H__ 321 322 //-eof------------------------------------------------------------------------- 323
