1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_SSG_A_REGISTERS_H__ 27 #define __SI32_SSG_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_SSG_A_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Pulse Generator Counter 42 volatile uint32_t COUNT: 12; 43 // Speed Select 44 volatile uint32_t SSEL: 1; 45 // Phase Generator Free-Run Enable 46 volatile uint32_t PHGFREN: 1; 47 // Pulse Generator Free-Run Enable 48 volatile uint32_t PUGFREN: 1; 49 uint32_t reserved0: 17; 50 }; 51 volatile uint32_t U32; 52 }; 53 }; 54 55 #define SI32_SSG_A_CONFIG_COUNT_MASK 0x00000FFF 56 #define SI32_SSG_A_CONFIG_COUNT_SHIFT 0 57 58 #define SI32_SSG_A_CONFIG_SSEL_MASK 0x00001000 59 #define SI32_SSG_A_CONFIG_SSEL_SHIFT 12 60 // The SSG module runs at normal speed, where each pulse and phase cycle consists 61 // of 16 ADC clocks. 62 #define SI32_SSG_A_CONFIG_SSEL_NORMAL_VALUE 0 63 #define SI32_SSG_A_CONFIG_SSEL_NORMAL_U32 \ 64 (SI32_SSG_A_CONFIG_SSEL_NORMAL_VALUE << SI32_SSG_A_CONFIG_SSEL_SHIFT) 65 // The SSG module runs at double speed, where each pulse and phase cycle consists 66 // of 8 ADC clocks. 67 #define SI32_SSG_A_CONFIG_SSEL_DOUBLE_VALUE 1 68 #define SI32_SSG_A_CONFIG_SSEL_DOUBLE_U32 \ 69 (SI32_SSG_A_CONFIG_SSEL_DOUBLE_VALUE << SI32_SSG_A_CONFIG_SSEL_SHIFT) 70 71 #define SI32_SSG_A_CONFIG_PHGFREN_MASK 0x00002000 72 #define SI32_SSG_A_CONFIG_PHGFREN_SHIFT 13 73 // The Phase Generator runs only when pulse generation occurs. 74 #define SI32_SSG_A_CONFIG_PHGFREN_DISABLED_VALUE 0 75 #define SI32_SSG_A_CONFIG_PHGFREN_DISABLED_U32 \ 76 (SI32_SSG_A_CONFIG_PHGFREN_DISABLED_VALUE << SI32_SSG_A_CONFIG_PHGFREN_SHIFT) 77 // The Phase Generator runs when an ADC is enabled, regardless of the Pulse 78 // Generator settings. 79 #define SI32_SSG_A_CONFIG_PHGFREN_ENABLED_VALUE 1 80 #define SI32_SSG_A_CONFIG_PHGFREN_ENABLED_U32 \ 81 (SI32_SSG_A_CONFIG_PHGFREN_ENABLED_VALUE << SI32_SSG_A_CONFIG_PHGFREN_SHIFT) 82 83 #define SI32_SSG_A_CONFIG_PUGFREN_MASK 0x00004000 84 #define SI32_SSG_A_CONFIG_PUGFREN_SHIFT 14 85 // The COUNT field determines the number of pulses generated by the Pulse 86 // Generator. 87 #define SI32_SSG_A_CONFIG_PUGFREN_DISABLED_VALUE 0 88 #define SI32_SSG_A_CONFIG_PUGFREN_DISABLED_U32 \ 89 (SI32_SSG_A_CONFIG_PUGFREN_DISABLED_VALUE << SI32_SSG_A_CONFIG_PUGFREN_SHIFT) 90 // The Pulse Generator always generates pulses regardless of COUNT unless all 91 // outputs are disabled (EX0EN, EX1EN, EX2EN, and EX3EN are all 0). 92 #define SI32_SSG_A_CONFIG_PUGFREN_ENABLED_VALUE 1 93 #define SI32_SSG_A_CONFIG_PUGFREN_ENABLED_U32 \ 94 (SI32_SSG_A_CONFIG_PUGFREN_ENABLED_VALUE << SI32_SSG_A_CONFIG_PUGFREN_SHIFT) 95 96 97 98 struct SI32_SSG_A_CONTROL_Struct 99 { 100 union 101 { 102 struct 103 { 104 // Output 0 Invert Enable 105 volatile uint32_t EX0INVEN: 1; 106 // Output 1 Invert Enable 107 volatile uint32_t EX1INVEN: 1; 108 // Output 2 Invert Enable 109 volatile uint32_t EX2INVEN: 1; 110 // Output 3 Invert Enable 111 volatile uint32_t EX3INVEN: 1; 112 // Output 0 Enable 113 volatile uint32_t EX0EN: 1; 114 // Output 1 Enable 115 volatile uint32_t EX1EN: 1; 116 // Output 2 Enable 117 volatile uint32_t EX2EN: 1; 118 // Output 3 Enable 119 volatile uint32_t EX3EN: 1; 120 // SSG Module Status 121 volatile uint32_t STATUS: 1; 122 uint32_t reserved0: 23; 123 }; 124 volatile uint32_t U32; 125 }; 126 }; 127 128 #define SI32_SSG_A_CONTROL_EX0INVEN_MASK 0x00000001 129 #define SI32_SSG_A_CONTROL_EX0INVEN_SHIFT 0 130 // Do not invert the Pulse Generator output on EX0. 131 #define SI32_SSG_A_CONTROL_EX0INVEN_NORMAL_VALUE 0 132 #define SI32_SSG_A_CONTROL_EX0INVEN_NORMAL_U32 \ 133 (SI32_SSG_A_CONTROL_EX0INVEN_NORMAL_VALUE << SI32_SSG_A_CONTROL_EX0INVEN_SHIFT) 134 // Invert the Pulse Generator output on EX0. 135 #define SI32_SSG_A_CONTROL_EX0INVEN_INVERT_VALUE 1 136 #define SI32_SSG_A_CONTROL_EX0INVEN_INVERT_U32 \ 137 (SI32_SSG_A_CONTROL_EX0INVEN_INVERT_VALUE << SI32_SSG_A_CONTROL_EX0INVEN_SHIFT) 138 139 #define SI32_SSG_A_CONTROL_EX1INVEN_MASK 0x00000002 140 #define SI32_SSG_A_CONTROL_EX1INVEN_SHIFT 1 141 // Do not invert the Pulse Generator output on EX1. 142 #define SI32_SSG_A_CONTROL_EX1INVEN_NORMAL_VALUE 0 143 #define SI32_SSG_A_CONTROL_EX1INVEN_NORMAL_U32 \ 144 (SI32_SSG_A_CONTROL_EX1INVEN_NORMAL_VALUE << SI32_SSG_A_CONTROL_EX1INVEN_SHIFT) 145 // Invert the Pulse Generator output on EX1. 146 #define SI32_SSG_A_CONTROL_EX1INVEN_INVERT_VALUE 1 147 #define SI32_SSG_A_CONTROL_EX1INVEN_INVERT_U32 \ 148 (SI32_SSG_A_CONTROL_EX1INVEN_INVERT_VALUE << SI32_SSG_A_CONTROL_EX1INVEN_SHIFT) 149 150 #define SI32_SSG_A_CONTROL_EX2INVEN_MASK 0x00000004 151 #define SI32_SSG_A_CONTROL_EX2INVEN_SHIFT 2 152 // Do not invert the Pulse Generator output on EX2. 153 #define SI32_SSG_A_CONTROL_EX2INVEN_NORMAL_VALUE 0 154 #define SI32_SSG_A_CONTROL_EX2INVEN_NORMAL_U32 \ 155 (SI32_SSG_A_CONTROL_EX2INVEN_NORMAL_VALUE << SI32_SSG_A_CONTROL_EX2INVEN_SHIFT) 156 // Invert the Pulse Generator output on EX2. 157 #define SI32_SSG_A_CONTROL_EX2INVEN_INVERT_VALUE 1 158 #define SI32_SSG_A_CONTROL_EX2INVEN_INVERT_U32 \ 159 (SI32_SSG_A_CONTROL_EX2INVEN_INVERT_VALUE << SI32_SSG_A_CONTROL_EX2INVEN_SHIFT) 160 161 #define SI32_SSG_A_CONTROL_EX3INVEN_MASK 0x00000008 162 #define SI32_SSG_A_CONTROL_EX3INVEN_SHIFT 3 163 // Do not invert the Pulse Generator output on EX3. 164 #define SI32_SSG_A_CONTROL_EX3INVEN_NORMAL_VALUE 0 165 #define SI32_SSG_A_CONTROL_EX3INVEN_NORMAL_U32 \ 166 (SI32_SSG_A_CONTROL_EX3INVEN_NORMAL_VALUE << SI32_SSG_A_CONTROL_EX3INVEN_SHIFT) 167 // Invert the Pulse Generator output on EX3. 168 #define SI32_SSG_A_CONTROL_EX3INVEN_INVERT_VALUE 1 169 #define SI32_SSG_A_CONTROL_EX3INVEN_INVERT_U32 \ 170 (SI32_SSG_A_CONTROL_EX3INVEN_INVERT_VALUE << SI32_SSG_A_CONTROL_EX3INVEN_SHIFT) 171 172 #define SI32_SSG_A_CONTROL_EX0EN_MASK 0x00000010 173 #define SI32_SSG_A_CONTROL_EX0EN_SHIFT 4 174 // Disable the EX0 Pulse Generator output. 175 #define SI32_SSG_A_CONTROL_EX0EN_DISABLED_VALUE 0 176 #define SI32_SSG_A_CONTROL_EX0EN_DISABLED_U32 \ 177 (SI32_SSG_A_CONTROL_EX0EN_DISABLED_VALUE << SI32_SSG_A_CONTROL_EX0EN_SHIFT) 178 // Enable the EX0 Pulse Generator output. 179 #define SI32_SSG_A_CONTROL_EX0EN_ENABLED_VALUE 1 180 #define SI32_SSG_A_CONTROL_EX0EN_ENABLED_U32 \ 181 (SI32_SSG_A_CONTROL_EX0EN_ENABLED_VALUE << SI32_SSG_A_CONTROL_EX0EN_SHIFT) 182 183 #define SI32_SSG_A_CONTROL_EX1EN_MASK 0x00000020 184 #define SI32_SSG_A_CONTROL_EX1EN_SHIFT 5 185 // Disable the EX1 Pulse Generator output. 186 #define SI32_SSG_A_CONTROL_EX1EN_DISABLED_VALUE 0 187 #define SI32_SSG_A_CONTROL_EX1EN_DISABLED_U32 \ 188 (SI32_SSG_A_CONTROL_EX1EN_DISABLED_VALUE << SI32_SSG_A_CONTROL_EX1EN_SHIFT) 189 // Enable the EX1 Pulse Generator output. 190 #define SI32_SSG_A_CONTROL_EX1EN_ENABLED_VALUE 1 191 #define SI32_SSG_A_CONTROL_EX1EN_ENABLED_U32 \ 192 (SI32_SSG_A_CONTROL_EX1EN_ENABLED_VALUE << SI32_SSG_A_CONTROL_EX1EN_SHIFT) 193 194 #define SI32_SSG_A_CONTROL_EX2EN_MASK 0x00000040 195 #define SI32_SSG_A_CONTROL_EX2EN_SHIFT 6 196 // Disable the EX2 Pulse Generator output. 197 #define SI32_SSG_A_CONTROL_EX2EN_DISABLED_VALUE 0 198 #define SI32_SSG_A_CONTROL_EX2EN_DISABLED_U32 \ 199 (SI32_SSG_A_CONTROL_EX2EN_DISABLED_VALUE << SI32_SSG_A_CONTROL_EX2EN_SHIFT) 200 // Enable the EX2 Pulse Generator output. 201 #define SI32_SSG_A_CONTROL_EX2EN_ENABLED_VALUE 1 202 #define SI32_SSG_A_CONTROL_EX2EN_ENABLED_U32 \ 203 (SI32_SSG_A_CONTROL_EX2EN_ENABLED_VALUE << SI32_SSG_A_CONTROL_EX2EN_SHIFT) 204 205 #define SI32_SSG_A_CONTROL_EX3EN_MASK 0x00000080 206 #define SI32_SSG_A_CONTROL_EX3EN_SHIFT 7 207 // Disable the EX3 Pulse Generator output. 208 #define SI32_SSG_A_CONTROL_EX3EN_DISABLED_VALUE 0 209 #define SI32_SSG_A_CONTROL_EX3EN_DISABLED_U32 \ 210 (SI32_SSG_A_CONTROL_EX3EN_DISABLED_VALUE << SI32_SSG_A_CONTROL_EX3EN_SHIFT) 211 // Enable the EX3 Pulse Generator output. 212 #define SI32_SSG_A_CONTROL_EX3EN_ENABLED_VALUE 1 213 #define SI32_SSG_A_CONTROL_EX3EN_ENABLED_U32 \ 214 (SI32_SSG_A_CONTROL_EX3EN_ENABLED_VALUE << SI32_SSG_A_CONTROL_EX3EN_SHIFT) 215 216 #define SI32_SSG_A_CONTROL_STATUS_MASK 0x00000100 217 #define SI32_SSG_A_CONTROL_STATUS_SHIFT 8 218 // The SSG module is idle and the Pulse Generator is not operating. 219 #define SI32_SSG_A_CONTROL_STATUS_IDLE_VALUE 0 220 #define SI32_SSG_A_CONTROL_STATUS_IDLE_U32 \ 221 (SI32_SSG_A_CONTROL_STATUS_IDLE_VALUE << SI32_SSG_A_CONTROL_STATUS_SHIFT) 222 // The SSG module is active and the Pulse Generator is counting. 223 #define SI32_SSG_A_CONTROL_STATUS_ACTIVE_VALUE 1 224 #define SI32_SSG_A_CONTROL_STATUS_ACTIVE_U32 \ 225 (SI32_SSG_A_CONTROL_STATUS_ACTIVE_VALUE << SI32_SSG_A_CONTROL_STATUS_SHIFT) 226 227 228 229 typedef struct SI32_SSG_A_Struct 230 { 231 struct SI32_SSG_A_CONFIG_Struct CONFIG ; // Base Address + 0x0 232 uint32_t reserved0; 233 uint32_t reserved1; 234 uint32_t reserved2; 235 struct SI32_SSG_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 236 volatile uint32_t CONTROL_SET; 237 volatile uint32_t CONTROL_CLR; 238 uint32_t reserved3; 239 } SI32_SSG_A_Type; 240 241 #ifdef __cplusplus 242 } 243 #endif 244 245 #endif // __SI32_SSG_A_REGISTERS_H__ 246 247 //-eof-------------------------------------------------------------------------- 248 249
