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Searched refs:SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE (Results 1 – 3 of 3) sorted by relevance

/hal_silabs-latest/si32/si32Hal/sim3c1xx/
DSI32_SIM3C1XX_RSTSRC_A_Registers.h93 #define SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE 0 macro
95 (SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE << SI32_RSTSRC_A_RESETEN_WDTREN_SHIFT)
/hal_silabs-latest/si32/si32Hal/sim3u1xx/
DSI32_SIM3U1XX_RSTSRC_A_Registers.h94 #define SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE 0 macro
96 (SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE << SI32_RSTSRC_A_RESETEN_WDTREN_SHIFT)
/hal_silabs-latest/si32/si32Hal/sim3l1xx/
DSI32_SIM3L1XX_RSTSRC_A_Registers.h102 #define SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE 0 macro
104 (SI32_RSTSRC_A_RESETEN_WDTREN_DISABLED_VALUE << SI32_RSTSRC_A_RESETEN_WDTREN_SHIFT)