1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_PCACH_A_REGISTERS_H__ 27 #define __SI32_PCACH_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_PCACH_A_MODE_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Channel Output Function Select 42 volatile uint32_t COSEL: 2; 43 // PWM N-Bit Mode 44 volatile uint32_t PWMMD: 4; 45 uint32_t reserved0: 2; 46 // Channel Operating Mode 47 volatile uint32_t CMD: 3; 48 uint32_t reserved1: 21; 49 }; 50 volatile uint32_t U32; 51 }; 52 }; 53 54 #define SI32_PCACH_A_MODE_COSEL_MASK 0x00000003 55 #define SI32_PCACH_A_MODE_COSEL_SHIFT 0 56 // Toggle the channel output at the next capture/compare, overflow, or intermediate 57 // event. 58 #define SI32_PCACH_A_MODE_COSEL_TOGGLE_OUTPUT_VALUE 0 59 #define SI32_PCACH_A_MODE_COSEL_TOGGLE_OUTPUT_U32 \ 60 (SI32_PCACH_A_MODE_COSEL_TOGGLE_OUTPUT_VALUE << SI32_PCACH_A_MODE_COSEL_SHIFT) 61 // Set the channel output at the next capture/compare, overflow, or intermediate 62 // event. 63 #define SI32_PCACH_A_MODE_COSEL_SET_OUTPUT_VALUE 1 64 #define SI32_PCACH_A_MODE_COSEL_SET_OUTPUT_U32 \ 65 (SI32_PCACH_A_MODE_COSEL_SET_OUTPUT_VALUE << SI32_PCACH_A_MODE_COSEL_SHIFT) 66 // Clear the output at the next capture/compare, overflow, or intermediate event. 67 #define SI32_PCACH_A_MODE_COSEL_CLEAR_OUTPUT_VALUE 2 68 #define SI32_PCACH_A_MODE_COSEL_CLEAR_OUTPUT_U32 \ 69 (SI32_PCACH_A_MODE_COSEL_CLEAR_OUTPUT_VALUE << SI32_PCACH_A_MODE_COSEL_SHIFT) 70 // Capture/Compare, overflow, or intermediate events do not control the output 71 // state. 72 #define SI32_PCACH_A_MODE_COSEL_NO_CHANGE_VALUE 3 73 #define SI32_PCACH_A_MODE_COSEL_NO_CHANGE_U32 \ 74 (SI32_PCACH_A_MODE_COSEL_NO_CHANGE_VALUE << SI32_PCACH_A_MODE_COSEL_SHIFT) 75 76 #define SI32_PCACH_A_MODE_PWMMD_MASK 0x0000003C 77 #define SI32_PCACH_A_MODE_PWMMD_SHIFT 2 78 79 #define SI32_PCACH_A_MODE_CMD_MASK 0x00000700 80 #define SI32_PCACH_A_MODE_CMD_SHIFT 8 81 // Configure the channel for edge-aligned PWM mode. 82 #define SI32_PCACH_A_MODE_CMD_EDGE_PWM_VALUE 0 83 #define SI32_PCACH_A_MODE_CMD_EDGE_PWM_U32 \ 84 (SI32_PCACH_A_MODE_CMD_EDGE_PWM_VALUE << SI32_PCACH_A_MODE_CMD_SHIFT) 85 // Configure the channel for center-aligned PWM mode. 86 #define SI32_PCACH_A_MODE_CMD_CENTER_ALIGNED_PWM_VALUE 1 87 #define SI32_PCACH_A_MODE_CMD_CENTER_ALIGNED_PWM_U32 \ 88 (SI32_PCACH_A_MODE_CMD_CENTER_ALIGNED_PWM_VALUE << SI32_PCACH_A_MODE_CMD_SHIFT) 89 // Configure the channel for high-frequency/square-wave mode. 90 #define SI32_PCACH_A_MODE_CMD_HF_SQUARE_WAVE_VALUE 2 91 #define SI32_PCACH_A_MODE_CMD_HF_SQUARE_WAVE_U32 \ 92 (SI32_PCACH_A_MODE_CMD_HF_SQUARE_WAVE_VALUE << SI32_PCACH_A_MODE_CMD_SHIFT) 93 // Configure the channel for timer/capture mode. 94 #define SI32_PCACH_A_MODE_CMD_TIMER_CAPTURE_VALUE 3 95 #define SI32_PCACH_A_MODE_CMD_TIMER_CAPTURE_U32 \ 96 (SI32_PCACH_A_MODE_CMD_TIMER_CAPTURE_VALUE << SI32_PCACH_A_MODE_CMD_SHIFT) 97 // Configure the channel for n-bit edge-aligned PWM mode. 98 #define SI32_PCACH_A_MODE_CMD_N_BIT_PWM_VALUE 4 99 #define SI32_PCACH_A_MODE_CMD_N_BIT_PWM_U32 \ 100 (SI32_PCACH_A_MODE_CMD_N_BIT_PWM_VALUE << SI32_PCACH_A_MODE_CMD_SHIFT) 101 102 103 104 struct SI32_PCACH_A_CONTROL_Struct 105 { 106 union 107 { 108 struct 109 { 110 // Channel Output State 111 volatile uint32_t COUTST: 1; 112 // Positive Edge Input Capture Enable 113 volatile uint32_t CPCAPEN: 1; 114 // Negative Edge Input Capture Enable 115 volatile uint32_t CNCAPEN: 1; 116 // Channel Register Update Complete Flag 117 volatile uint32_t CUPDCF: 1; 118 uint32_t reserved0: 4; 119 // Capture/Compare Interrupt Enable 120 volatile uint32_t CCIEN: 1; 121 uint32_t reserved1: 2; 122 // Intermediate Overflow Interrupt Enable 123 volatile uint32_t CIOVFIEN: 1; 124 uint32_t reserved2: 20; 125 }; 126 volatile uint32_t U32; 127 }; 128 }; 129 130 #define SI32_PCACH_A_CONTROL_COUTST_MASK 0x00000001 131 #define SI32_PCACH_A_CONTROL_COUTST_SHIFT 0 132 // The channel output state is low. 133 #define SI32_PCACH_A_CONTROL_COUTST_LOW_VALUE 0 134 #define SI32_PCACH_A_CONTROL_COUTST_LOW_U32 \ 135 (SI32_PCACH_A_CONTROL_COUTST_LOW_VALUE << SI32_PCACH_A_CONTROL_COUTST_SHIFT) 136 // The channel output state is high. 137 #define SI32_PCACH_A_CONTROL_COUTST_HIGH_VALUE 1 138 #define SI32_PCACH_A_CONTROL_COUTST_HIGH_U32 \ 139 (SI32_PCACH_A_CONTROL_COUTST_HIGH_VALUE << SI32_PCACH_A_CONTROL_COUTST_SHIFT) 140 141 #define SI32_PCACH_A_CONTROL_CPCAPEN_MASK 0x00000002 142 #define SI32_PCACH_A_CONTROL_CPCAPEN_SHIFT 1 143 // Disable positive-edge input capture. 144 #define SI32_PCACH_A_CONTROL_CPCAPEN_DISABLED_VALUE 0 145 #define SI32_PCACH_A_CONTROL_CPCAPEN_DISABLED_U32 \ 146 (SI32_PCACH_A_CONTROL_CPCAPEN_DISABLED_VALUE << SI32_PCACH_A_CONTROL_CPCAPEN_SHIFT) 147 // Enable positive-edge input capture. 148 #define SI32_PCACH_A_CONTROL_CPCAPEN_ENABLED_VALUE 1 149 #define SI32_PCACH_A_CONTROL_CPCAPEN_ENABLED_U32 \ 150 (SI32_PCACH_A_CONTROL_CPCAPEN_ENABLED_VALUE << SI32_PCACH_A_CONTROL_CPCAPEN_SHIFT) 151 152 #define SI32_PCACH_A_CONTROL_CNCAPEN_MASK 0x00000004 153 #define SI32_PCACH_A_CONTROL_CNCAPEN_SHIFT 2 154 // Disable negative-edge input capture. 155 #define SI32_PCACH_A_CONTROL_CNCAPEN_DISABLED_VALUE 0 156 #define SI32_PCACH_A_CONTROL_CNCAPEN_DISABLED_U32 \ 157 (SI32_PCACH_A_CONTROL_CNCAPEN_DISABLED_VALUE << SI32_PCACH_A_CONTROL_CNCAPEN_SHIFT) 158 // Enable negative-edge input capture. 159 #define SI32_PCACH_A_CONTROL_CNCAPEN_ENABLED_VALUE 1 160 #define SI32_PCACH_A_CONTROL_CNCAPEN_ENABLED_U32 \ 161 (SI32_PCACH_A_CONTROL_CNCAPEN_ENABLED_VALUE << SI32_PCACH_A_CONTROL_CNCAPEN_SHIFT) 162 163 #define SI32_PCACH_A_CONTROL_CUPDCF_MASK 0x00000008 164 #define SI32_PCACH_A_CONTROL_CUPDCF_SHIFT 3 165 // A PCA channel register update completed or is not pending. 166 #define SI32_PCACH_A_CONTROL_CUPDCF_NOT_SET_VALUE 0 167 #define SI32_PCACH_A_CONTROL_CUPDCF_NOT_SET_U32 \ 168 (SI32_PCACH_A_CONTROL_CUPDCF_NOT_SET_VALUE << SI32_PCACH_A_CONTROL_CUPDCF_SHIFT) 169 // A PCA channel register update has not completed and is still pending. 170 #define SI32_PCACH_A_CONTROL_CUPDCF_SET_VALUE 1 171 #define SI32_PCACH_A_CONTROL_CUPDCF_SET_U32 \ 172 (SI32_PCACH_A_CONTROL_CUPDCF_SET_VALUE << SI32_PCACH_A_CONTROL_CUPDCF_SHIFT) 173 174 #define SI32_PCACH_A_CONTROL_CCIEN_MASK 0x00000100 175 #define SI32_PCACH_A_CONTROL_CCIEN_SHIFT 8 176 // Disable the channel capture/compare interrupt. 177 #define SI32_PCACH_A_CONTROL_CCIEN_DISABLED_VALUE 0 178 #define SI32_PCACH_A_CONTROL_CCIEN_DISABLED_U32 \ 179 (SI32_PCACH_A_CONTROL_CCIEN_DISABLED_VALUE << SI32_PCACH_A_CONTROL_CCIEN_SHIFT) 180 // Enable the channel capture/compare interrupt. 181 #define SI32_PCACH_A_CONTROL_CCIEN_ENABLED_VALUE 1 182 #define SI32_PCACH_A_CONTROL_CCIEN_ENABLED_U32 \ 183 (SI32_PCACH_A_CONTROL_CCIEN_ENABLED_VALUE << SI32_PCACH_A_CONTROL_CCIEN_SHIFT) 184 185 #define SI32_PCACH_A_CONTROL_CIOVFIEN_MASK 0x00000800 186 #define SI32_PCACH_A_CONTROL_CIOVFIEN_SHIFT 11 187 // Disable the channel intermediate overflow interrupt. 188 #define SI32_PCACH_A_CONTROL_CIOVFIEN_DISABLED_VALUE 0 189 #define SI32_PCACH_A_CONTROL_CIOVFIEN_DISABLED_U32 \ 190 (SI32_PCACH_A_CONTROL_CIOVFIEN_DISABLED_VALUE << SI32_PCACH_A_CONTROL_CIOVFIEN_SHIFT) 191 // Enable the channel intermediate overflow interrupt. 192 #define SI32_PCACH_A_CONTROL_CIOVFIEN_ENABLED_VALUE 1 193 #define SI32_PCACH_A_CONTROL_CIOVFIEN_ENABLED_U32 \ 194 (SI32_PCACH_A_CONTROL_CIOVFIEN_ENABLED_VALUE << SI32_PCACH_A_CONTROL_CIOVFIEN_SHIFT) 195 196 197 198 struct SI32_PCACH_A_CCAPV_Struct 199 { 200 union 201 { 202 struct 203 { 204 // Channel Compare Value 205 volatile uint32_t CCAPV_BITS: 18; 206 uint32_t reserved0: 14; 207 }; 208 volatile uint32_t U32; 209 }; 210 }; 211 212 #define SI32_PCACH_A_CCAPV_CCAPV_MASK 0x0003FFFF 213 #define SI32_PCACH_A_CCAPV_CCAPV_SHIFT 0 214 215 216 217 struct SI32_PCACH_A_CCAPVUPD_Struct 218 { 219 union 220 { 221 struct 222 { 223 // Channel Compare Update Value 224 volatile uint32_t CCAPVUPD_BITS: 18; 225 uint32_t reserved0: 14; 226 }; 227 volatile uint32_t U32; 228 }; 229 }; 230 231 #define SI32_PCACH_A_CCAPVUPD_CCAPVUPD_MASK 0x0003FFFF 232 #define SI32_PCACH_A_CCAPVUPD_CCAPVUPD_SHIFT 0 233 234 235 236 typedef struct SI32_PCACH_A_Struct 237 { 238 struct SI32_PCACH_A_MODE_Struct MODE ; // Base Address + 0x0 239 uint32_t reserved0; 240 uint32_t reserved1; 241 uint32_t reserved2; 242 struct SI32_PCACH_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 243 volatile uint32_t CONTROL_SET; 244 volatile uint32_t CONTROL_CLR; 245 uint32_t reserved3; 246 struct SI32_PCACH_A_CCAPV_Struct CCAPV ; // Base Address + 0x20 247 uint32_t reserved4; 248 uint32_t reserved5; 249 uint32_t reserved6; 250 struct SI32_PCACH_A_CCAPVUPD_Struct CCAPVUPD ; // Base Address + 0x30 251 uint32_t reserved7; 252 uint32_t reserved8; 253 uint32_t reserved9; 254 } SI32_PCACH_A_Type; 255 256 #ifdef __cplusplus 257 } 258 #endif 259 260 #endif // __SI32_PCACH_A_REGISTERS_H__ 261 262 //-eof-------------------------------------------------------------------------- 263 264
