1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // This file applies to the SIM3L1XX_PBCFG_A module 24 // 25 // Script: 0.61 26 // Version: 1 27 28 #ifndef __SI32_PBCFG_A_REGISTERS_H__ 29 #define __SI32_PBCFG_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_PBCFG_A_CONTROL0_Struct 38 { 39 union 40 { 41 struct 42 { 43 // External Interrupt 0 Pin Selection 44 volatile uint32_t INT0SEL: 4; 45 // External Interrupt 0 Polarity 46 volatile uint32_t INT0POL: 1; 47 // External Interrupt 0 Mode 48 volatile uint32_t INT0MD: 2; 49 // External Interrupt 0 Enable 50 volatile uint32_t INT0EN: 1; 51 // External Interrupt 1 Pin Selection 52 volatile uint32_t INT1SEL: 4; 53 // External Interrupt 1 Polarity 54 volatile uint32_t INT1POL: 1; 55 // External Interrupt 1 Mode 56 volatile uint32_t INT1MD: 2; 57 // External Interrupt 1 Enable 58 volatile uint32_t INT1EN: 1; 59 uint32_t reserved0: 8; 60 // Pulse Generator Timer 61 volatile uint32_t PGTIMER: 5; 62 uint32_t reserved1: 2; 63 // Pulse Generator Timer Done Flag 64 volatile uint32_t PGDONEF: 1; 65 }; 66 volatile uint32_t U32; 67 }; 68 }; 69 70 #define SI32_PBCFG_A_CONTROL0_INT0SEL_MASK 0x0000000F 71 #define SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT 0 72 // Select INT0.0 73 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_0_VALUE 0 74 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_0_U32 \ 75 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_0_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 76 // Select INT0.1 77 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_1_VALUE 1 78 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_1_U32 \ 79 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_1_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 80 // Select INT0.2 81 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_2_VALUE 2 82 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_2_U32 \ 83 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_2_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 84 // Select INT0.3 85 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_3_VALUE 3 86 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_3_U32 \ 87 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_3_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 88 // Select INT0.4 89 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_4_VALUE 4 90 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_4_U32 \ 91 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_4_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 92 // Select INT0.5 93 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_5_VALUE 5 94 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_5_U32 \ 95 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_5_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 96 // Select INT0.6 97 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_6_VALUE 6 98 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_6_U32 \ 99 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_6_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 100 // Select INT0.7 101 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_7_VALUE 7 102 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_7_U32 \ 103 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_7_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 104 // Select INT0.8 105 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_8_VALUE 8 106 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_8_U32 \ 107 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_8_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 108 // Select INT0.9 109 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_9_VALUE 9 110 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_9_U32 \ 111 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_9_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 112 // Select INT0.10 113 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_10_VALUE 10 114 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_10_U32 \ 115 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_10_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 116 // Select INT0.11 117 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_11_VALUE 11 118 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_11_U32 \ 119 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_11_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 120 // Select INT0.12 121 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_12_VALUE 12 122 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_12_U32 \ 123 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_12_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 124 // Select INT0.13 125 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_13_VALUE 13 126 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_13_U32 \ 127 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_13_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 128 // Select INT0.14 129 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_14_VALUE 14 130 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_14_U32 \ 131 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_14_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 132 // Select INT0.15 133 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_15_VALUE 15 134 #define SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_15_U32 \ 135 (SI32_PBCFG_A_CONTROL0_INT0SEL_INT0_15_VALUE << SI32_PBCFG_A_CONTROL0_INT0SEL_SHIFT) 136 137 #define SI32_PBCFG_A_CONTROL0_INT0POL_MASK 0x00000010 138 #define SI32_PBCFG_A_CONTROL0_INT0POL_SHIFT 4 139 // A low value or falling edge on the selected pin will cause interrupt. 140 #define SI32_PBCFG_A_CONTROL0_INT0POL_LOW_VALUE 0 141 #define SI32_PBCFG_A_CONTROL0_INT0POL_LOW_U32 \ 142 (SI32_PBCFG_A_CONTROL0_INT0POL_LOW_VALUE << SI32_PBCFG_A_CONTROL0_INT0POL_SHIFT) 143 // A high value or rising edge on the selected pin will cause interrupt. 144 #define SI32_PBCFG_A_CONTROL0_INT0POL_HIGH_VALUE 1 145 #define SI32_PBCFG_A_CONTROL0_INT0POL_HIGH_U32 \ 146 (SI32_PBCFG_A_CONTROL0_INT0POL_HIGH_VALUE << SI32_PBCFG_A_CONTROL0_INT0POL_SHIFT) 147 148 #define SI32_PBCFG_A_CONTROL0_INT0MD_MASK 0x00000060 149 #define SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT 5 150 // Interrupt on logic level at pin, as selected by the INT0POL field. 151 #define SI32_PBCFG_A_CONTROL0_INT0MD_LEVEL_VALUE 0 152 #define SI32_PBCFG_A_CONTROL0_INT0MD_LEVEL_U32 \ 153 (SI32_PBCFG_A_CONTROL0_INT0MD_LEVEL_VALUE << SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT) 154 // Interrupt on either rising or falling edge, as selected by the INT0POL field. 155 #define SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_VALUE 1 156 #define SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_U32 \ 157 (SI32_PBCFG_A_CONTROL0_INT0MD_EDGE_VALUE << SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT) 158 // Interrupt on both rising and falling edges (ignores INT0POL). 159 #define SI32_PBCFG_A_CONTROL0_INT0MD_DUAL_EDGE_VALUE 2 160 #define SI32_PBCFG_A_CONTROL0_INT0MD_DUAL_EDGE_U32 \ 161 (SI32_PBCFG_A_CONTROL0_INT0MD_DUAL_EDGE_VALUE << SI32_PBCFG_A_CONTROL0_INT0MD_SHIFT) 162 163 #define SI32_PBCFG_A_CONTROL0_INT0EN_MASK 0x00000080 164 #define SI32_PBCFG_A_CONTROL0_INT0EN_SHIFT 7 165 // Disable external interrupt 0. 166 #define SI32_PBCFG_A_CONTROL0_INT0EN_DISABLED_VALUE 0 167 #define SI32_PBCFG_A_CONTROL0_INT0EN_DISABLED_U32 \ 168 (SI32_PBCFG_A_CONTROL0_INT0EN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT0EN_SHIFT) 169 // Enable external interrupt 0. 170 #define SI32_PBCFG_A_CONTROL0_INT0EN_ENABLED_VALUE 1 171 #define SI32_PBCFG_A_CONTROL0_INT0EN_ENABLED_U32 \ 172 (SI32_PBCFG_A_CONTROL0_INT0EN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT0EN_SHIFT) 173 174 #define SI32_PBCFG_A_CONTROL0_INT1SEL_MASK 0x00000F00 175 #define SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT 8 176 // Select INT1.0 177 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_0_VALUE 0 178 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_0_U32 \ 179 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_0_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 180 // Select INT1.1 181 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_1_VALUE 1 182 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_1_U32 \ 183 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_1_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 184 // Select INT1.2 185 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_2_VALUE 2 186 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_2_U32 \ 187 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_2_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 188 // Select INT1.3 189 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_3_VALUE 3 190 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_3_U32 \ 191 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_3_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 192 // Select INT1.4 193 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_4_VALUE 4 194 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_4_U32 \ 195 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_4_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 196 // Select INT1.5 197 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_5_VALUE 5 198 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_5_U32 \ 199 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_5_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 200 // Select INT1.6 201 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_6_VALUE 6 202 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_6_U32 \ 203 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_6_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 204 // Select INT1.7 205 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_7_VALUE 7 206 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_7_U32 \ 207 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_7_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 208 // Select INT1.8 209 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_8_VALUE 8 210 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_8_U32 \ 211 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_8_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 212 // Select INT1.9 213 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_9_VALUE 9 214 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_9_U32 \ 215 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_9_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 216 // Select INT1.10 217 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_10_VALUE 10 218 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_10_U32 \ 219 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_10_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 220 // Select INT1.11 221 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_11_VALUE 11 222 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_11_U32 \ 223 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_11_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 224 // Select INT1.12 225 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_12_VALUE 12 226 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_12_U32 \ 227 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_12_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 228 // Select INT1.13 229 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_13_VALUE 13 230 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_13_U32 \ 231 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_13_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 232 // Select INT1.14 233 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_14_VALUE 14 234 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_14_U32 \ 235 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_14_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 236 // Select INT1.15 237 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_15_VALUE 15 238 #define SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_15_U32 \ 239 (SI32_PBCFG_A_CONTROL0_INT1SEL_INT1_15_VALUE << SI32_PBCFG_A_CONTROL0_INT1SEL_SHIFT) 240 241 #define SI32_PBCFG_A_CONTROL0_INT1POL_MASK 0x00001000 242 #define SI32_PBCFG_A_CONTROL0_INT1POL_SHIFT 12 243 // A low value or falling edge on the selected pin will cause interrupt. 244 #define SI32_PBCFG_A_CONTROL0_INT1POL_LOW_VALUE 0 245 #define SI32_PBCFG_A_CONTROL0_INT1POL_LOW_U32 \ 246 (SI32_PBCFG_A_CONTROL0_INT1POL_LOW_VALUE << SI32_PBCFG_A_CONTROL0_INT1POL_SHIFT) 247 // A high value or rising edge on the selected pin will cause interrupt. 248 #define SI32_PBCFG_A_CONTROL0_INT1POL_HIGH_VALUE 1 249 #define SI32_PBCFG_A_CONTROL0_INT1POL_HIGH_U32 \ 250 (SI32_PBCFG_A_CONTROL0_INT1POL_HIGH_VALUE << SI32_PBCFG_A_CONTROL0_INT1POL_SHIFT) 251 252 #define SI32_PBCFG_A_CONTROL0_INT1MD_MASK 0x00006000 253 #define SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT 13 254 // Interrupt on logic level at pin, as selected by the INT1POL field. 255 #define SI32_PBCFG_A_CONTROL0_INT1MD_LEVEL_VALUE 0 256 #define SI32_PBCFG_A_CONTROL0_INT1MD_LEVEL_U32 \ 257 (SI32_PBCFG_A_CONTROL0_INT1MD_LEVEL_VALUE << SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT) 258 // Interrupt on either rising or falling edge, as selected by the INT1POL field. 259 #define SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_VALUE 1 260 #define SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_U32 \ 261 (SI32_PBCFG_A_CONTROL0_INT1MD_EDGE_VALUE << SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT) 262 // Interrupt on both rising and falling edges (ignores INT1POL). 263 #define SI32_PBCFG_A_CONTROL0_INT1MD_DUAL_EDGE_VALUE 2 264 #define SI32_PBCFG_A_CONTROL0_INT1MD_DUAL_EDGE_U32 \ 265 (SI32_PBCFG_A_CONTROL0_INT1MD_DUAL_EDGE_VALUE << SI32_PBCFG_A_CONTROL0_INT1MD_SHIFT) 266 267 #define SI32_PBCFG_A_CONTROL0_INT1EN_MASK 0x00008000 268 #define SI32_PBCFG_A_CONTROL0_INT1EN_SHIFT 15 269 // Disable external interrupt 1. 270 #define SI32_PBCFG_A_CONTROL0_INT1EN_DISABLED_VALUE 0 271 #define SI32_PBCFG_A_CONTROL0_INT1EN_DISABLED_U32 \ 272 (SI32_PBCFG_A_CONTROL0_INT1EN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT1EN_SHIFT) 273 // Enable external interrupt 1. 274 #define SI32_PBCFG_A_CONTROL0_INT1EN_ENABLED_VALUE 1 275 #define SI32_PBCFG_A_CONTROL0_INT1EN_ENABLED_U32 \ 276 (SI32_PBCFG_A_CONTROL0_INT1EN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL0_INT1EN_SHIFT) 277 278 #define SI32_PBCFG_A_CONTROL0_PGTIMER_MASK 0x1F000000 279 #define SI32_PBCFG_A_CONTROL0_PGTIMER_SHIFT 24 280 281 #define SI32_PBCFG_A_CONTROL0_PGDONEF_MASK 0x80000000 282 #define SI32_PBCFG_A_CONTROL0_PGDONEF_SHIFT 31 283 // Firmware has written to the PBPGPHASE register, but the Pulse Generator timer 284 // has not expired. 285 #define SI32_PBCFG_A_CONTROL0_PGDONEF_NOT_SET_VALUE 0U 286 #define SI32_PBCFG_A_CONTROL0_PGDONEF_NOT_SET_U32 \ 287 (SI32_PBCFG_A_CONTROL0_PGDONEF_NOT_SET_VALUE << SI32_PBCFG_A_CONTROL0_PGDONEF_SHIFT) 288 // The Pulse Generator cycle finished since the last time PBPGPHASE was written. 289 #define SI32_PBCFG_A_CONTROL0_PGDONEF_SET_VALUE 1U 290 #define SI32_PBCFG_A_CONTROL0_PGDONEF_SET_U32 \ 291 (SI32_PBCFG_A_CONTROL0_PGDONEF_SET_VALUE << SI32_PBCFG_A_CONTROL0_PGDONEF_SHIFT) 292 293 294 295 struct SI32_PBCFG_A_CONTROL1_Struct 296 { 297 union 298 { 299 struct 300 { 301 // JTAG Enable 302 volatile uint32_t JTAGEN: 1; 303 // ETM Enable 304 volatile uint32_t ETMEN: 1; 305 // SWV Enable 306 volatile uint32_t SWVEN: 1; 307 uint32_t reserved0: 5; 308 // SPI1 Fixed Port Selection 309 volatile uint32_t SPI1SEL: 1; 310 // Port Match Interrupt Enable 311 volatile uint32_t PMATCHEN: 1; 312 uint32_t reserved1: 2; 313 // Low Power Timer Output Pin Select 314 volatile uint32_t LPTOSEL: 1; 315 uint32_t reserved2: 18; 316 // Port Bank Configuration Lock 317 volatile uint32_t LOCK: 1; 318 }; 319 volatile uint32_t U32; 320 }; 321 }; 322 323 #define SI32_PBCFG_A_CONTROL1_JTAGEN_MASK 0x00000001 324 #define SI32_PBCFG_A_CONTROL1_JTAGEN_SHIFT 0 325 // JTAG functionality is not pinned out. 326 #define SI32_PBCFG_A_CONTROL1_JTAGEN_DISABLED_VALUE 0 327 #define SI32_PBCFG_A_CONTROL1_JTAGEN_DISABLED_U32 \ 328 (SI32_PBCFG_A_CONTROL1_JTAGEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_JTAGEN_SHIFT) 329 // JTAG functionality is pinned out. 330 #define SI32_PBCFG_A_CONTROL1_JTAGEN_ENABLED_VALUE 1 331 #define SI32_PBCFG_A_CONTROL1_JTAGEN_ENABLED_U32 \ 332 (SI32_PBCFG_A_CONTROL1_JTAGEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_JTAGEN_SHIFT) 333 334 #define SI32_PBCFG_A_CONTROL1_ETMEN_MASK 0x00000002 335 #define SI32_PBCFG_A_CONTROL1_ETMEN_SHIFT 1 336 // ETM not pinned out. 337 #define SI32_PBCFG_A_CONTROL1_ETMEN_DISABLED_VALUE 0 338 #define SI32_PBCFG_A_CONTROL1_ETMEN_DISABLED_U32 \ 339 (SI32_PBCFG_A_CONTROL1_ETMEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_ETMEN_SHIFT) 340 // ETM is enabled and pinned out. 341 #define SI32_PBCFG_A_CONTROL1_ETMEN_ENABLED_VALUE 1 342 #define SI32_PBCFG_A_CONTROL1_ETMEN_ENABLED_U32 \ 343 (SI32_PBCFG_A_CONTROL1_ETMEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_ETMEN_SHIFT) 344 345 #define SI32_PBCFG_A_CONTROL1_SWVEN_MASK 0x00000004 346 #define SI32_PBCFG_A_CONTROL1_SWVEN_SHIFT 2 347 // SWV is not pinned out. 348 #define SI32_PBCFG_A_CONTROL1_SWVEN_DISABLED_VALUE 0 349 #define SI32_PBCFG_A_CONTROL1_SWVEN_DISABLED_U32 \ 350 (SI32_PBCFG_A_CONTROL1_SWVEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_SWVEN_SHIFT) 351 // SWV is enabled and pinned out. 352 #define SI32_PBCFG_A_CONTROL1_SWVEN_ENABLED_VALUE 1 353 #define SI32_PBCFG_A_CONTROL1_SWVEN_ENABLED_U32 \ 354 (SI32_PBCFG_A_CONTROL1_SWVEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_SWVEN_SHIFT) 355 356 #define SI32_PBCFG_A_CONTROL1_SPI1SEL_MASK 0x00000100 357 #define SI32_PBCFG_A_CONTROL1_SPI1SEL_SHIFT 8 358 // Disconnect SPI1 from the dedicated pins. 359 #define SI32_PBCFG_A_CONTROL1_SPI1SEL_DISABLED_VALUE 0 360 #define SI32_PBCFG_A_CONTROL1_SPI1SEL_DISABLED_U32 \ 361 (SI32_PBCFG_A_CONTROL1_SPI1SEL_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_SPI1SEL_SHIFT) 362 // Connect SPI1 to the dedicated pins. 363 #define SI32_PBCFG_A_CONTROL1_SPI1SEL_ENABLED_VALUE 1 364 #define SI32_PBCFG_A_CONTROL1_SPI1SEL_ENABLED_U32 \ 365 (SI32_PBCFG_A_CONTROL1_SPI1SEL_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_SPI1SEL_SHIFT) 366 367 #define SI32_PBCFG_A_CONTROL1_PMATCHEN_MASK 0x00000200 368 #define SI32_PBCFG_A_CONTROL1_PMATCHEN_SHIFT 9 369 // Disable the port match logic. The PBnMAT registers are not read/write accessible 370 // on the APB bus. 371 #define SI32_PBCFG_A_CONTROL1_PMATCHEN_DISABLED_VALUE 0 372 #define SI32_PBCFG_A_CONTROL1_PMATCHEN_DISABLED_U32 \ 373 (SI32_PBCFG_A_CONTROL1_PMATCHEN_DISABLED_VALUE << SI32_PBCFG_A_CONTROL1_PMATCHEN_SHIFT) 374 // Enable the port match logic to generate a port match interrupt. The PBnMAT 375 // registers are read/write accessible on the APB bus. 376 #define SI32_PBCFG_A_CONTROL1_PMATCHEN_ENABLED_VALUE 1 377 #define SI32_PBCFG_A_CONTROL1_PMATCHEN_ENABLED_U32 \ 378 (SI32_PBCFG_A_CONTROL1_PMATCHEN_ENABLED_VALUE << SI32_PBCFG_A_CONTROL1_PMATCHEN_SHIFT) 379 380 #define SI32_PBCFG_A_CONTROL1_LPTOSEL_MASK 0x00001000 381 #define SI32_PBCFG_A_CONTROL1_LPTOSEL_SHIFT 12 382 // Route the Low Power Timer output to LPT0OUT0. 383 #define SI32_PBCFG_A_CONTROL1_LPTOSEL_LPT0OUT0_VALUE 0 384 #define SI32_PBCFG_A_CONTROL1_LPTOSEL_LPT0OUT0_U32 \ 385 (SI32_PBCFG_A_CONTROL1_LPTOSEL_LPT0OUT0_VALUE << SI32_PBCFG_A_CONTROL1_LPTOSEL_SHIFT) 386 // Route the Low Power Timer output to LPT0OUT1. 387 #define SI32_PBCFG_A_CONTROL1_LPTOSEL_LPT0OUT1_VALUE 1 388 #define SI32_PBCFG_A_CONTROL1_LPTOSEL_LPT0OUT1_U32 \ 389 (SI32_PBCFG_A_CONTROL1_LPTOSEL_LPT0OUT1_VALUE << SI32_PBCFG_A_CONTROL1_LPTOSEL_SHIFT) 390 391 #define SI32_PBCFG_A_CONTROL1_LOCK_MASK 0x80000000 392 #define SI32_PBCFG_A_CONTROL1_LOCK_SHIFT 31 393 // Port Bank Configuration and Control registers are unlocked. 394 #define SI32_PBCFG_A_CONTROL1_LOCK_UNLOCKED_VALUE 0U 395 #define SI32_PBCFG_A_CONTROL1_LOCK_UNLOCKED_U32 \ 396 (SI32_PBCFG_A_CONTROL1_LOCK_UNLOCKED_VALUE << SI32_PBCFG_A_CONTROL1_LOCK_SHIFT) 397 // The following registers are locked from write access: CONTROL1, XBAR0, and all 398 // PBSKIP registers. 399 #define SI32_PBCFG_A_CONTROL1_LOCK_LOCKED_VALUE 1U 400 #define SI32_PBCFG_A_CONTROL1_LOCK_LOCKED_U32 \ 401 (SI32_PBCFG_A_CONTROL1_LOCK_LOCKED_VALUE << SI32_PBCFG_A_CONTROL1_LOCK_SHIFT) 402 403 404 405 struct SI32_PBCFG_A_XBAR0_Struct 406 { 407 union 408 { 409 struct 410 { 411 // USART0 Enable 412 volatile uint32_t USART0EN: 1; 413 // USART0 Flow Control Enable 414 volatile uint32_t USART0FCEN: 1; 415 // USART0 Clock Signal Enable 416 volatile uint32_t USART0CEN: 1; 417 // DMA Trigger 0 Enable 418 volatile uint32_t DMA0T0EN: 1; 419 // DMA Trigger 1 Enabled 420 volatile uint32_t DMA0T1EN: 1; 421 // IDAC0 Trigger Enable 422 volatile uint32_t IDAC0TEN: 1; 423 // SPI0 Enable 424 volatile uint32_t SPI0EN: 1; 425 // SPI0 NSS Pin Enable 426 volatile uint32_t SPI0NSSEN: 1; 427 // EPCA0 Channel Enable 428 volatile uint32_t EPCA0EN: 3; 429 // EPCA0 ECI Enable 430 volatile uint32_t EECI0EN: 1; 431 // I2C0 Enable 432 volatile uint32_t I2C0EN: 1; 433 // Comparator 0 Synchronous Output (CMP0S) Enable 434 volatile uint32_t CMP0SEN: 1; 435 // Comparator 0 Asynchronous Output (CMP0A) Enable 436 volatile uint32_t CMP0AEN: 1; 437 // Comparator 1 Synchronous Output (CMP1S) Enable 438 volatile uint32_t CMP1SEN: 1; 439 // Comparator 1 Asynchronous Output (CMP1A) Enable 440 volatile uint32_t CMP1AEN: 1; 441 // TIMER0 T0CT Enable 442 volatile uint32_t TMR0CTEN: 1; 443 // TIMER0 T0EX Enable 444 volatile uint32_t TMR0EXEN: 1; 445 // TIMER1 T1CT Enable 446 volatile uint32_t TMR1CTEN: 1; 447 // TIMER1 T1EX Enable 448 volatile uint32_t TMR1EXEN: 1; 449 // SARADC0 Trigger Enable 450 volatile uint32_t SARADC0TEN: 1; 451 // AHB Clock Output Enable 452 volatile uint32_t AHBEN: 1; 453 uint32_t reserved0: 8; 454 // Crossbar 0 Enable 455 volatile uint32_t XBAR0EN: 1; 456 }; 457 volatile uint32_t U32; 458 }; 459 }; 460 461 #define SI32_PBCFG_A_XBAR0_USART0EN_MASK 0x00000001 462 #define SI32_PBCFG_A_XBAR0_USART0EN_SHIFT 0 463 // Disable USART0 RX and TX on Crossbar 0. 464 #define SI32_PBCFG_A_XBAR0_USART0EN_DISABLED_VALUE 0 465 #define SI32_PBCFG_A_XBAR0_USART0EN_DISABLED_U32 \ 466 (SI32_PBCFG_A_XBAR0_USART0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_USART0EN_SHIFT) 467 // Enable USART0 RX and TX on Crossbar 0. 468 #define SI32_PBCFG_A_XBAR0_USART0EN_ENABLED_VALUE 1 469 #define SI32_PBCFG_A_XBAR0_USART0EN_ENABLED_U32 \ 470 (SI32_PBCFG_A_XBAR0_USART0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_USART0EN_SHIFT) 471 472 #define SI32_PBCFG_A_XBAR0_USART0FCEN_MASK 0x00000002 473 #define SI32_PBCFG_A_XBAR0_USART0FCEN_SHIFT 1 474 // Disable USART0 flow control on Crossbar 0. 475 #define SI32_PBCFG_A_XBAR0_USART0FCEN_DISABLED_VALUE 0 476 #define SI32_PBCFG_A_XBAR0_USART0FCEN_DISABLED_U32 \ 477 (SI32_PBCFG_A_XBAR0_USART0FCEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_USART0FCEN_SHIFT) 478 // Enable USART0 flow control on Crossbar 0. 479 #define SI32_PBCFG_A_XBAR0_USART0FCEN_ENABLED_VALUE 1 480 #define SI32_PBCFG_A_XBAR0_USART0FCEN_ENABLED_U32 \ 481 (SI32_PBCFG_A_XBAR0_USART0FCEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_USART0FCEN_SHIFT) 482 483 #define SI32_PBCFG_A_XBAR0_USART0CEN_MASK 0x00000004 484 #define SI32_PBCFG_A_XBAR0_USART0CEN_SHIFT 2 485 // Disable USART0 clock on Crossbar 0. 486 #define SI32_PBCFG_A_XBAR0_USART0CEN_DISABLED_VALUE 0 487 #define SI32_PBCFG_A_XBAR0_USART0CEN_DISABLED_U32 \ 488 (SI32_PBCFG_A_XBAR0_USART0CEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_USART0CEN_SHIFT) 489 // Enable USART0 clock on Crossbar 0. 490 #define SI32_PBCFG_A_XBAR0_USART0CEN_ENABLED_VALUE 1 491 #define SI32_PBCFG_A_XBAR0_USART0CEN_ENABLED_U32 \ 492 (SI32_PBCFG_A_XBAR0_USART0CEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_USART0CEN_SHIFT) 493 494 #define SI32_PBCFG_A_XBAR0_DMA0T0EN_MASK 0x00000008 495 #define SI32_PBCFG_A_XBAR0_DMA0T0EN_SHIFT 3 496 // Disable the DMA trigger 0 on Crossbar 0. 497 #define SI32_PBCFG_A_XBAR0_DMA0T0EN_DISABLED_VALUE 0 498 #define SI32_PBCFG_A_XBAR0_DMA0T0EN_DISABLED_U32 \ 499 (SI32_PBCFG_A_XBAR0_DMA0T0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_DMA0T0EN_SHIFT) 500 // Enable the DMA trigger 0 on Crossbar 0. 501 #define SI32_PBCFG_A_XBAR0_DMA0T0EN_ENABLED_VALUE 1 502 #define SI32_PBCFG_A_XBAR0_DMA0T0EN_ENABLED_U32 \ 503 (SI32_PBCFG_A_XBAR0_DMA0T0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_DMA0T0EN_SHIFT) 504 505 #define SI32_PBCFG_A_XBAR0_DMA0T1EN_MASK 0x00000010 506 #define SI32_PBCFG_A_XBAR0_DMA0T1EN_SHIFT 4 507 // Disable the DMA trigger 1 on Crossbar 0. 508 #define SI32_PBCFG_A_XBAR0_DMA0T1EN_DISABLED_VALUE 0 509 #define SI32_PBCFG_A_XBAR0_DMA0T1EN_DISABLED_U32 \ 510 (SI32_PBCFG_A_XBAR0_DMA0T1EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_DMA0T1EN_SHIFT) 511 // Enable the DMA trigger 1 on Crossbar 0. 512 #define SI32_PBCFG_A_XBAR0_DMA0T1EN_ENABLED_VALUE 1 513 #define SI32_PBCFG_A_XBAR0_DMA0T1EN_ENABLED_U32 \ 514 (SI32_PBCFG_A_XBAR0_DMA0T1EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_DMA0T1EN_SHIFT) 515 516 #define SI32_PBCFG_A_XBAR0_IDAC0TEN_MASK 0x00000020 517 #define SI32_PBCFG_A_XBAR0_IDAC0TEN_SHIFT 5 518 // Disable the IDAC0 trigger on Crossbar 0. 519 #define SI32_PBCFG_A_XBAR0_IDAC0TEN_DISABLED_VALUE 0 520 #define SI32_PBCFG_A_XBAR0_IDAC0TEN_DISABLED_U32 \ 521 (SI32_PBCFG_A_XBAR0_IDAC0TEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_IDAC0TEN_SHIFT) 522 // Enable the IDAC0 trigger on Crossbar 0. 523 #define SI32_PBCFG_A_XBAR0_IDAC0TEN_ENABLED_VALUE 1 524 #define SI32_PBCFG_A_XBAR0_IDAC0TEN_ENABLED_U32 \ 525 (SI32_PBCFG_A_XBAR0_IDAC0TEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_IDAC0TEN_SHIFT) 526 527 #define SI32_PBCFG_A_XBAR0_SPI0EN_MASK 0x00000040 528 #define SI32_PBCFG_A_XBAR0_SPI0EN_SHIFT 6 529 // Disable SPI0 SCK, MISO, and MOSI on Crossbar 0. 530 #define SI32_PBCFG_A_XBAR0_SPI0EN_DISABLED_VALUE 0 531 #define SI32_PBCFG_A_XBAR0_SPI0EN_DISABLED_U32 \ 532 (SI32_PBCFG_A_XBAR0_SPI0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_SPI0EN_SHIFT) 533 // Enable SPI0 SCK, MISO, and MOSI on Crossbar 0. 534 #define SI32_PBCFG_A_XBAR0_SPI0EN_ENABLED_VALUE 1 535 #define SI32_PBCFG_A_XBAR0_SPI0EN_ENABLED_U32 \ 536 (SI32_PBCFG_A_XBAR0_SPI0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_SPI0EN_SHIFT) 537 538 #define SI32_PBCFG_A_XBAR0_SPI0NSSEN_MASK 0x00000080 539 #define SI32_PBCFG_A_XBAR0_SPI0NSSEN_SHIFT 7 540 // Disable SPI0 NSS on Crossbar 0. 541 #define SI32_PBCFG_A_XBAR0_SPI0NSSEN_DISABLED_VALUE 0 542 #define SI32_PBCFG_A_XBAR0_SPI0NSSEN_DISABLED_U32 \ 543 (SI32_PBCFG_A_XBAR0_SPI0NSSEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_SPI0NSSEN_SHIFT) 544 // Enable SPI0 NSS on Crossbar 0. 545 #define SI32_PBCFG_A_XBAR0_SPI0NSSEN_ENABLED_VALUE 1 546 #define SI32_PBCFG_A_XBAR0_SPI0NSSEN_ENABLED_U32 \ 547 (SI32_PBCFG_A_XBAR0_SPI0NSSEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_SPI0NSSEN_SHIFT) 548 549 #define SI32_PBCFG_A_XBAR0_EPCA0EN_MASK 0x00000700 550 #define SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT 8 551 // Disable all EPCA0 channels on Crossbar 0. 552 #define SI32_PBCFG_A_XBAR0_EPCA0EN_NONE_VALUE 0 553 #define SI32_PBCFG_A_XBAR0_EPCA0EN_NONE_U32 \ 554 (SI32_PBCFG_A_XBAR0_EPCA0EN_NONE_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 555 // Enable EPCA0 CEX0 on Crossbar 0. 556 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_0_VALUE 1 557 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_0_U32 \ 558 (SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_0_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 559 // Enable EPCA0 CEX0 and CEX1 on Crossbar 0. 560 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_1_VALUE 2 561 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_1_U32 \ 562 (SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_1_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 563 // Enable EPCA0 CEX0, CEX1, and CEX2 on Crossbar 0. 564 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_2_VALUE 3 565 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_2_U32 \ 566 (SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_2_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 567 // Enable EPCA0 CEX0, CEX1, CEX2, and CEX3 on Crossbar 0. 568 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_3_VALUE 4 569 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_3_U32 \ 570 (SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_3_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 571 // Enable EPCA0 CEX0, CEX1, CEX2, CEX3, and CEX4 on Crossbar 0. 572 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_4_VALUE 5 573 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_4_U32 \ 574 (SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_4_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 575 // Enable EPCA0 CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 on Crossbar 0. 576 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_5_VALUE 6 577 #define SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_5_U32 \ 578 (SI32_PBCFG_A_XBAR0_EPCA0EN_CEX0_5_VALUE << SI32_PBCFG_A_XBAR0_EPCA0EN_SHIFT) 579 580 #define SI32_PBCFG_A_XBAR0_EECI0EN_MASK 0x00000800 581 #define SI32_PBCFG_A_XBAR0_EECI0EN_SHIFT 11 582 // Disable EPCA0 ECI on Crossbar 0. 583 #define SI32_PBCFG_A_XBAR0_EECI0EN_DISABLED_VALUE 0 584 #define SI32_PBCFG_A_XBAR0_EECI0EN_DISABLED_U32 \ 585 (SI32_PBCFG_A_XBAR0_EECI0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_EECI0EN_SHIFT) 586 // Enable EPCA0 ECI on Crossbar 0. 587 #define SI32_PBCFG_A_XBAR0_EECI0EN_ENABLED_VALUE 1 588 #define SI32_PBCFG_A_XBAR0_EECI0EN_ENABLED_U32 \ 589 (SI32_PBCFG_A_XBAR0_EECI0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_EECI0EN_SHIFT) 590 591 #define SI32_PBCFG_A_XBAR0_I2C0EN_MASK 0x00001000 592 #define SI32_PBCFG_A_XBAR0_I2C0EN_SHIFT 12 593 // Disable I2C0 SDA and SCL on Crossbar 0. 594 #define SI32_PBCFG_A_XBAR0_I2C0EN_DISABLED_VALUE 0 595 #define SI32_PBCFG_A_XBAR0_I2C0EN_DISABLED_U32 \ 596 (SI32_PBCFG_A_XBAR0_I2C0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_I2C0EN_SHIFT) 597 // Enable I2C0 SDA and SCL on Crossbar 0. 598 #define SI32_PBCFG_A_XBAR0_I2C0EN_ENABLED_VALUE 1 599 #define SI32_PBCFG_A_XBAR0_I2C0EN_ENABLED_U32 \ 600 (SI32_PBCFG_A_XBAR0_I2C0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_I2C0EN_SHIFT) 601 602 #define SI32_PBCFG_A_XBAR0_CMP0SEN_MASK 0x00002000 603 #define SI32_PBCFG_A_XBAR0_CMP0SEN_SHIFT 13 604 // Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0. 605 #define SI32_PBCFG_A_XBAR0_CMP0SEN_DISABLED_VALUE 0 606 #define SI32_PBCFG_A_XBAR0_CMP0SEN_DISABLED_U32 \ 607 (SI32_PBCFG_A_XBAR0_CMP0SEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP0SEN_SHIFT) 608 // Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0. 609 #define SI32_PBCFG_A_XBAR0_CMP0SEN_ENABLED_VALUE 1 610 #define SI32_PBCFG_A_XBAR0_CMP0SEN_ENABLED_U32 \ 611 (SI32_PBCFG_A_XBAR0_CMP0SEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP0SEN_SHIFT) 612 613 #define SI32_PBCFG_A_XBAR0_CMP0AEN_MASK 0x00004000 614 #define SI32_PBCFG_A_XBAR0_CMP0AEN_SHIFT 14 615 // Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0. 616 #define SI32_PBCFG_A_XBAR0_CMP0AEN_DISABLED_VALUE 0 617 #define SI32_PBCFG_A_XBAR0_CMP0AEN_DISABLED_U32 \ 618 (SI32_PBCFG_A_XBAR0_CMP0AEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP0AEN_SHIFT) 619 // Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0. 620 #define SI32_PBCFG_A_XBAR0_CMP0AEN_ENABLED_VALUE 1 621 #define SI32_PBCFG_A_XBAR0_CMP0AEN_ENABLED_U32 \ 622 (SI32_PBCFG_A_XBAR0_CMP0AEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP0AEN_SHIFT) 623 624 #define SI32_PBCFG_A_XBAR0_CMP1SEN_MASK 0x00008000 625 #define SI32_PBCFG_A_XBAR0_CMP1SEN_SHIFT 15 626 // Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0. 627 #define SI32_PBCFG_A_XBAR0_CMP1SEN_DISABLED_VALUE 0 628 #define SI32_PBCFG_A_XBAR0_CMP1SEN_DISABLED_U32 \ 629 (SI32_PBCFG_A_XBAR0_CMP1SEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP1SEN_SHIFT) 630 // Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0. 631 #define SI32_PBCFG_A_XBAR0_CMP1SEN_ENABLED_VALUE 1 632 #define SI32_PBCFG_A_XBAR0_CMP1SEN_ENABLED_U32 \ 633 (SI32_PBCFG_A_XBAR0_CMP1SEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP1SEN_SHIFT) 634 635 #define SI32_PBCFG_A_XBAR0_CMP1AEN_MASK 0x00010000 636 #define SI32_PBCFG_A_XBAR0_CMP1AEN_SHIFT 16 637 // Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0. 638 #define SI32_PBCFG_A_XBAR0_CMP1AEN_DISABLED_VALUE 0 639 #define SI32_PBCFG_A_XBAR0_CMP1AEN_DISABLED_U32 \ 640 (SI32_PBCFG_A_XBAR0_CMP1AEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP1AEN_SHIFT) 641 // Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0. 642 #define SI32_PBCFG_A_XBAR0_CMP1AEN_ENABLED_VALUE 1 643 #define SI32_PBCFG_A_XBAR0_CMP1AEN_ENABLED_U32 \ 644 (SI32_PBCFG_A_XBAR0_CMP1AEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_CMP1AEN_SHIFT) 645 646 #define SI32_PBCFG_A_XBAR0_TMR0CTEN_MASK 0x00020000 647 #define SI32_PBCFG_A_XBAR0_TMR0CTEN_SHIFT 17 648 // Disable TIMER0 CT on Crossbar 0. 649 #define SI32_PBCFG_A_XBAR0_TMR0CTEN_DISABLED_VALUE 0 650 #define SI32_PBCFG_A_XBAR0_TMR0CTEN_DISABLED_U32 \ 651 (SI32_PBCFG_A_XBAR0_TMR0CTEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR0CTEN_SHIFT) 652 // Enable TIMER0 CT on Crossbar 0. 653 #define SI32_PBCFG_A_XBAR0_TMR0CTEN_ENABLED_VALUE 1 654 #define SI32_PBCFG_A_XBAR0_TMR0CTEN_ENABLED_U32 \ 655 (SI32_PBCFG_A_XBAR0_TMR0CTEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR0CTEN_SHIFT) 656 657 #define SI32_PBCFG_A_XBAR0_TMR0EXEN_MASK 0x00040000 658 #define SI32_PBCFG_A_XBAR0_TMR0EXEN_SHIFT 18 659 // Disable TIMER0 EX on Crossbar 0. 660 #define SI32_PBCFG_A_XBAR0_TMR0EXEN_DISABLED_VALUE 0 661 #define SI32_PBCFG_A_XBAR0_TMR0EXEN_DISABLED_U32 \ 662 (SI32_PBCFG_A_XBAR0_TMR0EXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR0EXEN_SHIFT) 663 // Enable TIMER0 EX on Crossbar 0. 664 #define SI32_PBCFG_A_XBAR0_TMR0EXEN_ENABLED_VALUE 1 665 #define SI32_PBCFG_A_XBAR0_TMR0EXEN_ENABLED_U32 \ 666 (SI32_PBCFG_A_XBAR0_TMR0EXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR0EXEN_SHIFT) 667 668 #define SI32_PBCFG_A_XBAR0_TMR1CTEN_MASK 0x00080000 669 #define SI32_PBCFG_A_XBAR0_TMR1CTEN_SHIFT 19 670 // Disable TIMER1 CT on Crossbar 0. 671 #define SI32_PBCFG_A_XBAR0_TMR1CTEN_DISABLED_VALUE 0 672 #define SI32_PBCFG_A_XBAR0_TMR1CTEN_DISABLED_U32 \ 673 (SI32_PBCFG_A_XBAR0_TMR1CTEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR1CTEN_SHIFT) 674 // Enable TIMER1 CT on Crossbar 0. 675 #define SI32_PBCFG_A_XBAR0_TMR1CTEN_ENABLED_VALUE 1 676 #define SI32_PBCFG_A_XBAR0_TMR1CTEN_ENABLED_U32 \ 677 (SI32_PBCFG_A_XBAR0_TMR1CTEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR1CTEN_SHIFT) 678 679 #define SI32_PBCFG_A_XBAR0_TMR1EXEN_MASK 0x00100000 680 #define SI32_PBCFG_A_XBAR0_TMR1EXEN_SHIFT 20 681 // Disable TIMER1 EX on Crossbar 0. 682 #define SI32_PBCFG_A_XBAR0_TMR1EXEN_DISABLED_VALUE 0 683 #define SI32_PBCFG_A_XBAR0_TMR1EXEN_DISABLED_U32 \ 684 (SI32_PBCFG_A_XBAR0_TMR1EXEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR1EXEN_SHIFT) 685 // Enable TIMER1 EX on Crossbar 0. 686 #define SI32_PBCFG_A_XBAR0_TMR1EXEN_ENABLED_VALUE 1 687 #define SI32_PBCFG_A_XBAR0_TMR1EXEN_ENABLED_U32 \ 688 (SI32_PBCFG_A_XBAR0_TMR1EXEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_TMR1EXEN_SHIFT) 689 690 #define SI32_PBCFG_A_XBAR0_SARADC0TEN_MASK 0x00200000 691 #define SI32_PBCFG_A_XBAR0_SARADC0TEN_SHIFT 21 692 // Disable SARADC0 conversion start trigger on Crossbar 0. 693 #define SI32_PBCFG_A_XBAR0_SARADC0TEN_DISABLED_VALUE 0 694 #define SI32_PBCFG_A_XBAR0_SARADC0TEN_DISABLED_U32 \ 695 (SI32_PBCFG_A_XBAR0_SARADC0TEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_SARADC0TEN_SHIFT) 696 // Enable SARADC0 conversion start trigger on Crossbar 0. 697 #define SI32_PBCFG_A_XBAR0_SARADC0TEN_ENABLED_VALUE 1 698 #define SI32_PBCFG_A_XBAR0_SARADC0TEN_ENABLED_U32 \ 699 (SI32_PBCFG_A_XBAR0_SARADC0TEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_SARADC0TEN_SHIFT) 700 701 #define SI32_PBCFG_A_XBAR0_AHBEN_MASK 0x00400000 702 #define SI32_PBCFG_A_XBAR0_AHBEN_SHIFT 22 703 // Disable the AHB Clock / 16 output on Crossbar 0. 704 #define SI32_PBCFG_A_XBAR0_AHBEN_DISABLED_VALUE 0 705 #define SI32_PBCFG_A_XBAR0_AHBEN_DISABLED_U32 \ 706 (SI32_PBCFG_A_XBAR0_AHBEN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_AHBEN_SHIFT) 707 // Enable the AHB Clock / 16 output on Crossbar 0. 708 #define SI32_PBCFG_A_XBAR0_AHBEN_ENABLED_VALUE 1 709 #define SI32_PBCFG_A_XBAR0_AHBEN_ENABLED_U32 \ 710 (SI32_PBCFG_A_XBAR0_AHBEN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_AHBEN_SHIFT) 711 712 #define SI32_PBCFG_A_XBAR0_XBAR0EN_MASK 0x80000000 713 #define SI32_PBCFG_A_XBAR0_XBAR0EN_SHIFT 31 714 // Disable Crossbar 0. 715 #define SI32_PBCFG_A_XBAR0_XBAR0EN_DISABLED_VALUE 0U 716 #define SI32_PBCFG_A_XBAR0_XBAR0EN_DISABLED_U32 \ 717 (SI32_PBCFG_A_XBAR0_XBAR0EN_DISABLED_VALUE << SI32_PBCFG_A_XBAR0_XBAR0EN_SHIFT) 718 // Enable Crossbar 0. 719 #define SI32_PBCFG_A_XBAR0_XBAR0EN_ENABLED_VALUE 1U 720 #define SI32_PBCFG_A_XBAR0_XBAR0EN_ENABLED_U32 \ 721 (SI32_PBCFG_A_XBAR0_XBAR0EN_ENABLED_VALUE << SI32_PBCFG_A_XBAR0_XBAR0EN_SHIFT) 722 723 724 725 struct SI32_PBCFG_A_PBKEY_Struct 726 { 727 union 728 { 729 struct 730 { 731 // Port Bank Key 732 volatile uint8_t KEY; 733 uint32_t reserved0: 24; 734 }; 735 volatile uint32_t U32; 736 }; 737 }; 738 739 #define SI32_PBCFG_A_PBKEY_KEY_MASK 0x000000FF 740 #define SI32_PBCFG_A_PBKEY_KEY_SHIFT 0 741 // Port Bank registers are locked and no valid values have been written to PBKEY. 742 #define SI32_PBCFG_A_PBKEY_KEY_LOCKED_VALUE 0 743 #define SI32_PBCFG_A_PBKEY_KEY_LOCKED_U32 \ 744 (SI32_PBCFG_A_PBKEY_KEY_LOCKED_VALUE << SI32_PBCFG_A_PBKEY_KEY_SHIFT) 745 // Port Bank registers are locked and the first valid value (0xA5) has been written 746 // to PBKEY. 747 #define SI32_PBCFG_A_PBKEY_KEY_INTERMEDIATE_VALUE 1 748 #define SI32_PBCFG_A_PBKEY_KEY_INTERMEDIATE_U32 \ 749 (SI32_PBCFG_A_PBKEY_KEY_INTERMEDIATE_VALUE << SI32_PBCFG_A_PBKEY_KEY_SHIFT) 750 // Port Bank registers are unlocked. Any subsequent writes to the Port Bank 751 // registers or PBKEY will lock the interface. 752 #define SI32_PBCFG_A_PBKEY_KEY_UNLOCKED_VALUE 2 753 #define SI32_PBCFG_A_PBKEY_KEY_UNLOCKED_U32 \ 754 (SI32_PBCFG_A_PBKEY_KEY_UNLOCKED_VALUE << SI32_PBCFG_A_PBKEY_KEY_SHIFT) 755 756 757 758 typedef struct SI32_PBCFG_A_Struct 759 { 760 struct SI32_PBCFG_A_CONTROL0_Struct CONTROL0 ; // Base Address + 0x0 761 volatile uint32_t CONTROL0_SET; 762 volatile uint32_t CONTROL0_CLR; 763 uint32_t reserved0; 764 struct SI32_PBCFG_A_CONTROL1_Struct CONTROL1 ; // Base Address + 0x10 765 volatile uint32_t CONTROL1_SET; 766 volatile uint32_t CONTROL1_CLR; 767 uint32_t reserved1; 768 struct SI32_PBCFG_A_XBAR0_Struct XBAR0 ; // Base Address + 0x20 769 volatile uint32_t XBAR0_SET; 770 volatile uint32_t XBAR0_CLR; 771 uint32_t reserved2; 772 struct SI32_PBCFG_A_PBKEY_Struct PBKEY ; // Base Address + 0x30 773 uint32_t reserved3; 774 uint32_t reserved4; 775 uint32_t reserved5; 776 } SI32_PBCFG_A_Type; 777 778 #ifdef __cplusplus 779 } 780 #endif 781 782 #endif // __SI32_PBCFG_A_REGISTERS_H__ 783 784 //-eof-------------------------------------------------------------------------- 785 786
