1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_LPTIMER_A_REGISTERS_H__ 27 #define __SI32_LPTIMER_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_LPTIMER_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Count Mode 42 volatile uint32_t CMD: 2; 43 uint32_t reserved0: 2; 44 // External Trigger Source Select 45 volatile uint32_t EXTSEL: 4; 46 // Timer Set 47 volatile uint32_t TMRSET: 1; 48 // Timer Capture 49 volatile uint32_t TMRCAP: 1; 50 // Timer Comparator Set 51 volatile uint32_t CMPSET: 1; 52 // Timer Comparator Capture 53 volatile uint32_t CMPCAP: 1; 54 uint32_t reserved1: 4; 55 // Timer Overflow Interrupt Enable 56 volatile uint32_t OVFIEN: 1; 57 // Timer Compare Event Interrupt Enable 58 volatile uint32_t CMPIEN: 1; 59 // Timer Overflow Toggle Mode 60 volatile uint32_t OVFTMD: 1; 61 // Timer Compare Event Toggle Mode 62 volatile uint32_t CMPTMD: 1; 63 uint32_t reserved2: 4; 64 // Timer Compare Event Reset Enable 65 volatile uint32_t CMPRSTEN: 1; 66 uint32_t reserved3: 5; 67 // Low Power Timer Debug Mode 68 volatile uint32_t DBGMD: 1; 69 // Timer Run Control and Compare Threshold Enable 70 volatile uint32_t RUN: 1; 71 }; 72 volatile uint32_t U32; 73 }; 74 }; 75 76 #define SI32_LPTIMER_A_CONTROL_CMD_MASK 0x00000003 77 #define SI32_LPTIMER_A_CONTROL_CMD_SHIFT 0 78 // The timer is free running mode on the RTC0 timer clock (RTC0TCLK). 79 #define SI32_LPTIMER_A_CONTROL_CMD_FREE_VALUE 0 80 #define SI32_LPTIMER_A_CONTROL_CMD_FREE_U32 \ 81 (SI32_LPTIMER_A_CONTROL_CMD_FREE_VALUE << SI32_LPTIMER_A_CONTROL_CMD_SHIFT) 82 // The timer is incremented on the rising edges of the selected external trigger 83 // (LPTnTx). 84 #define SI32_LPTIMER_A_CONTROL_CMD_RISING_EDGE_VALUE 1 85 #define SI32_LPTIMER_A_CONTROL_CMD_RISING_EDGE_U32 \ 86 (SI32_LPTIMER_A_CONTROL_CMD_RISING_EDGE_VALUE << SI32_LPTIMER_A_CONTROL_CMD_SHIFT) 87 // The timer is incremented on the falling edges of the selected external trigger 88 // (LPTnTx). 89 #define SI32_LPTIMER_A_CONTROL_CMD_FALLING_EDGE_VALUE 2 90 #define SI32_LPTIMER_A_CONTROL_CMD_FALLING_EDGE_U32 \ 91 (SI32_LPTIMER_A_CONTROL_CMD_FALLING_EDGE_VALUE << SI32_LPTIMER_A_CONTROL_CMD_SHIFT) 92 // The timer is incremented on both edges of the selected external trigger 93 // (LPTnTx). 94 #define SI32_LPTIMER_A_CONTROL_CMD_ANY_EDGE_VALUE 3 95 #define SI32_LPTIMER_A_CONTROL_CMD_ANY_EDGE_U32 \ 96 (SI32_LPTIMER_A_CONTROL_CMD_ANY_EDGE_VALUE << SI32_LPTIMER_A_CONTROL_CMD_SHIFT) 97 98 #define SI32_LPTIMER_A_CONTROL_EXTSEL_MASK 0x000000F0 99 #define SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT 4 100 // Select external trigger LPTnT0. 101 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT0_VALUE 0 102 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT0_U32 \ 103 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT0_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 104 // Select external trigger LPTnT1. 105 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT1_VALUE 1 106 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT1_U32 \ 107 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT1_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 108 // Select external trigger LPTnT2. 109 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT2_VALUE 2 110 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT2_U32 \ 111 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT2_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 112 // Select external trigger LPTnT3. 113 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT3_VALUE 3 114 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT3_U32 \ 115 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT3_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 116 // Select external trigger LPTnT4. 117 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT4_VALUE 4 118 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT4_U32 \ 119 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT4_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 120 // Select external trigger LPTnT5. 121 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT5_VALUE 5 122 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT5_U32 \ 123 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT5_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 124 // Select external trigger LPTnT6. 125 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT6_VALUE 6 126 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT6_U32 \ 127 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT6_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 128 // Select external trigger LPTnT7. 129 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT7_VALUE 7 130 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT7_U32 \ 131 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT7_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 132 // Select external trigger LPTnT8. 133 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT8_VALUE 8 134 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT8_U32 \ 135 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT8_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 136 // Select external trigger LPTnT9. 137 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT9_VALUE 9 138 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT9_U32 \ 139 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT9_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 140 // Select external trigger LPTnT10. 141 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT10_VALUE 10 142 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT10_U32 \ 143 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT10_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 144 // Select external trigger LPTnT11. 145 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT11_VALUE 11 146 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT11_U32 \ 147 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT11_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 148 // Select external trigger LPTnT12. 149 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT12_VALUE 12 150 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT12_U32 \ 151 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT12_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 152 // Select external trigger LPTnT13. 153 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT13_VALUE 13 154 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT13_U32 \ 155 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT13_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 156 // Select external trigger LPTnT14. 157 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT14_VALUE 14 158 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT14_U32 \ 159 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT14_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 160 // Select external trigger LPTnT15. 161 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT15_VALUE 15 162 #define SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT15_U32 \ 163 (SI32_LPTIMER_A_CONTROL_EXTSEL_LPTNT15_VALUE << SI32_LPTIMER_A_CONTROL_EXTSEL_SHIFT) 164 165 #define SI32_LPTIMER_A_CONTROL_TMRSET_MASK 0x00000100 166 #define SI32_LPTIMER_A_CONTROL_TMRSET_SHIFT 8 167 // Writing a 1 to TMRSET initiates a copy of the value from the DATA register into 168 // the internal timer register. This field is automatically cleared by hardware 169 // when the copy is complete and does not need to be cleared by software. 170 #define SI32_LPTIMER_A_CONTROL_TMRSET_SET_VALUE 1 171 #define SI32_LPTIMER_A_CONTROL_TMRSET_SET_U32 \ 172 (SI32_LPTIMER_A_CONTROL_TMRSET_SET_VALUE << SI32_LPTIMER_A_CONTROL_TMRSET_SHIFT) 173 174 #define SI32_LPTIMER_A_CONTROL_TMRCAP_MASK 0x00000200 175 #define SI32_LPTIMER_A_CONTROL_TMRCAP_SHIFT 9 176 // Writing a 1 to TMRCAP initiates a read of internal timer register into the DATA 177 // register. This field is automatically cleared by hardware when the operation 178 // completes and does not need to be cleared by software. 179 #define SI32_LPTIMER_A_CONTROL_TMRCAP_SET_VALUE 1 180 #define SI32_LPTIMER_A_CONTROL_TMRCAP_SET_U32 \ 181 (SI32_LPTIMER_A_CONTROL_TMRCAP_SET_VALUE << SI32_LPTIMER_A_CONTROL_TMRCAP_SHIFT) 182 183 #define SI32_LPTIMER_A_CONTROL_CMPSET_MASK 0x00000400 184 #define SI32_LPTIMER_A_CONTROL_CMPSET_SHIFT 10 185 // Writing a 1 to CMPSET initiates a copy of the value in DATA into the internal 186 // timer comparator register. This field is automatically cleared by hardware when 187 // the copy is complete and does not need to be cleared by software. 188 #define SI32_LPTIMER_A_CONTROL_CMPSET_SET_VALUE 1 189 #define SI32_LPTIMER_A_CONTROL_CMPSET_SET_U32 \ 190 (SI32_LPTIMER_A_CONTROL_CMPSET_SET_VALUE << SI32_LPTIMER_A_CONTROL_CMPSET_SHIFT) 191 192 #define SI32_LPTIMER_A_CONTROL_CMPCAP_MASK 0x00000800 193 #define SI32_LPTIMER_A_CONTROL_CMPCAP_SHIFT 11 194 // Writing a 1 to CMPCAP initiates a read of the internal comparator register into 195 // the DATA register. This field is automatically cleared by hardware when the 196 // operation completes and does not need to be cleared by software. 197 #define SI32_LPTIMER_A_CONTROL_CMPCAP_SET_VALUE 1 198 #define SI32_LPTIMER_A_CONTROL_CMPCAP_SET_U32 \ 199 (SI32_LPTIMER_A_CONTROL_CMPCAP_SET_VALUE << SI32_LPTIMER_A_CONTROL_CMPCAP_SHIFT) 200 201 #define SI32_LPTIMER_A_CONTROL_OVFIEN_MASK 0x00010000 202 #define SI32_LPTIMER_A_CONTROL_OVFIEN_SHIFT 16 203 // Disable the timer overflow interrupt. 204 #define SI32_LPTIMER_A_CONTROL_OVFIEN_DISABLED_VALUE 0 205 #define SI32_LPTIMER_A_CONTROL_OVFIEN_DISABLED_U32 \ 206 (SI32_LPTIMER_A_CONTROL_OVFIEN_DISABLED_VALUE << SI32_LPTIMER_A_CONTROL_OVFIEN_SHIFT) 207 // Enable the timer overflow interrupt. 208 #define SI32_LPTIMER_A_CONTROL_OVFIEN_ENABLED_VALUE 1 209 #define SI32_LPTIMER_A_CONTROL_OVFIEN_ENABLED_U32 \ 210 (SI32_LPTIMER_A_CONTROL_OVFIEN_ENABLED_VALUE << SI32_LPTIMER_A_CONTROL_OVFIEN_SHIFT) 211 212 #define SI32_LPTIMER_A_CONTROL_CMPIEN_MASK 0x00020000 213 #define SI32_LPTIMER_A_CONTROL_CMPIEN_SHIFT 17 214 // Disable the timer compare event interrupt. 215 #define SI32_LPTIMER_A_CONTROL_CMPIEN_DISABLED_VALUE 0 216 #define SI32_LPTIMER_A_CONTROL_CMPIEN_DISABLED_U32 \ 217 (SI32_LPTIMER_A_CONTROL_CMPIEN_DISABLED_VALUE << SI32_LPTIMER_A_CONTROL_CMPIEN_SHIFT) 218 // Enable the timer compare event interrupt. 219 #define SI32_LPTIMER_A_CONTROL_CMPIEN_ENABLED_VALUE 1 220 #define SI32_LPTIMER_A_CONTROL_CMPIEN_ENABLED_U32 \ 221 (SI32_LPTIMER_A_CONTROL_CMPIEN_ENABLED_VALUE << SI32_LPTIMER_A_CONTROL_CMPIEN_SHIFT) 222 223 #define SI32_LPTIMER_A_CONTROL_OVFTMD_MASK 0x00040000 224 #define SI32_LPTIMER_A_CONTROL_OVFTMD_SHIFT 18 225 // Timer overflows do not toggle the Low Power Timer output. 226 #define SI32_LPTIMER_A_CONTROL_OVFTMD_DISABLED_VALUE 0 227 #define SI32_LPTIMER_A_CONTROL_OVFTMD_DISABLED_U32 \ 228 (SI32_LPTIMER_A_CONTROL_OVFTMD_DISABLED_VALUE << SI32_LPTIMER_A_CONTROL_OVFTMD_SHIFT) 229 // Timer overflows toggle the Low Power Timer output. 230 #define SI32_LPTIMER_A_CONTROL_OVFTMD_ENABLED_VALUE 1 231 #define SI32_LPTIMER_A_CONTROL_OVFTMD_ENABLED_U32 \ 232 (SI32_LPTIMER_A_CONTROL_OVFTMD_ENABLED_VALUE << SI32_LPTIMER_A_CONTROL_OVFTMD_SHIFT) 233 234 #define SI32_LPTIMER_A_CONTROL_CMPTMD_MASK 0x00080000 235 #define SI32_LPTIMER_A_CONTROL_CMPTMD_SHIFT 19 236 // Timer compare events do not toggle the Low Power Timer output. 237 #define SI32_LPTIMER_A_CONTROL_CMPTMD_DISABLED_VALUE 0 238 #define SI32_LPTIMER_A_CONTROL_CMPTMD_DISABLED_U32 \ 239 (SI32_LPTIMER_A_CONTROL_CMPTMD_DISABLED_VALUE << SI32_LPTIMER_A_CONTROL_CMPTMD_SHIFT) 240 // Timer compare events toggle the Low Power Timer output. 241 #define SI32_LPTIMER_A_CONTROL_CMPTMD_ENABLED_VALUE 1 242 #define SI32_LPTIMER_A_CONTROL_CMPTMD_ENABLED_U32 \ 243 (SI32_LPTIMER_A_CONTROL_CMPTMD_ENABLED_VALUE << SI32_LPTIMER_A_CONTROL_CMPTMD_SHIFT) 244 245 #define SI32_LPTIMER_A_CONTROL_CMPRSTEN_MASK 0x01000000 246 #define SI32_LPTIMER_A_CONTROL_CMPRSTEN_SHIFT 24 247 // Timer compare events do not reset the timer. 248 #define SI32_LPTIMER_A_CONTROL_CMPRSTEN_DISABLED_VALUE 0 249 #define SI32_LPTIMER_A_CONTROL_CMPRSTEN_DISABLED_U32 \ 250 (SI32_LPTIMER_A_CONTROL_CMPRSTEN_DISABLED_VALUE << SI32_LPTIMER_A_CONTROL_CMPRSTEN_SHIFT) 251 // Timer compare events reset the timer. 252 #define SI32_LPTIMER_A_CONTROL_CMPRSTEN_ENABLED_VALUE 1 253 #define SI32_LPTIMER_A_CONTROL_CMPRSTEN_ENABLED_U32 \ 254 (SI32_LPTIMER_A_CONTROL_CMPRSTEN_ENABLED_VALUE << SI32_LPTIMER_A_CONTROL_CMPRSTEN_SHIFT) 255 256 #define SI32_LPTIMER_A_CONTROL_DBGMD_MASK 0x40000000 257 #define SI32_LPTIMER_A_CONTROL_DBGMD_SHIFT 30 258 // The Low Power Timer module will continue to operate while the core is halted in 259 // debug mode. 260 #define SI32_LPTIMER_A_CONTROL_DBGMD_RUN_VALUE 0 261 #define SI32_LPTIMER_A_CONTROL_DBGMD_RUN_U32 \ 262 (SI32_LPTIMER_A_CONTROL_DBGMD_RUN_VALUE << SI32_LPTIMER_A_CONTROL_DBGMD_SHIFT) 263 // A debug breakpoint will cause the Low Power Timer module to halt. 264 #define SI32_LPTIMER_A_CONTROL_DBGMD_HALT_VALUE 1 265 #define SI32_LPTIMER_A_CONTROL_DBGMD_HALT_U32 \ 266 (SI32_LPTIMER_A_CONTROL_DBGMD_HALT_VALUE << SI32_LPTIMER_A_CONTROL_DBGMD_SHIFT) 267 268 #define SI32_LPTIMER_A_CONTROL_RUN_MASK 0x80000000 269 #define SI32_LPTIMER_A_CONTROL_RUN_SHIFT 31 270 // Stop the timer and disable the compare threshold. 271 #define SI32_LPTIMER_A_CONTROL_RUN_STOP_VALUE 0U 272 #define SI32_LPTIMER_A_CONTROL_RUN_STOP_U32 \ 273 (SI32_LPTIMER_A_CONTROL_RUN_STOP_VALUE << SI32_LPTIMER_A_CONTROL_RUN_SHIFT) 274 // Start the timer running and enable the compare threshold. 275 #define SI32_LPTIMER_A_CONTROL_RUN_START_VALUE 1U 276 #define SI32_LPTIMER_A_CONTROL_RUN_START_U32 \ 277 (SI32_LPTIMER_A_CONTROL_RUN_START_VALUE << SI32_LPTIMER_A_CONTROL_RUN_SHIFT) 278 279 280 281 struct SI32_LPTIMER_A_DATA_Struct 282 { 283 union 284 { 285 struct 286 { 287 // Timer and Comparator Data 288 volatile uint16_t DATA_BITS; 289 uint32_t reserved0: 16; 290 }; 291 volatile uint32_t U32; 292 }; 293 }; 294 295 #define SI32_LPTIMER_A_DATA_DATA_MASK 0x0000FFFF 296 #define SI32_LPTIMER_A_DATA_DATA_SHIFT 0 297 298 299 300 struct SI32_LPTIMER_A_STATUS_Struct 301 { 302 union 303 { 304 struct 305 { 306 // Timer Overflow Interrupt Flag 307 volatile uint32_t OVFI: 1; 308 // Timer Compare Event Interrupt Flag 309 volatile uint32_t CMPI: 1; 310 uint32_t reserved0: 30; 311 }; 312 volatile uint32_t U32; 313 }; 314 }; 315 316 #define SI32_LPTIMER_A_STATUS_OVFI_MASK 0x00000001 317 #define SI32_LPTIMER_A_STATUS_OVFI_SHIFT 0 318 // A timer overflow has not occurred. 319 #define SI32_LPTIMER_A_STATUS_OVFI_NOT_SET_VALUE 0 320 #define SI32_LPTIMER_A_STATUS_OVFI_NOT_SET_U32 \ 321 (SI32_LPTIMER_A_STATUS_OVFI_NOT_SET_VALUE << SI32_LPTIMER_A_STATUS_OVFI_SHIFT) 322 // A timer overflow occurred. 323 #define SI32_LPTIMER_A_STATUS_OVFI_SET_VALUE 1 324 #define SI32_LPTIMER_A_STATUS_OVFI_SET_U32 \ 325 (SI32_LPTIMER_A_STATUS_OVFI_SET_VALUE << SI32_LPTIMER_A_STATUS_OVFI_SHIFT) 326 327 #define SI32_LPTIMER_A_STATUS_CMPI_MASK 0x00000002 328 #define SI32_LPTIMER_A_STATUS_CMPI_SHIFT 1 329 // A timer compare event has not occurred. 330 #define SI32_LPTIMER_A_STATUS_CMPI_NOT_SET_VALUE 0 331 #define SI32_LPTIMER_A_STATUS_CMPI_NOT_SET_U32 \ 332 (SI32_LPTIMER_A_STATUS_CMPI_NOT_SET_VALUE << SI32_LPTIMER_A_STATUS_CMPI_SHIFT) 333 // A timer compare event occurred. 334 #define SI32_LPTIMER_A_STATUS_CMPI_SET_VALUE 1 335 #define SI32_LPTIMER_A_STATUS_CMPI_SET_U32 \ 336 (SI32_LPTIMER_A_STATUS_CMPI_SET_VALUE << SI32_LPTIMER_A_STATUS_CMPI_SHIFT) 337 338 339 340 typedef struct SI32_LPTIMER_A_Struct 341 { 342 struct SI32_LPTIMER_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 343 volatile uint32_t CONTROL_SET; 344 volatile uint32_t CONTROL_CLR; 345 uint32_t reserved0; 346 struct SI32_LPTIMER_A_DATA_Struct DATA ; // Base Address + 0x10 347 uint32_t reserved1; 348 uint32_t reserved2; 349 uint32_t reserved3; 350 struct SI32_LPTIMER_A_STATUS_Struct STATUS ; // Base Address + 0x20 351 volatile uint32_t STATUS_SET; 352 volatile uint32_t STATUS_CLR; 353 uint32_t reserved4; 354 } SI32_LPTIMER_A_Type; 355 356 #ifdef __cplusplus 357 } 358 #endif 359 360 #endif // __SI32_LPTIMER_A_REGISTERS_H__ 361 362 //-eof-------------------------------------------------------------------------- 363 364
