1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_I2S_A_REGISTERS_H__ 27 #define __SI32_I2S_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_I2S_A_TXCONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // DFS Generator Enable 42 volatile uint32_t FSGEN: 1; 43 // DFS Synchronize Enable 44 volatile uint32_t FSSEN: 1; 45 uint32_t reserved0: 3; 46 // Transmit Delay Disable 47 volatile uint32_t DDIS: 1; 48 // Transmit Initial Phase Delay 49 volatile uint32_t FSDEL: 8; 50 // Transmit Frame Sync Source Select 51 volatile uint32_t FSSRCSEL: 1; 52 // Transmit Data Fill Select 53 volatile uint32_t FILLSEL: 2; 54 // Transmit Data Justification Select 55 volatile uint32_t JSEL: 1; 56 uint32_t reserved1: 2; 57 // Transmit WS Inversion Enable 58 volatile uint32_t FSINVEN: 1; 59 // Transmit SCK Inversion Enable 60 volatile uint32_t SCLKINVEN: 1; 61 // Transmit Order 62 volatile uint32_t ORDER: 1; 63 uint32_t reserved2: 1; 64 // Transmit Mono Bit-Width Select 65 volatile uint32_t MBSEL: 3; 66 uint32_t reserved3: 2; 67 // Transmitter Enable 68 volatile uint32_t TXEN: 1; 69 uint32_t reserved4: 2; 70 }; 71 volatile uint32_t U32; 72 }; 73 }; 74 75 #define SI32_I2S_A_TXCONTROL_FSGEN_MASK 0x00000001 76 #define SI32_I2S_A_TXCONTROL_FSGEN_SHIFT 0 77 // Disable the internal DFS generator. 78 #define SI32_I2S_A_TXCONTROL_FSGEN_DISABLED_VALUE 0 79 #define SI32_I2S_A_TXCONTROL_FSGEN_DISABLED_U32 \ 80 (SI32_I2S_A_TXCONTROL_FSGEN_DISABLED_VALUE << SI32_I2S_A_TXCONTROL_FSGEN_SHIFT) 81 // Enable the internal DFS generator. 82 #define SI32_I2S_A_TXCONTROL_FSGEN_ENABLED_VALUE 1 83 #define SI32_I2S_A_TXCONTROL_FSGEN_ENABLED_U32 \ 84 (SI32_I2S_A_TXCONTROL_FSGEN_ENABLED_VALUE << SI32_I2S_A_TXCONTROL_FSGEN_SHIFT) 85 86 #define SI32_I2S_A_TXCONTROL_FSSEN_MASK 0x00000002 87 #define SI32_I2S_A_TXCONTROL_FSSEN_SHIFT 1 88 // The internal DFS generator starts immediately when FSGEN is set to 1. 89 #define SI32_I2S_A_TXCONTROL_FSSEN_DISABLED_VALUE 0 90 #define SI32_I2S_A_TXCONTROL_FSSEN_DISABLED_U32 \ 91 (SI32_I2S_A_TXCONTROL_FSSEN_DISABLED_VALUE << SI32_I2S_A_TXCONTROL_FSSEN_SHIFT) 92 // Synchronize the rising edge of the internally generated WS signal from the DFS 93 // generator to the rising edge of the external WS input signal. 94 #define SI32_I2S_A_TXCONTROL_FSSEN_ENABLED_VALUE 1 95 #define SI32_I2S_A_TXCONTROL_FSSEN_ENABLED_U32 \ 96 (SI32_I2S_A_TXCONTROL_FSSEN_ENABLED_VALUE << SI32_I2S_A_TXCONTROL_FSSEN_SHIFT) 97 98 #define SI32_I2S_A_TXCONTROL_DDIS_MASK 0x00000020 99 #define SI32_I2S_A_TXCONTROL_DDIS_SHIFT 5 100 // The first data bit is sent on the second or later rising edge of SCK after WS 101 // changes. 102 #define SI32_I2S_A_TXCONTROL_DDIS_INACTIVE_VALUE 0 103 #define SI32_I2S_A_TXCONTROL_DDIS_INACTIVE_U32 \ 104 (SI32_I2S_A_TXCONTROL_DDIS_INACTIVE_VALUE << SI32_I2S_A_TXCONTROL_DDIS_SHIFT) 105 // The first data bit is sent on the first rising edge of SCK after WS changes. 106 #define SI32_I2S_A_TXCONTROL_DDIS_ACTIVE_VALUE 1 107 #define SI32_I2S_A_TXCONTROL_DDIS_ACTIVE_U32 \ 108 (SI32_I2S_A_TXCONTROL_DDIS_ACTIVE_VALUE << SI32_I2S_A_TXCONTROL_DDIS_SHIFT) 109 110 #define SI32_I2S_A_TXCONTROL_FSDEL_MASK 0x00003FC0 111 #define SI32_I2S_A_TXCONTROL_FSDEL_SHIFT 6 112 113 #define SI32_I2S_A_TXCONTROL_FSSRCSEL_MASK 0x00004000 114 #define SI32_I2S_A_TXCONTROL_FSSRCSEL_SHIFT 14 115 // The word select or frame sync is input from the WS pin. 116 #define SI32_I2S_A_TXCONTROL_FSSRCSEL_FSIN_EXT_VALUE 0 117 #define SI32_I2S_A_TXCONTROL_FSSRCSEL_FSIN_EXT_U32 \ 118 (SI32_I2S_A_TXCONTROL_FSSRCSEL_FSIN_EXT_VALUE << SI32_I2S_A_TXCONTROL_FSSRCSEL_SHIFT) 119 // The word select or frame sync is input from the internal DFS generator. 120 #define SI32_I2S_A_TXCONTROL_FSSRCSEL_FSIN_INT_VALUE 1 121 #define SI32_I2S_A_TXCONTROL_FSSRCSEL_FSIN_INT_U32 \ 122 (SI32_I2S_A_TXCONTROL_FSSRCSEL_FSIN_INT_VALUE << SI32_I2S_A_TXCONTROL_FSSRCSEL_SHIFT) 123 124 #define SI32_I2S_A_TXCONTROL_FILLSEL_MASK 0x00018000 125 #define SI32_I2S_A_TXCONTROL_FILLSEL_SHIFT 15 126 // Send zeros during unused bit cycles. 127 #define SI32_I2S_A_TXCONTROL_FILLSEL_ZEROS_VALUE 0 128 #define SI32_I2S_A_TXCONTROL_FILLSEL_ZEROS_U32 \ 129 (SI32_I2S_A_TXCONTROL_FILLSEL_ZEROS_VALUE << SI32_I2S_A_TXCONTROL_FILLSEL_SHIFT) 130 // Send ones during unused bit cycles. 131 #define SI32_I2S_A_TXCONTROL_FILLSEL_ONES_VALUE 1 132 #define SI32_I2S_A_TXCONTROL_FILLSEL_ONES_U32 \ 133 (SI32_I2S_A_TXCONTROL_FILLSEL_ONES_VALUE << SI32_I2S_A_TXCONTROL_FILLSEL_SHIFT) 134 // Send the sign bit of the current sample (MSB-first format) or last sample (LSB- 135 // first format) during unused bit cycles. 136 #define SI32_I2S_A_TXCONTROL_FILLSEL_SIGN_VALUE 2 137 #define SI32_I2S_A_TXCONTROL_FILLSEL_SIGN_U32 \ 138 (SI32_I2S_A_TXCONTROL_FILLSEL_SIGN_VALUE << SI32_I2S_A_TXCONTROL_FILLSEL_SHIFT) 139 // Send pseudo-random data generated by an 8-bit LFSR during unused bit cycles. 140 #define SI32_I2S_A_TXCONTROL_FILLSEL_RANDOM_VALUE 3 141 #define SI32_I2S_A_TXCONTROL_FILLSEL_RANDOM_U32 \ 142 (SI32_I2S_A_TXCONTROL_FILLSEL_RANDOM_VALUE << SI32_I2S_A_TXCONTROL_FILLSEL_SHIFT) 143 144 #define SI32_I2S_A_TXCONTROL_JSEL_MASK 0x00020000 145 #define SI32_I2S_A_TXCONTROL_JSEL_SHIFT 17 146 // Use left-justified or I2S-style formats. 147 #define SI32_I2S_A_TXCONTROL_JSEL_LEFT_VALUE 0 148 #define SI32_I2S_A_TXCONTROL_JSEL_LEFT_U32 \ 149 (SI32_I2S_A_TXCONTROL_JSEL_LEFT_VALUE << SI32_I2S_A_TXCONTROL_JSEL_SHIFT) 150 // Use right-justified format. 151 #define SI32_I2S_A_TXCONTROL_JSEL_RIGHT_VALUE 1 152 #define SI32_I2S_A_TXCONTROL_JSEL_RIGHT_U32 \ 153 (SI32_I2S_A_TXCONTROL_JSEL_RIGHT_VALUE << SI32_I2S_A_TXCONTROL_JSEL_SHIFT) 154 155 #define SI32_I2S_A_TXCONTROL_FSINVEN_MASK 0x00100000 156 #define SI32_I2S_A_TXCONTROL_FSINVEN_SHIFT 20 157 // Don't invert the WS signal. Use this setting for I2S format. 158 #define SI32_I2S_A_TXCONTROL_FSINVEN_DISABLED_VALUE 0 159 #define SI32_I2S_A_TXCONTROL_FSINVEN_DISABLED_U32 \ 160 (SI32_I2S_A_TXCONTROL_FSINVEN_DISABLED_VALUE << SI32_I2S_A_TXCONTROL_FSINVEN_SHIFT) 161 // Invert the WS signal. 162 #define SI32_I2S_A_TXCONTROL_FSINVEN_ENABLED_VALUE 1 163 #define SI32_I2S_A_TXCONTROL_FSINVEN_ENABLED_U32 \ 164 (SI32_I2S_A_TXCONTROL_FSINVEN_ENABLED_VALUE << SI32_I2S_A_TXCONTROL_FSINVEN_SHIFT) 165 166 #define SI32_I2S_A_TXCONTROL_SCLKINVEN_MASK 0x00200000 167 #define SI32_I2S_A_TXCONTROL_SCLKINVEN_SHIFT 21 168 // Do not invert the transmitter bit clock. 169 #define SI32_I2S_A_TXCONTROL_SCLKINVEN_DISABLED_VALUE 0 170 #define SI32_I2S_A_TXCONTROL_SCLKINVEN_DISABLED_U32 \ 171 (SI32_I2S_A_TXCONTROL_SCLKINVEN_DISABLED_VALUE << SI32_I2S_A_TXCONTROL_SCLKINVEN_SHIFT) 172 // Invert the transmitter bit clock. 173 #define SI32_I2S_A_TXCONTROL_SCLKINVEN_ENABLED_VALUE 1 174 #define SI32_I2S_A_TXCONTROL_SCLKINVEN_ENABLED_U32 \ 175 (SI32_I2S_A_TXCONTROL_SCLKINVEN_ENABLED_VALUE << SI32_I2S_A_TXCONTROL_SCLKINVEN_SHIFT) 176 177 #define SI32_I2S_A_TXCONTROL_ORDER_MASK 0x00400000 178 #define SI32_I2S_A_TXCONTROL_ORDER_SHIFT 22 179 // Left sample transmitted first, right sample transmitted second. Use this setting 180 // for I2S format. 181 #define SI32_I2S_A_TXCONTROL_ORDER_LEFT_RIGHT_VALUE 0 182 #define SI32_I2S_A_TXCONTROL_ORDER_LEFT_RIGHT_U32 \ 183 (SI32_I2S_A_TXCONTROL_ORDER_LEFT_RIGHT_VALUE << SI32_I2S_A_TXCONTROL_ORDER_SHIFT) 184 // Right sample transmitted first, left sample transmitted second. 185 #define SI32_I2S_A_TXCONTROL_ORDER_RIGHT_LEFT_VALUE 1 186 #define SI32_I2S_A_TXCONTROL_ORDER_RIGHT_LEFT_U32 \ 187 (SI32_I2S_A_TXCONTROL_ORDER_RIGHT_LEFT_VALUE << SI32_I2S_A_TXCONTROL_ORDER_SHIFT) 188 189 #define SI32_I2S_A_TXCONTROL_MBSEL_MASK 0x07000000 190 #define SI32_I2S_A_TXCONTROL_MBSEL_SHIFT 24 191 // 8 bits are sent per mono sample. 192 #define SI32_I2S_A_TXCONTROL_MBSEL_8BITS_VALUE 0 193 #define SI32_I2S_A_TXCONTROL_MBSEL_8BITS_U32 \ 194 (SI32_I2S_A_TXCONTROL_MBSEL_8BITS_VALUE << SI32_I2S_A_TXCONTROL_MBSEL_SHIFT) 195 // 9 bits are sent per mono sample. 196 #define SI32_I2S_A_TXCONTROL_MBSEL_9BITS_VALUE 1 197 #define SI32_I2S_A_TXCONTROL_MBSEL_9BITS_U32 \ 198 (SI32_I2S_A_TXCONTROL_MBSEL_9BITS_VALUE << SI32_I2S_A_TXCONTROL_MBSEL_SHIFT) 199 // 16 bits are sent per mono sample. 200 #define SI32_I2S_A_TXCONTROL_MBSEL_16BITS_VALUE 2 201 #define SI32_I2S_A_TXCONTROL_MBSEL_16BITS_U32 \ 202 (SI32_I2S_A_TXCONTROL_MBSEL_16BITS_VALUE << SI32_I2S_A_TXCONTROL_MBSEL_SHIFT) 203 // 24 bits are sent per mono sample. 204 #define SI32_I2S_A_TXCONTROL_MBSEL_24BITS_VALUE 3 205 #define SI32_I2S_A_TXCONTROL_MBSEL_24BITS_U32 \ 206 (SI32_I2S_A_TXCONTROL_MBSEL_24BITS_VALUE << SI32_I2S_A_TXCONTROL_MBSEL_SHIFT) 207 // 32 bits are sent per mono sample. 208 #define SI32_I2S_A_TXCONTROL_MBSEL_32BITS_VALUE 4 209 #define SI32_I2S_A_TXCONTROL_MBSEL_32BITS_U32 \ 210 (SI32_I2S_A_TXCONTROL_MBSEL_32BITS_VALUE << SI32_I2S_A_TXCONTROL_MBSEL_SHIFT) 211 212 #define SI32_I2S_A_TXCONTROL_TXEN_MASK 0x20000000 213 #define SI32_I2S_A_TXCONTROL_TXEN_SHIFT 29 214 // Disable the I2S transmitter. 215 #define SI32_I2S_A_TXCONTROL_TXEN_DISABLED_VALUE 0 216 #define SI32_I2S_A_TXCONTROL_TXEN_DISABLED_U32 \ 217 (SI32_I2S_A_TXCONTROL_TXEN_DISABLED_VALUE << SI32_I2S_A_TXCONTROL_TXEN_SHIFT) 218 // Enable the I2S transmitter. 219 #define SI32_I2S_A_TXCONTROL_TXEN_ENABLED_VALUE 1 220 #define SI32_I2S_A_TXCONTROL_TXEN_ENABLED_U32 \ 221 (SI32_I2S_A_TXCONTROL_TXEN_ENABLED_VALUE << SI32_I2S_A_TXCONTROL_TXEN_SHIFT) 222 223 224 225 struct SI32_I2S_A_TXMODE_Struct 226 { 227 union 228 { 229 struct 230 { 231 // Transmit Clock Cycle Select 232 volatile uint32_t CYCLE: 12; 233 // Transmit Start Control 234 volatile uint32_t START: 8; 235 // Transmit Drive Select 236 volatile uint32_t SLOTS: 5; 237 // Transmit Drive Early Disable 238 volatile uint32_t DEDIS: 1; 239 // Transmit Drive Inactive Mode 240 volatile uint32_t DIMD: 1; 241 // Transmit Time Division Multiplexing Enable 242 volatile uint32_t TDMEN: 1; 243 uint32_t reserved0: 4; 244 }; 245 volatile uint32_t U32; 246 }; 247 }; 248 249 #define SI32_I2S_A_TXMODE_CYCLE_MASK 0x00000FFF 250 #define SI32_I2S_A_TXMODE_CYCLE_SHIFT 0 251 252 #define SI32_I2S_A_TXMODE_START_MASK 0x000FF000 253 #define SI32_I2S_A_TXMODE_START_SHIFT 12 254 255 #define SI32_I2S_A_TXMODE_SLOTS_MASK 0x01F00000 256 #define SI32_I2S_A_TXMODE_SLOTS_SHIFT 20 257 258 #define SI32_I2S_A_TXMODE_DEDIS_MASK 0x02000000 259 #define SI32_I2S_A_TXMODE_DEDIS_SHIFT 25 260 // Drive the output during every cycle of the transmitter's assigned slot(s), 261 // including the last clock cycle. 262 #define SI32_I2S_A_TXMODE_DEDIS_INACTIVE_VALUE 0 263 #define SI32_I2S_A_TXMODE_DEDIS_INACTIVE_U32 \ 264 (SI32_I2S_A_TXMODE_DEDIS_INACTIVE_VALUE << SI32_I2S_A_TXMODE_DEDIS_SHIFT) 265 // Drive the output for every cycle of the transmitter's assigned slot(s), except 266 // for the last clock cycle of the last slot. 267 #define SI32_I2S_A_TXMODE_DEDIS_ACTIVE_VALUE 1 268 #define SI32_I2S_A_TXMODE_DEDIS_ACTIVE_U32 \ 269 (SI32_I2S_A_TXMODE_DEDIS_ACTIVE_VALUE << SI32_I2S_A_TXMODE_DEDIS_SHIFT) 270 271 #define SI32_I2S_A_TXMODE_DIMD_MASK 0x04000000 272 #define SI32_I2S_A_TXMODE_DIMD_SHIFT 26 273 // Drive zero on the data output pin during non-active slots. 274 #define SI32_I2S_A_TXMODE_DIMD_ZERO_VALUE 0 275 #define SI32_I2S_A_TXMODE_DIMD_ZERO_U32 \ 276 (SI32_I2S_A_TXMODE_DIMD_ZERO_VALUE << SI32_I2S_A_TXMODE_DIMD_SHIFT) 277 // Don't drive the data output pin. The data output pin is tristated. 278 #define SI32_I2S_A_TXMODE_DIMD_HIGH_Z_VALUE 1 279 #define SI32_I2S_A_TXMODE_DIMD_HIGH_Z_U32 \ 280 (SI32_I2S_A_TXMODE_DIMD_HIGH_Z_VALUE << SI32_I2S_A_TXMODE_DIMD_SHIFT) 281 282 #define SI32_I2S_A_TXMODE_TDMEN_MASK 0x08000000 283 #define SI32_I2S_A_TXMODE_TDMEN_SHIFT 27 284 // Disable the time division multiplexing (TDM) feature. 285 #define SI32_I2S_A_TXMODE_TDMEN_DISABLED_VALUE 0 286 #define SI32_I2S_A_TXMODE_TDMEN_DISABLED_U32 \ 287 (SI32_I2S_A_TXMODE_TDMEN_DISABLED_VALUE << SI32_I2S_A_TXMODE_TDMEN_SHIFT) 288 // Enable the time division multiplexing (TDM) feature. 289 #define SI32_I2S_A_TXMODE_TDMEN_ENABLED_VALUE 1 290 #define SI32_I2S_A_TXMODE_TDMEN_ENABLED_U32 \ 291 (SI32_I2S_A_TXMODE_TDMEN_ENABLED_VALUE << SI32_I2S_A_TXMODE_TDMEN_SHIFT) 292 293 294 295 struct SI32_I2S_A_FSDUTY_Struct 296 { 297 union 298 { 299 struct 300 { 301 // Frame Sync Low Time 302 volatile uint16_t FSLOW; 303 // Frame Sync High Time 304 volatile uint16_t FSHIGH; 305 }; 306 volatile uint32_t U32; 307 }; 308 }; 309 310 #define SI32_I2S_A_FSDUTY_FSLOW_MASK 0x0000FFFF 311 #define SI32_I2S_A_FSDUTY_FSLOW_SHIFT 0 312 313 #define SI32_I2S_A_FSDUTY_FSHIGH_MASK 0xFFFF0000 314 #define SI32_I2S_A_FSDUTY_FSHIGH_SHIFT 16 315 316 317 318 struct SI32_I2S_A_RXCONTROL_Struct 319 { 320 union 321 { 322 struct 323 { 324 // Receive Initial Phase Delay 325 volatile uint8_t FSDEL; 326 // Receive Data Justification 327 volatile uint32_t JSEL: 1; 328 // Receive Delay Disable 329 volatile uint32_t DDIS: 1; 330 uint32_t reserved0: 1; 331 // Receive WS Inversion Enable 332 volatile uint32_t FSINVEN: 1; 333 // Receive SCK Inversion Enable 334 volatile uint32_t SCLKINVEN: 1; 335 // Receive Order 336 volatile uint32_t ORDER: 1; 337 uint32_t reserved1: 1; 338 // Receive Mono Bit-Width Select 339 volatile uint32_t MBSEL: 3; 340 uint32_t reserved2: 2; 341 // Receive Frame Sync Source Select 342 volatile uint32_t FSSRCSEL: 1; 343 // Receive Enable 344 volatile uint32_t RXEN: 1; 345 uint32_t reserved3: 10; 346 }; 347 volatile uint32_t U32; 348 }; 349 }; 350 351 #define SI32_I2S_A_RXCONTROL_FSDEL_MASK 0x000000FF 352 #define SI32_I2S_A_RXCONTROL_FSDEL_SHIFT 0 353 354 #define SI32_I2S_A_RXCONTROL_JSEL_MASK 0x00000100 355 #define SI32_I2S_A_RXCONTROL_JSEL_SHIFT 8 356 // Use left-justified or I2S-style formats. 357 #define SI32_I2S_A_RXCONTROL_JSEL_LEFT_VALUE 0 358 #define SI32_I2S_A_RXCONTROL_JSEL_LEFT_U32 \ 359 (SI32_I2S_A_RXCONTROL_JSEL_LEFT_VALUE << SI32_I2S_A_RXCONTROL_JSEL_SHIFT) 360 // Use right-justified format. 361 #define SI32_I2S_A_RXCONTROL_JSEL_RIGHT_VALUE 1 362 #define SI32_I2S_A_RXCONTROL_JSEL_RIGHT_U32 \ 363 (SI32_I2S_A_RXCONTROL_JSEL_RIGHT_VALUE << SI32_I2S_A_RXCONTROL_JSEL_SHIFT) 364 365 #define SI32_I2S_A_RXCONTROL_DDIS_MASK 0x00000200 366 #define SI32_I2S_A_RXCONTROL_DDIS_SHIFT 9 367 // The first data bit is captured on the second or later rising edge of SCK after 368 // WS changes. 369 #define SI32_I2S_A_RXCONTROL_DDIS_INACTIVE_VALUE 0 370 #define SI32_I2S_A_RXCONTROL_DDIS_INACTIVE_U32 \ 371 (SI32_I2S_A_RXCONTROL_DDIS_INACTIVE_VALUE << SI32_I2S_A_RXCONTROL_DDIS_SHIFT) 372 // The first data bit is captured by the receiver on the first rising edge of SCK 373 // after WS changes. 374 #define SI32_I2S_A_RXCONTROL_DDIS_ACTIVE_VALUE 1 375 #define SI32_I2S_A_RXCONTROL_DDIS_ACTIVE_U32 \ 376 (SI32_I2S_A_RXCONTROL_DDIS_ACTIVE_VALUE << SI32_I2S_A_RXCONTROL_DDIS_SHIFT) 377 378 #define SI32_I2S_A_RXCONTROL_FSINVEN_MASK 0x00000800 379 #define SI32_I2S_A_RXCONTROL_FSINVEN_SHIFT 11 380 // Don't invert the WS signal. Use this setting for I2S format. 381 #define SI32_I2S_A_RXCONTROL_FSINVEN_DISABLED_VALUE 0 382 #define SI32_I2S_A_RXCONTROL_FSINVEN_DISABLED_U32 \ 383 (SI32_I2S_A_RXCONTROL_FSINVEN_DISABLED_VALUE << SI32_I2S_A_RXCONTROL_FSINVEN_SHIFT) 384 // Invert the WS signal. 385 #define SI32_I2S_A_RXCONTROL_FSINVEN_ENABLED_VALUE 1 386 #define SI32_I2S_A_RXCONTROL_FSINVEN_ENABLED_U32 \ 387 (SI32_I2S_A_RXCONTROL_FSINVEN_ENABLED_VALUE << SI32_I2S_A_RXCONTROL_FSINVEN_SHIFT) 388 389 #define SI32_I2S_A_RXCONTROL_SCLKINVEN_MASK 0x00001000 390 #define SI32_I2S_A_RXCONTROL_SCLKINVEN_SHIFT 12 391 // Do not invert the receiver bit clock. 392 #define SI32_I2S_A_RXCONTROL_SCLKINVEN_DISABLED_VALUE 0 393 #define SI32_I2S_A_RXCONTROL_SCLKINVEN_DISABLED_U32 \ 394 (SI32_I2S_A_RXCONTROL_SCLKINVEN_DISABLED_VALUE << SI32_I2S_A_RXCONTROL_SCLKINVEN_SHIFT) 395 // Invert the receiver bit clock. 396 #define SI32_I2S_A_RXCONTROL_SCLKINVEN_ENABLED_VALUE 1 397 #define SI32_I2S_A_RXCONTROL_SCLKINVEN_ENABLED_U32 \ 398 (SI32_I2S_A_RXCONTROL_SCLKINVEN_ENABLED_VALUE << SI32_I2S_A_RXCONTROL_SCLKINVEN_SHIFT) 399 400 #define SI32_I2S_A_RXCONTROL_ORDER_MASK 0x00002000 401 #define SI32_I2S_A_RXCONTROL_ORDER_SHIFT 13 402 // Left sample received first, right sample received second. Use this setting for 403 // I2S format. 404 #define SI32_I2S_A_RXCONTROL_ORDER_LEFT_RIGHT_VALUE 0 405 #define SI32_I2S_A_RXCONTROL_ORDER_LEFT_RIGHT_U32 \ 406 (SI32_I2S_A_RXCONTROL_ORDER_LEFT_RIGHT_VALUE << SI32_I2S_A_RXCONTROL_ORDER_SHIFT) 407 // Right sample received first, left sample received second. 408 #define SI32_I2S_A_RXCONTROL_ORDER_RIGHT_LEFT_VALUE 1 409 #define SI32_I2S_A_RXCONTROL_ORDER_RIGHT_LEFT_U32 \ 410 (SI32_I2S_A_RXCONTROL_ORDER_RIGHT_LEFT_VALUE << SI32_I2S_A_RXCONTROL_ORDER_SHIFT) 411 412 #define SI32_I2S_A_RXCONTROL_MBSEL_MASK 0x00038000 413 #define SI32_I2S_A_RXCONTROL_MBSEL_SHIFT 15 414 // 8 bits are received per mono sample. 415 #define SI32_I2S_A_RXCONTROL_MBSEL_8BITS_VALUE 0 416 #define SI32_I2S_A_RXCONTROL_MBSEL_8BITS_U32 \ 417 (SI32_I2S_A_RXCONTROL_MBSEL_8BITS_VALUE << SI32_I2S_A_RXCONTROL_MBSEL_SHIFT) 418 // 9 bits are received per mono sample. 419 #define SI32_I2S_A_RXCONTROL_MBSEL_9BITS_VALUE 1 420 #define SI32_I2S_A_RXCONTROL_MBSEL_9BITS_U32 \ 421 (SI32_I2S_A_RXCONTROL_MBSEL_9BITS_VALUE << SI32_I2S_A_RXCONTROL_MBSEL_SHIFT) 422 // 16 bits are received per mono sample. 423 #define SI32_I2S_A_RXCONTROL_MBSEL_16BITS_VALUE 2 424 #define SI32_I2S_A_RXCONTROL_MBSEL_16BITS_U32 \ 425 (SI32_I2S_A_RXCONTROL_MBSEL_16BITS_VALUE << SI32_I2S_A_RXCONTROL_MBSEL_SHIFT) 426 // 24 bits are received per mono sample. 427 #define SI32_I2S_A_RXCONTROL_MBSEL_24BITS_VALUE 3 428 #define SI32_I2S_A_RXCONTROL_MBSEL_24BITS_U32 \ 429 (SI32_I2S_A_RXCONTROL_MBSEL_24BITS_VALUE << SI32_I2S_A_RXCONTROL_MBSEL_SHIFT) 430 // 32 bits are received per mono sample. 431 #define SI32_I2S_A_RXCONTROL_MBSEL_32BITS_VALUE 4 432 #define SI32_I2S_A_RXCONTROL_MBSEL_32BITS_U32 \ 433 (SI32_I2S_A_RXCONTROL_MBSEL_32BITS_VALUE << SI32_I2S_A_RXCONTROL_MBSEL_SHIFT) 434 435 #define SI32_I2S_A_RXCONTROL_FSSRCSEL_MASK 0x00100000 436 #define SI32_I2S_A_RXCONTROL_FSSRCSEL_SHIFT 20 437 // The word select or frame sync is input from the WS pin. 438 #define SI32_I2S_A_RXCONTROL_FSSRCSEL_FSIN_EXT_VALUE 0 439 #define SI32_I2S_A_RXCONTROL_FSSRCSEL_FSIN_EXT_U32 \ 440 (SI32_I2S_A_RXCONTROL_FSSRCSEL_FSIN_EXT_VALUE << SI32_I2S_A_RXCONTROL_FSSRCSEL_SHIFT) 441 // The word select or frame sync is input from the internal DFS generator. 442 #define SI32_I2S_A_RXCONTROL_FSSRCSEL_FSIN_INT_VALUE 1 443 #define SI32_I2S_A_RXCONTROL_FSSRCSEL_FSIN_INT_U32 \ 444 (SI32_I2S_A_RXCONTROL_FSSRCSEL_FSIN_INT_VALUE << SI32_I2S_A_RXCONTROL_FSSRCSEL_SHIFT) 445 446 #define SI32_I2S_A_RXCONTROL_RXEN_MASK 0x00200000 447 #define SI32_I2S_A_RXCONTROL_RXEN_SHIFT 21 448 // Disable the I2S receiver. 449 #define SI32_I2S_A_RXCONTROL_RXEN_DISABLED_VALUE 0 450 #define SI32_I2S_A_RXCONTROL_RXEN_DISABLED_U32 \ 451 (SI32_I2S_A_RXCONTROL_RXEN_DISABLED_VALUE << SI32_I2S_A_RXCONTROL_RXEN_SHIFT) 452 // Enable the I2S receiver. 453 #define SI32_I2S_A_RXCONTROL_RXEN_ENABLED_VALUE 1 454 #define SI32_I2S_A_RXCONTROL_RXEN_ENABLED_U32 \ 455 (SI32_I2S_A_RXCONTROL_RXEN_ENABLED_VALUE << SI32_I2S_A_RXCONTROL_RXEN_SHIFT) 456 457 458 459 struct SI32_I2S_A_RXMODE_Struct 460 { 461 union 462 { 463 struct 464 { 465 // Receive Clock Cycle Select 466 volatile uint32_t CYCLE: 12; 467 // Receive Start Control 468 volatile uint32_t START: 8; 469 // Receive Drive Select 470 volatile uint32_t SLOTS: 6; 471 uint32_t reserved0: 1; 472 // Receive Time Division Multiplexing Enable 473 volatile uint32_t TDMEN: 1; 474 uint32_t reserved1: 4; 475 }; 476 volatile uint32_t U32; 477 }; 478 }; 479 480 #define SI32_I2S_A_RXMODE_CYCLE_MASK 0x00000FFF 481 #define SI32_I2S_A_RXMODE_CYCLE_SHIFT 0 482 483 #define SI32_I2S_A_RXMODE_START_MASK 0x000FF000 484 #define SI32_I2S_A_RXMODE_START_SHIFT 12 485 486 #define SI32_I2S_A_RXMODE_SLOTS_MASK 0x03F00000 487 #define SI32_I2S_A_RXMODE_SLOTS_SHIFT 20 488 489 #define SI32_I2S_A_RXMODE_TDMEN_MASK 0x08000000 490 #define SI32_I2S_A_RXMODE_TDMEN_SHIFT 27 491 // Disable the time division multiplexing (TDM) feature. 492 #define SI32_I2S_A_RXMODE_TDMEN_DISABLED_VALUE 0 493 #define SI32_I2S_A_RXMODE_TDMEN_DISABLED_U32 \ 494 (SI32_I2S_A_RXMODE_TDMEN_DISABLED_VALUE << SI32_I2S_A_RXMODE_TDMEN_SHIFT) 495 // Enable the time division multiplexing (TDM) feature. 496 #define SI32_I2S_A_RXMODE_TDMEN_ENABLED_VALUE 1 497 #define SI32_I2S_A_RXMODE_TDMEN_ENABLED_U32 \ 498 (SI32_I2S_A_RXMODE_TDMEN_ENABLED_VALUE << SI32_I2S_A_RXMODE_TDMEN_SHIFT) 499 500 501 502 struct SI32_I2S_A_CLKCONTROL_Struct 503 { 504 union 505 { 506 struct 507 { 508 // Clock Divider Integer Value 509 volatile uint32_t INTDIV: 10; 510 // Clock Divider Fractional Value 511 volatile uint32_t FRACDIV: 8; 512 // Duty Cycle Adjustment Mode 513 volatile uint32_t DUTYMD: 1; 514 // Clock Divider Update 515 volatile uint32_t CLKUPD: 1; 516 // Clock Divider Enable 517 volatile uint32_t DIVEN: 1; 518 // Transmit Clock Select 519 volatile uint32_t TXCLKSEL: 1; 520 // Receive Clock Select 521 volatile uint32_t RXCLKSEL: 1; 522 // I2S Module Reset 523 volatile uint32_t RESET: 1; 524 // Receive Clock Enable 525 volatile uint32_t RXCLKEN: 1; 526 // Transmit Clock Enable 527 volatile uint32_t TXCLKEN: 1; 528 // Receive SCK Mode 529 volatile uint32_t RXSCLKMD: 1; 530 // Transmit SCK Mode 531 volatile uint32_t TXSCLKMD: 1; 532 uint32_t reserved0: 4; 533 }; 534 volatile uint32_t U32; 535 }; 536 }; 537 538 #define SI32_I2S_A_CLKCONTROL_INTDIV_MASK 0x000003FF 539 #define SI32_I2S_A_CLKCONTROL_INTDIV_SHIFT 0 540 541 #define SI32_I2S_A_CLKCONTROL_FRACDIV_MASK 0x0003FC00 542 #define SI32_I2S_A_CLKCONTROL_FRACDIV_SHIFT 10 543 544 #define SI32_I2S_A_CLKCONTROL_DUTYMD_MASK 0x00040000 545 #define SI32_I2S_A_CLKCONTROL_DUTYMD_SHIFT 18 546 // When the division is fractional, the clock high time will be greater than 50% 547 // (by half of the source clock period). 548 #define SI32_I2S_A_CLKCONTROL_DUTYMD_MORE_VALUE 0 549 #define SI32_I2S_A_CLKCONTROL_DUTYMD_MORE_U32 \ 550 (SI32_I2S_A_CLKCONTROL_DUTYMD_MORE_VALUE << SI32_I2S_A_CLKCONTROL_DUTYMD_SHIFT) 551 // When the division is fractional, the clock low time will be greater than 50% (by 552 // half of the source clock period). 553 #define SI32_I2S_A_CLKCONTROL_DUTYMD_LESS_VALUE 1 554 #define SI32_I2S_A_CLKCONTROL_DUTYMD_LESS_U32 \ 555 (SI32_I2S_A_CLKCONTROL_DUTYMD_LESS_VALUE << SI32_I2S_A_CLKCONTROL_DUTYMD_SHIFT) 556 557 #define SI32_I2S_A_CLKCONTROL_CLKUPD_MASK 0x00080000 558 #define SI32_I2S_A_CLKCONTROL_CLKUPD_SHIFT 19 559 // Update the clock divider with new values of INTDIV, FRACDIV, and DIVEN. 560 #define SI32_I2S_A_CLKCONTROL_CLKUPD_UPDATE_VALUE 1 561 #define SI32_I2S_A_CLKCONTROL_CLKUPD_UPDATE_U32 \ 562 (SI32_I2S_A_CLKCONTROL_CLKUPD_UPDATE_VALUE << SI32_I2S_A_CLKCONTROL_CLKUPD_SHIFT) 563 564 #define SI32_I2S_A_CLKCONTROL_DIVEN_MASK 0x00100000 565 #define SI32_I2S_A_CLKCONTROL_DIVEN_SHIFT 20 566 // Disable the clock divider. 567 #define SI32_I2S_A_CLKCONTROL_DIVEN_DISABLED_VALUE 0 568 #define SI32_I2S_A_CLKCONTROL_DIVEN_DISABLED_U32 \ 569 (SI32_I2S_A_CLKCONTROL_DIVEN_DISABLED_VALUE << SI32_I2S_A_CLKCONTROL_DIVEN_SHIFT) 570 // Enable the clock divider. 571 #define SI32_I2S_A_CLKCONTROL_DIVEN_ENABLED_VALUE 1 572 #define SI32_I2S_A_CLKCONTROL_DIVEN_ENABLED_U32 \ 573 (SI32_I2S_A_CLKCONTROL_DIVEN_ENABLED_VALUE << SI32_I2S_A_CLKCONTROL_DIVEN_SHIFT) 574 575 #define SI32_I2S_A_CLKCONTROL_TXCLKSEL_MASK 0x00200000 576 #define SI32_I2S_A_CLKCONTROL_TXCLKSEL_SHIFT 21 577 // The I2S transmitter is clocked from the internal clock divider. 578 #define SI32_I2S_A_CLKCONTROL_TXCLKSEL_INTERNAL_VALUE 0 579 #define SI32_I2S_A_CLKCONTROL_TXCLKSEL_INTERNAL_U32 \ 580 (SI32_I2S_A_CLKCONTROL_TXCLKSEL_INTERNAL_VALUE << SI32_I2S_A_CLKCONTROL_TXCLKSEL_SHIFT) 581 // The I2S transmitter is clocked from the SCK pin. 582 #define SI32_I2S_A_CLKCONTROL_TXCLKSEL_EXTERNAL_VALUE 1 583 #define SI32_I2S_A_CLKCONTROL_TXCLKSEL_EXTERNAL_U32 \ 584 (SI32_I2S_A_CLKCONTROL_TXCLKSEL_EXTERNAL_VALUE << SI32_I2S_A_CLKCONTROL_TXCLKSEL_SHIFT) 585 586 #define SI32_I2S_A_CLKCONTROL_RXCLKSEL_MASK 0x00400000 587 #define SI32_I2S_A_CLKCONTROL_RXCLKSEL_SHIFT 22 588 // The I2S receiver is clocked from the internal clock divider. 589 #define SI32_I2S_A_CLKCONTROL_RXCLKSEL_INTERNAL_VALUE 0 590 #define SI32_I2S_A_CLKCONTROL_RXCLKSEL_INTERNAL_U32 \ 591 (SI32_I2S_A_CLKCONTROL_RXCLKSEL_INTERNAL_VALUE << SI32_I2S_A_CLKCONTROL_RXCLKSEL_SHIFT) 592 // The I2S receiver is clocked from the SCK pin. 593 #define SI32_I2S_A_CLKCONTROL_RXCLKSEL_EXTERNAL_VALUE 1 594 #define SI32_I2S_A_CLKCONTROL_RXCLKSEL_EXTERNAL_U32 \ 595 (SI32_I2S_A_CLKCONTROL_RXCLKSEL_EXTERNAL_VALUE << SI32_I2S_A_CLKCONTROL_RXCLKSEL_SHIFT) 596 597 #define SI32_I2S_A_CLKCONTROL_RESET_MASK 0x00800000 598 #define SI32_I2S_A_CLKCONTROL_RESET_SHIFT 23 599 // Reset the I2S module. 600 #define SI32_I2S_A_CLKCONTROL_RESET_ACTIVE_VALUE 1 601 #define SI32_I2S_A_CLKCONTROL_RESET_ACTIVE_U32 \ 602 (SI32_I2S_A_CLKCONTROL_RESET_ACTIVE_VALUE << SI32_I2S_A_CLKCONTROL_RESET_SHIFT) 603 604 #define SI32_I2S_A_CLKCONTROL_RXCLKEN_MASK 0x01000000 605 #define SI32_I2S_A_CLKCONTROL_RXCLKEN_SHIFT 24 606 // Disable the I2S receiver clock. 607 #define SI32_I2S_A_CLKCONTROL_RXCLKEN_DISABLED_VALUE 0 608 #define SI32_I2S_A_CLKCONTROL_RXCLKEN_DISABLED_U32 \ 609 (SI32_I2S_A_CLKCONTROL_RXCLKEN_DISABLED_VALUE << SI32_I2S_A_CLKCONTROL_RXCLKEN_SHIFT) 610 // Enable the I2S receiver clock. 611 #define SI32_I2S_A_CLKCONTROL_RXCLKEN_ENABLED_VALUE 1 612 #define SI32_I2S_A_CLKCONTROL_RXCLKEN_ENABLED_U32 \ 613 (SI32_I2S_A_CLKCONTROL_RXCLKEN_ENABLED_VALUE << SI32_I2S_A_CLKCONTROL_RXCLKEN_SHIFT) 614 615 #define SI32_I2S_A_CLKCONTROL_TXCLKEN_MASK 0x02000000 616 #define SI32_I2S_A_CLKCONTROL_TXCLKEN_SHIFT 25 617 // Disable the I2S transmitter clock. 618 #define SI32_I2S_A_CLKCONTROL_TXCLKEN_DISABLED_VALUE 0 619 #define SI32_I2S_A_CLKCONTROL_TXCLKEN_DISABLED_U32 \ 620 (SI32_I2S_A_CLKCONTROL_TXCLKEN_DISABLED_VALUE << SI32_I2S_A_CLKCONTROL_TXCLKEN_SHIFT) 621 // Enable the I2S transmitter clock. 622 #define SI32_I2S_A_CLKCONTROL_TXCLKEN_ENABLED_VALUE 1 623 #define SI32_I2S_A_CLKCONTROL_TXCLKEN_ENABLED_U32 \ 624 (SI32_I2S_A_CLKCONTROL_TXCLKEN_ENABLED_VALUE << SI32_I2S_A_CLKCONTROL_TXCLKEN_SHIFT) 625 626 #define SI32_I2S_A_CLKCONTROL_RXSCLKMD_MASK 0x04000000 627 #define SI32_I2S_A_CLKCONTROL_RXSCLKMD_SHIFT 26 628 // The I2S receiver SCK signal is an output. 629 #define SI32_I2S_A_CLKCONTROL_RXSCLKMD_SCK_OUTPUT_VALUE 0 630 #define SI32_I2S_A_CLKCONTROL_RXSCLKMD_SCK_OUTPUT_U32 \ 631 (SI32_I2S_A_CLKCONTROL_RXSCLKMD_SCK_OUTPUT_VALUE << SI32_I2S_A_CLKCONTROL_RXSCLKMD_SHIFT) 632 // The I2S receiver SCK signal is an input. 633 #define SI32_I2S_A_CLKCONTROL_RXSCLKMD_SCK_INPUT_VALUE 1 634 #define SI32_I2S_A_CLKCONTROL_RXSCLKMD_SCK_INPUT_U32 \ 635 (SI32_I2S_A_CLKCONTROL_RXSCLKMD_SCK_INPUT_VALUE << SI32_I2S_A_CLKCONTROL_RXSCLKMD_SHIFT) 636 637 #define SI32_I2S_A_CLKCONTROL_TXSCLKMD_MASK 0x08000000 638 #define SI32_I2S_A_CLKCONTROL_TXSCLKMD_SHIFT 27 639 // The I2S transmitter SCK signal is an output. 640 #define SI32_I2S_A_CLKCONTROL_TXSCLKMD_SCK_OUTPUT_VALUE 0 641 #define SI32_I2S_A_CLKCONTROL_TXSCLKMD_SCK_OUTPUT_U32 \ 642 (SI32_I2S_A_CLKCONTROL_TXSCLKMD_SCK_OUTPUT_VALUE << SI32_I2S_A_CLKCONTROL_TXSCLKMD_SHIFT) 643 // The I2S transmitter SCK signal is an input. 644 #define SI32_I2S_A_CLKCONTROL_TXSCLKMD_SCK_INPUT_VALUE 1 645 #define SI32_I2S_A_CLKCONTROL_TXSCLKMD_SCK_INPUT_U32 \ 646 (SI32_I2S_A_CLKCONTROL_TXSCLKMD_SCK_INPUT_VALUE << SI32_I2S_A_CLKCONTROL_TXSCLKMD_SHIFT) 647 648 649 650 struct SI32_I2S_A_TXFIFO_Struct 651 { 652 union 653 { 654 // This is a FIFO register 655 volatile uint32_t U32; 656 }; 657 }; 658 659 #define SI32_I2S_A_TXFIFO_TXFIFO_MASK 0xFFFFFFFF 660 #define SI32_I2S_A_TXFIFO_TXFIFO_SHIFT 0 661 662 663 664 struct SI32_I2S_A_RXFIFO_Struct 665 { 666 union 667 { 668 // This is a FIFO register 669 volatile uint32_t U32; 670 }; 671 }; 672 673 #define SI32_I2S_A_RXFIFO_RXFIFO_MASK 0xFFFFFFFF 674 #define SI32_I2S_A_RXFIFO_RXFIFO_SHIFT 0 675 676 677 678 struct SI32_I2S_A_FIFOSTATUS_Struct 679 { 680 union 681 { 682 struct 683 { 684 // Transmit FIFO Status 685 volatile uint32_t TXFIFONUM: 4; 686 uint32_t reserved0: 12; 687 // Receive FIFO Status 688 volatile uint32_t RXFIFONUM: 4; 689 uint32_t reserved1: 12; 690 }; 691 volatile uint32_t U32; 692 }; 693 }; 694 695 #define SI32_I2S_A_FIFOSTATUS_TXFIFONUM_MASK 0x0000000F 696 #define SI32_I2S_A_FIFOSTATUS_TXFIFONUM_SHIFT 0 697 698 #define SI32_I2S_A_FIFOSTATUS_RXFIFONUM_MASK 0x000F0000 699 #define SI32_I2S_A_FIFOSTATUS_RXFIFONUM_SHIFT 16 700 701 702 703 struct SI32_I2S_A_FIFOCONTROL_Struct 704 { 705 union 706 { 707 struct 708 { 709 // Transmit FIFO Low Watermark 710 volatile uint32_t TXFIFOWM: 4; 711 uint32_t reserved0: 12; 712 // Receive FIFO High Watermark 713 volatile uint32_t RXFIFOWM: 4; 714 uint32_t reserved1: 1; 715 // Transmit FIFO Flush 716 volatile uint32_t TXFIFOFL: 1; 717 // Receive FIFO Flush 718 volatile uint32_t RXFIFOFL: 1; 719 uint32_t reserved2: 9; 720 }; 721 volatile uint32_t U32; 722 }; 723 }; 724 725 #define SI32_I2S_A_FIFOCONTROL_TXFIFOWM_MASK 0x0000000F 726 #define SI32_I2S_A_FIFOCONTROL_TXFIFOWM_SHIFT 0 727 728 #define SI32_I2S_A_FIFOCONTROL_RXFIFOWM_MASK 0x000F0000 729 #define SI32_I2S_A_FIFOCONTROL_RXFIFOWM_SHIFT 16 730 731 #define SI32_I2S_A_FIFOCONTROL_TXFIFOFL_MASK 0x00200000 732 #define SI32_I2S_A_FIFOCONTROL_TXFIFOFL_SHIFT 21 733 // Flush the I2S transmitter FIFO. 734 #define SI32_I2S_A_FIFOCONTROL_TXFIFOFL_SET_VALUE 1 735 #define SI32_I2S_A_FIFOCONTROL_TXFIFOFL_SET_U32 \ 736 (SI32_I2S_A_FIFOCONTROL_TXFIFOFL_SET_VALUE << SI32_I2S_A_FIFOCONTROL_TXFIFOFL_SHIFT) 737 738 #define SI32_I2S_A_FIFOCONTROL_RXFIFOFL_MASK 0x00400000 739 #define SI32_I2S_A_FIFOCONTROL_RXFIFOFL_SHIFT 22 740 // Flush the I2S receiver FIFO. 741 #define SI32_I2S_A_FIFOCONTROL_RXFIFOFL_SET_VALUE 1 742 #define SI32_I2S_A_FIFOCONTROL_RXFIFOFL_SET_U32 \ 743 (SI32_I2S_A_FIFOCONTROL_RXFIFOFL_SET_VALUE << SI32_I2S_A_FIFOCONTROL_RXFIFOFL_SHIFT) 744 745 746 747 struct SI32_I2S_A_INTCONTROL_Struct 748 { 749 union 750 { 751 struct 752 { 753 // Transmit Underflow Interrupt Enable 754 volatile uint32_t TXUFIEN: 1; 755 // Receive Overflow Interrupt Enable 756 volatile uint32_t RXOFIEN: 1; 757 // Transmit FIFO Low Watermark Interrupt Enable 758 volatile uint32_t TXLWMIEN: 1; 759 // Receive FIFO High Watermark Interrupt Enable 760 volatile uint32_t RXHWMIEN: 1; 761 uint32_t reserved0: 28; 762 }; 763 volatile uint32_t U32; 764 }; 765 }; 766 767 #define SI32_I2S_A_INTCONTROL_TXUFIEN_MASK 0x00000001 768 #define SI32_I2S_A_INTCONTROL_TXUFIEN_SHIFT 0 769 // Disable the transmit underflow interrupt. 770 #define SI32_I2S_A_INTCONTROL_TXUFIEN_DISABLED_VALUE 0 771 #define SI32_I2S_A_INTCONTROL_TXUFIEN_DISABLED_U32 \ 772 (SI32_I2S_A_INTCONTROL_TXUFIEN_DISABLED_VALUE << SI32_I2S_A_INTCONTROL_TXUFIEN_SHIFT) 773 // Enable the transmit underflow interrupt. 774 #define SI32_I2S_A_INTCONTROL_TXUFIEN_ENABLED_VALUE 1 775 #define SI32_I2S_A_INTCONTROL_TXUFIEN_ENABLED_U32 \ 776 (SI32_I2S_A_INTCONTROL_TXUFIEN_ENABLED_VALUE << SI32_I2S_A_INTCONTROL_TXUFIEN_SHIFT) 777 778 #define SI32_I2S_A_INTCONTROL_RXOFIEN_MASK 0x00000002 779 #define SI32_I2S_A_INTCONTROL_RXOFIEN_SHIFT 1 780 // Disable the receive overflow interrupt. 781 #define SI32_I2S_A_INTCONTROL_RXOFIEN_DISABLED_VALUE 0 782 #define SI32_I2S_A_INTCONTROL_RXOFIEN_DISABLED_U32 \ 783 (SI32_I2S_A_INTCONTROL_RXOFIEN_DISABLED_VALUE << SI32_I2S_A_INTCONTROL_RXOFIEN_SHIFT) 784 // Enable the receive overflow interrupt. 785 #define SI32_I2S_A_INTCONTROL_RXOFIEN_ENABLED_VALUE 1 786 #define SI32_I2S_A_INTCONTROL_RXOFIEN_ENABLED_U32 \ 787 (SI32_I2S_A_INTCONTROL_RXOFIEN_ENABLED_VALUE << SI32_I2S_A_INTCONTROL_RXOFIEN_SHIFT) 788 789 #define SI32_I2S_A_INTCONTROL_TXLWMIEN_MASK 0x00000004 790 #define SI32_I2S_A_INTCONTROL_TXLWMIEN_SHIFT 2 791 // Disable the transmit FIFO low watermark interrupt. 792 #define SI32_I2S_A_INTCONTROL_TXLWMIEN_DISABLED_VALUE 0 793 #define SI32_I2S_A_INTCONTROL_TXLWMIEN_DISABLED_U32 \ 794 (SI32_I2S_A_INTCONTROL_TXLWMIEN_DISABLED_VALUE << SI32_I2S_A_INTCONTROL_TXLWMIEN_SHIFT) 795 // Enable the transmit FIFO low watermark interrupt. 796 #define SI32_I2S_A_INTCONTROL_TXLWMIEN_ENABLED_VALUE 1 797 #define SI32_I2S_A_INTCONTROL_TXLWMIEN_ENABLED_U32 \ 798 (SI32_I2S_A_INTCONTROL_TXLWMIEN_ENABLED_VALUE << SI32_I2S_A_INTCONTROL_TXLWMIEN_SHIFT) 799 800 #define SI32_I2S_A_INTCONTROL_RXHWMIEN_MASK 0x00000008 801 #define SI32_I2S_A_INTCONTROL_RXHWMIEN_SHIFT 3 802 // Disable the receive FIFO high watermark interrupt. 803 #define SI32_I2S_A_INTCONTROL_RXHWMIEN_DISABLED_VALUE 0 804 #define SI32_I2S_A_INTCONTROL_RXHWMIEN_DISABLED_U32 \ 805 (SI32_I2S_A_INTCONTROL_RXHWMIEN_DISABLED_VALUE << SI32_I2S_A_INTCONTROL_RXHWMIEN_SHIFT) 806 // Enable the receive FIFO high watermark interrupt. 807 #define SI32_I2S_A_INTCONTROL_RXHWMIEN_ENABLED_VALUE 1 808 #define SI32_I2S_A_INTCONTROL_RXHWMIEN_ENABLED_U32 \ 809 (SI32_I2S_A_INTCONTROL_RXHWMIEN_ENABLED_VALUE << SI32_I2S_A_INTCONTROL_RXHWMIEN_SHIFT) 810 811 812 813 struct SI32_I2S_A_STATUS_Struct 814 { 815 union 816 { 817 struct 818 { 819 // Transmit Underflow Interrupt Flag 820 volatile uint32_t TXUFI: 1; 821 // Receive Overflow Interrupt Flag 822 volatile uint32_t RXOFI: 1; 823 // Transmit FIFO Low Watermark Interrupt Flag 824 volatile uint32_t TXLWMI: 1; 825 // Receive FIFO High Watermark Interrupt Flag 826 volatile uint32_t RXHWMI: 1; 827 // Clock Divider Busy Flag 828 volatile uint32_t CDBUSYF: 1; 829 // Clock Divider Counter Status 830 volatile uint32_t CDSTS: 1; 831 // Transmit Clock Select Ready Flag 832 volatile uint32_t TXCLKSELRF: 1; 833 // Receive Clock Select Ready Flag 834 volatile uint32_t RXCLKSELRF: 1; 835 // Transmit Clock Enable Ready Flag 836 volatile uint32_t TXCLKENRF: 1; 837 // Receive Clock Enable Ready Flag 838 volatile uint32_t RXCLKENRF: 1; 839 uint32_t reserved0: 22; 840 }; 841 volatile uint32_t U32; 842 }; 843 }; 844 845 #define SI32_I2S_A_STATUS_TXUFI_MASK 0x00000001 846 #define SI32_I2S_A_STATUS_TXUFI_SHIFT 0 847 // A transmit underflow has not occurred. 848 #define SI32_I2S_A_STATUS_TXUFI_NOT_SET_VALUE 0 849 #define SI32_I2S_A_STATUS_TXUFI_NOT_SET_U32 \ 850 (SI32_I2S_A_STATUS_TXUFI_NOT_SET_VALUE << SI32_I2S_A_STATUS_TXUFI_SHIFT) 851 // A transmit underflow occurred. 852 #define SI32_I2S_A_STATUS_TXUFI_SET_VALUE 1 853 #define SI32_I2S_A_STATUS_TXUFI_SET_U32 \ 854 (SI32_I2S_A_STATUS_TXUFI_SET_VALUE << SI32_I2S_A_STATUS_TXUFI_SHIFT) 855 856 #define SI32_I2S_A_STATUS_RXOFI_MASK 0x00000002 857 #define SI32_I2S_A_STATUS_RXOFI_SHIFT 1 858 // A receive overflow has not occurred. 859 #define SI32_I2S_A_STATUS_RXOFI_NOT_SET_VALUE 0 860 #define SI32_I2S_A_STATUS_RXOFI_NOT_SET_U32 \ 861 (SI32_I2S_A_STATUS_RXOFI_NOT_SET_VALUE << SI32_I2S_A_STATUS_RXOFI_SHIFT) 862 // A receive overflow occurred. 863 #define SI32_I2S_A_STATUS_RXOFI_SET_VALUE 1 864 #define SI32_I2S_A_STATUS_RXOFI_SET_U32 \ 865 (SI32_I2S_A_STATUS_RXOFI_SET_VALUE << SI32_I2S_A_STATUS_RXOFI_SHIFT) 866 867 #define SI32_I2S_A_STATUS_TXLWMI_MASK 0x00000004 868 #define SI32_I2S_A_STATUS_TXLWMI_SHIFT 2 869 // Transmit FIFO level is above the low watermark. 870 #define SI32_I2S_A_STATUS_TXLWMI_NOT_SET_VALUE 0 871 #define SI32_I2S_A_STATUS_TXLWMI_NOT_SET_U32 \ 872 (SI32_I2S_A_STATUS_TXLWMI_NOT_SET_VALUE << SI32_I2S_A_STATUS_TXLWMI_SHIFT) 873 // Transmit FIFO level is at or below the low watermark. 874 #define SI32_I2S_A_STATUS_TXLWMI_SET_VALUE 1 875 #define SI32_I2S_A_STATUS_TXLWMI_SET_U32 \ 876 (SI32_I2S_A_STATUS_TXLWMI_SET_VALUE << SI32_I2S_A_STATUS_TXLWMI_SHIFT) 877 878 #define SI32_I2S_A_STATUS_RXHWMI_MASK 0x00000008 879 #define SI32_I2S_A_STATUS_RXHWMI_SHIFT 3 880 // Receive FIFO level is below the high watermark. 881 #define SI32_I2S_A_STATUS_RXHWMI_NOT_SET_VALUE 0 882 #define SI32_I2S_A_STATUS_RXHWMI_NOT_SET_U32 \ 883 (SI32_I2S_A_STATUS_RXHWMI_NOT_SET_VALUE << SI32_I2S_A_STATUS_RXHWMI_SHIFT) 884 // Receive FIFO level is at or above the high watermark. 885 #define SI32_I2S_A_STATUS_RXHWMI_SET_VALUE 1 886 #define SI32_I2S_A_STATUS_RXHWMI_SET_U32 \ 887 (SI32_I2S_A_STATUS_RXHWMI_SET_VALUE << SI32_I2S_A_STATUS_RXHWMI_SHIFT) 888 889 #define SI32_I2S_A_STATUS_CDBUSYF_MASK 0x00000010 890 #define SI32_I2S_A_STATUS_CDBUSYF_SHIFT 4 891 // The divider is not busy and an update is not pending. 892 #define SI32_I2S_A_STATUS_CDBUSYF_NOT_BUSY_VALUE 0 893 #define SI32_I2S_A_STATUS_CDBUSYF_NOT_BUSY_U32 \ 894 (SI32_I2S_A_STATUS_CDBUSYF_NOT_BUSY_VALUE << SI32_I2S_A_STATUS_CDBUSYF_SHIFT) 895 // The divider is busy and an update is pending. 896 #define SI32_I2S_A_STATUS_CDBUSYF_BUSY_VALUE 1 897 #define SI32_I2S_A_STATUS_CDBUSYF_BUSY_U32 \ 898 (SI32_I2S_A_STATUS_CDBUSYF_BUSY_VALUE << SI32_I2S_A_STATUS_CDBUSYF_SHIFT) 899 900 #define SI32_I2S_A_STATUS_CDSTS_MASK 0x00000020 901 #define SI32_I2S_A_STATUS_CDSTS_SHIFT 5 902 // Divided clock output is running. 903 #define SI32_I2S_A_STATUS_CDSTS_RUNNING_VALUE 0 904 #define SI32_I2S_A_STATUS_CDSTS_RUNNING_U32 \ 905 (SI32_I2S_A_STATUS_CDSTS_RUNNING_VALUE << SI32_I2S_A_STATUS_CDSTS_SHIFT) 906 // Divided clock output is halted. 907 #define SI32_I2S_A_STATUS_CDSTS_HALTED_VALUE 1 908 #define SI32_I2S_A_STATUS_CDSTS_HALTED_U32 \ 909 (SI32_I2S_A_STATUS_CDSTS_HALTED_VALUE << SI32_I2S_A_STATUS_CDSTS_SHIFT) 910 911 #define SI32_I2S_A_STATUS_TXCLKSELRF_MASK 0x00000040 912 #define SI32_I2S_A_STATUS_TXCLKSELRF_SHIFT 6 913 // The transmit clock is not synchronized. 914 #define SI32_I2S_A_STATUS_TXCLKSELRF_NOT_SET_VALUE 0 915 #define SI32_I2S_A_STATUS_TXCLKSELRF_NOT_SET_U32 \ 916 (SI32_I2S_A_STATUS_TXCLKSELRF_NOT_SET_VALUE << SI32_I2S_A_STATUS_TXCLKSELRF_SHIFT) 917 // The transmit clock is synchronized and the transmitter is ready to send data. 918 #define SI32_I2S_A_STATUS_TXCLKSELRF_SET_VALUE 1 919 #define SI32_I2S_A_STATUS_TXCLKSELRF_SET_U32 \ 920 (SI32_I2S_A_STATUS_TXCLKSELRF_SET_VALUE << SI32_I2S_A_STATUS_TXCLKSELRF_SHIFT) 921 922 #define SI32_I2S_A_STATUS_RXCLKSELRF_MASK 0x00000080 923 #define SI32_I2S_A_STATUS_RXCLKSELRF_SHIFT 7 924 // The receive clock is not synchronized. 925 #define SI32_I2S_A_STATUS_RXCLKSELRF_NOT_SET_VALUE 0 926 #define SI32_I2S_A_STATUS_RXCLKSELRF_NOT_SET_U32 \ 927 (SI32_I2S_A_STATUS_RXCLKSELRF_NOT_SET_VALUE << SI32_I2S_A_STATUS_RXCLKSELRF_SHIFT) 928 // The receive clock is synchronized and the receiver is ready to accept data. 929 #define SI32_I2S_A_STATUS_RXCLKSELRF_SET_VALUE 1 930 #define SI32_I2S_A_STATUS_RXCLKSELRF_SET_U32 \ 931 (SI32_I2S_A_STATUS_RXCLKSELRF_SET_VALUE << SI32_I2S_A_STATUS_RXCLKSELRF_SHIFT) 932 933 #define SI32_I2S_A_STATUS_TXCLKENRF_MASK 0x00000100 934 #define SI32_I2S_A_STATUS_TXCLKENRF_SHIFT 8 935 // The transmit clock is not synchronized. 936 #define SI32_I2S_A_STATUS_TXCLKENRF_NOT_SET_VALUE 0 937 #define SI32_I2S_A_STATUS_TXCLKENRF_NOT_SET_U32 \ 938 (SI32_I2S_A_STATUS_TXCLKENRF_NOT_SET_VALUE << SI32_I2S_A_STATUS_TXCLKENRF_SHIFT) 939 // The transmit clock is synchronized and the transmitter is ready to send data. 940 #define SI32_I2S_A_STATUS_TXCLKENRF_SET_VALUE 1 941 #define SI32_I2S_A_STATUS_TXCLKENRF_SET_U32 \ 942 (SI32_I2S_A_STATUS_TXCLKENRF_SET_VALUE << SI32_I2S_A_STATUS_TXCLKENRF_SHIFT) 943 944 #define SI32_I2S_A_STATUS_RXCLKENRF_MASK 0x00000200 945 #define SI32_I2S_A_STATUS_RXCLKENRF_SHIFT 9 946 // The receive clock is not synchronized. 947 #define SI32_I2S_A_STATUS_RXCLKENRF_NOT_SET_VALUE 0 948 #define SI32_I2S_A_STATUS_RXCLKENRF_NOT_SET_U32 \ 949 (SI32_I2S_A_STATUS_RXCLKENRF_NOT_SET_VALUE << SI32_I2S_A_STATUS_RXCLKENRF_SHIFT) 950 // The receive clock is synchronized and the receiver is ready to accept data. 951 #define SI32_I2S_A_STATUS_RXCLKENRF_SET_VALUE 1 952 #define SI32_I2S_A_STATUS_RXCLKENRF_SET_U32 \ 953 (SI32_I2S_A_STATUS_RXCLKENRF_SET_VALUE << SI32_I2S_A_STATUS_RXCLKENRF_SHIFT) 954 955 956 957 struct SI32_I2S_A_DMACONTROL_Struct 958 { 959 union 960 { 961 struct 962 { 963 // Transmit DMA Enable 964 volatile uint32_t TXDMAEN: 1; 965 // Receive DMA Enable 966 volatile uint32_t RXDMAEN: 1; 967 // Transmit DMA Burst Mode 968 volatile uint32_t TXDMABMD: 1; 969 // Receive DMA Burst Mode 970 volatile uint32_t RXDMABMD: 1; 971 uint32_t reserved0: 28; 972 }; 973 volatile uint32_t U32; 974 }; 975 }; 976 977 #define SI32_I2S_A_DMACONTROL_TXDMAEN_MASK 0x00000001 978 #define SI32_I2S_A_DMACONTROL_TXDMAEN_SHIFT 0 979 // Disable transmitter DMA data requests. 980 #define SI32_I2S_A_DMACONTROL_TXDMAEN_DISABLED_VALUE 0 981 #define SI32_I2S_A_DMACONTROL_TXDMAEN_DISABLED_U32 \ 982 (SI32_I2S_A_DMACONTROL_TXDMAEN_DISABLED_VALUE << SI32_I2S_A_DMACONTROL_TXDMAEN_SHIFT) 983 // Enable transmitter DMA data requests. 984 #define SI32_I2S_A_DMACONTROL_TXDMAEN_ENABLED_VALUE 1 985 #define SI32_I2S_A_DMACONTROL_TXDMAEN_ENABLED_U32 \ 986 (SI32_I2S_A_DMACONTROL_TXDMAEN_ENABLED_VALUE << SI32_I2S_A_DMACONTROL_TXDMAEN_SHIFT) 987 988 #define SI32_I2S_A_DMACONTROL_RXDMAEN_MASK 0x00000002 989 #define SI32_I2S_A_DMACONTROL_RXDMAEN_SHIFT 1 990 // Disable receiver DMA data transfer requests. 991 #define SI32_I2S_A_DMACONTROL_RXDMAEN_DISABLED_VALUE 0 992 #define SI32_I2S_A_DMACONTROL_RXDMAEN_DISABLED_U32 \ 993 (SI32_I2S_A_DMACONTROL_RXDMAEN_DISABLED_VALUE << SI32_I2S_A_DMACONTROL_RXDMAEN_SHIFT) 994 // Enable receiver DMA data transfer requests. 995 #define SI32_I2S_A_DMACONTROL_RXDMAEN_ENABLED_VALUE 1 996 #define SI32_I2S_A_DMACONTROL_RXDMAEN_ENABLED_U32 \ 997 (SI32_I2S_A_DMACONTROL_RXDMAEN_ENABLED_VALUE << SI32_I2S_A_DMACONTROL_RXDMAEN_SHIFT) 998 999 #define SI32_I2S_A_DMACONTROL_TXDMABMD_MASK 0x00000004 1000 #define SI32_I2S_A_DMACONTROL_TXDMABMD_SHIFT 2 1001 // The transmitter transmits one word at a time. Whenever there is any room in the 1002 // transmit FIFO, a single word burst DMA data request is generated. 1003 #define SI32_I2S_A_DMACONTROL_TXDMABMD_ONE_WORD_VALUE 0 1004 #define SI32_I2S_A_DMACONTROL_TXDMABMD_ONE_WORD_U32 \ 1005 (SI32_I2S_A_DMACONTROL_TXDMABMD_ONE_WORD_VALUE << SI32_I2S_A_DMACONTROL_TXDMABMD_SHIFT) 1006 // The transmitter transmits four words at a time. Whenever the FIFO depth drops 1007 // below five, a DMA burst request is generated for four words. 1008 #define SI32_I2S_A_DMACONTROL_TXDMABMD_FOUR_WORDS_VALUE 1 1009 #define SI32_I2S_A_DMACONTROL_TXDMABMD_FOUR_WORDS_U32 \ 1010 (SI32_I2S_A_DMACONTROL_TXDMABMD_FOUR_WORDS_VALUE << SI32_I2S_A_DMACONTROL_TXDMABMD_SHIFT) 1011 1012 #define SI32_I2S_A_DMACONTROL_RXDMABMD_MASK 0x00000008 1013 #define SI32_I2S_A_DMACONTROL_RXDMABMD_SHIFT 3 1014 // The receiver receives one word at a time. Whenever there is at least one word in 1015 // the receive FIFO, a single word burst DMA request is generated. 1016 #define SI32_I2S_A_DMACONTROL_RXDMABMD_ONE_WORD_VALUE 0 1017 #define SI32_I2S_A_DMACONTROL_RXDMABMD_ONE_WORD_U32 \ 1018 (SI32_I2S_A_DMACONTROL_RXDMABMD_ONE_WORD_VALUE << SI32_I2S_A_DMACONTROL_RXDMABMD_SHIFT) 1019 // The receiver receives four words at a time. Whenever the FIFO depth rises above 1020 // three, a DMA burst request is generated for four words. 1021 #define SI32_I2S_A_DMACONTROL_RXDMABMD_FOUR_WORDS_VALUE 1 1022 #define SI32_I2S_A_DMACONTROL_RXDMABMD_FOUR_WORDS_U32 \ 1023 (SI32_I2S_A_DMACONTROL_RXDMABMD_FOUR_WORDS_VALUE << SI32_I2S_A_DMACONTROL_RXDMABMD_SHIFT) 1024 1025 1026 1027 struct SI32_I2S_A_DBGCONTROL_Struct 1028 { 1029 union 1030 { 1031 struct 1032 { 1033 // I2S Transmit DMA Debug Halt Enable 1034 volatile uint32_t TXDBGHEN: 1; 1035 // I2S Receive DMA Debug Halt Enable 1036 volatile uint32_t RXDBGHEN: 1; 1037 // I2S Transmit Debug Mode 1038 volatile uint32_t TXDBGMD: 1; 1039 // I2S Receive Debug Mode 1040 volatile uint32_t RXDBGMD: 1; 1041 uint32_t reserved0: 28; 1042 }; 1043 volatile uint32_t U32; 1044 }; 1045 }; 1046 1047 #define SI32_I2S_A_DBGCONTROL_TXDBGHEN_MASK 0x00000001 1048 #define SI32_I2S_A_DBGCONTROL_TXDBGHEN_SHIFT 0 1049 // Transmit DMA requests continue while the core is debug mode. 1050 #define SI32_I2S_A_DBGCONTROL_TXDBGHEN_DISABLED_VALUE 0 1051 #define SI32_I2S_A_DBGCONTROL_TXDBGHEN_DISABLED_U32 \ 1052 (SI32_I2S_A_DBGCONTROL_TXDBGHEN_DISABLED_VALUE << SI32_I2S_A_DBGCONTROL_TXDBGHEN_SHIFT) 1053 // Transmit DMA requests stop while the core is debug mode. 1054 #define SI32_I2S_A_DBGCONTROL_TXDBGHEN_ENABLED_VALUE 1 1055 #define SI32_I2S_A_DBGCONTROL_TXDBGHEN_ENABLED_U32 \ 1056 (SI32_I2S_A_DBGCONTROL_TXDBGHEN_ENABLED_VALUE << SI32_I2S_A_DBGCONTROL_TXDBGHEN_SHIFT) 1057 1058 #define SI32_I2S_A_DBGCONTROL_RXDBGHEN_MASK 0x00000002 1059 #define SI32_I2S_A_DBGCONTROL_RXDBGHEN_SHIFT 1 1060 // Receive DMA requests continue while the core is debug mode. 1061 #define SI32_I2S_A_DBGCONTROL_RXDBGHEN_DISABLED_VALUE 0 1062 #define SI32_I2S_A_DBGCONTROL_RXDBGHEN_DISABLED_U32 \ 1063 (SI32_I2S_A_DBGCONTROL_RXDBGHEN_DISABLED_VALUE << SI32_I2S_A_DBGCONTROL_RXDBGHEN_SHIFT) 1064 // Receive DMA requests stop while the core is debug mode. 1065 #define SI32_I2S_A_DBGCONTROL_RXDBGHEN_ENABLED_VALUE 1 1066 #define SI32_I2S_A_DBGCONTROL_RXDBGHEN_ENABLED_U32 \ 1067 (SI32_I2S_A_DBGCONTROL_RXDBGHEN_ENABLED_VALUE << SI32_I2S_A_DBGCONTROL_RXDBGHEN_SHIFT) 1068 1069 #define SI32_I2S_A_DBGCONTROL_TXDBGMD_MASK 0x00000004 1070 #define SI32_I2S_A_DBGCONTROL_TXDBGMD_SHIFT 2 1071 // The clock to the I2S transmitter is active in debug mode. 1072 #define SI32_I2S_A_DBGCONTROL_TXDBGMD_RUN_VALUE 0 1073 #define SI32_I2S_A_DBGCONTROL_TXDBGMD_RUN_U32 \ 1074 (SI32_I2S_A_DBGCONTROL_TXDBGMD_RUN_VALUE << SI32_I2S_A_DBGCONTROL_TXDBGMD_SHIFT) 1075 // The clock to the I2S transmitter is not active in debug mode. The clock divider 1076 // keeps running and the clock will be disabled when two samples are ready to be 1077 // sent by the transmitter. 1078 #define SI32_I2S_A_DBGCONTROL_TXDBGMD_HALT_VALUE 1 1079 #define SI32_I2S_A_DBGCONTROL_TXDBGMD_HALT_U32 \ 1080 (SI32_I2S_A_DBGCONTROL_TXDBGMD_HALT_VALUE << SI32_I2S_A_DBGCONTROL_TXDBGMD_SHIFT) 1081 1082 #define SI32_I2S_A_DBGCONTROL_RXDBGMD_MASK 0x00000008 1083 #define SI32_I2S_A_DBGCONTROL_RXDBGMD_SHIFT 3 1084 // The clock to the I2S receiver is active in debug mode. 1085 #define SI32_I2S_A_DBGCONTROL_RXDBGMD_RUN_VALUE 0 1086 #define SI32_I2S_A_DBGCONTROL_RXDBGMD_RUN_U32 \ 1087 (SI32_I2S_A_DBGCONTROL_RXDBGMD_RUN_VALUE << SI32_I2S_A_DBGCONTROL_RXDBGMD_SHIFT) 1088 // The clock to the I2S receiver is not active in debug mode. The clock divider 1089 // keeps running and the clock will be disabled when two samples are captured in 1090 // the receiver. 1091 #define SI32_I2S_A_DBGCONTROL_RXDBGMD_HALT_VALUE 1 1092 #define SI32_I2S_A_DBGCONTROL_RXDBGMD_HALT_U32 \ 1093 (SI32_I2S_A_DBGCONTROL_RXDBGMD_HALT_VALUE << SI32_I2S_A_DBGCONTROL_RXDBGMD_SHIFT) 1094 1095 1096 1097 typedef struct SI32_I2S_A_Struct 1098 { 1099 struct SI32_I2S_A_TXCONTROL_Struct TXCONTROL ; // Base Address + 0x0 1100 volatile uint32_t TXCONTROL_SET; 1101 volatile uint32_t TXCONTROL_CLR; 1102 uint32_t reserved0; 1103 struct SI32_I2S_A_TXMODE_Struct TXMODE ; // Base Address + 0x10 1104 volatile uint32_t TXMODE_SET; 1105 volatile uint32_t TXMODE_CLR; 1106 uint32_t reserved1; 1107 struct SI32_I2S_A_FSDUTY_Struct FSDUTY ; // Base Address + 0x20 1108 uint32_t reserved2; 1109 uint32_t reserved3; 1110 uint32_t reserved4; 1111 struct SI32_I2S_A_RXCONTROL_Struct RXCONTROL ; // Base Address + 0x30 1112 volatile uint32_t RXCONTROL_SET; 1113 volatile uint32_t RXCONTROL_CLR; 1114 uint32_t reserved5; 1115 struct SI32_I2S_A_RXMODE_Struct RXMODE ; // Base Address + 0x40 1116 volatile uint32_t RXMODE_SET; 1117 volatile uint32_t RXMODE_CLR; 1118 uint32_t reserved6; 1119 struct SI32_I2S_A_CLKCONTROL_Struct CLKCONTROL ; // Base Address + 0x50 1120 volatile uint32_t CLKCONTROL_SET; 1121 volatile uint32_t CLKCONTROL_CLR; 1122 uint32_t reserved7; 1123 struct SI32_I2S_A_TXFIFO_Struct TXFIFO ; // Base Address + 0x60 1124 uint32_t reserved8; 1125 uint32_t reserved9; 1126 uint32_t reserved10; 1127 struct SI32_I2S_A_RXFIFO_Struct RXFIFO ; // Base Address + 0x70 1128 uint32_t reserved11; 1129 uint32_t reserved12; 1130 uint32_t reserved13; 1131 struct SI32_I2S_A_FIFOSTATUS_Struct FIFOSTATUS ; // Base Address + 0x80 1132 uint32_t reserved14; 1133 uint32_t reserved15; 1134 uint32_t reserved16; 1135 struct SI32_I2S_A_FIFOCONTROL_Struct FIFOCONTROL ; // Base Address + 0x90 1136 volatile uint32_t FIFOCONTROL_SET; 1137 volatile uint32_t FIFOCONTROL_CLR; 1138 uint32_t reserved17; 1139 struct SI32_I2S_A_INTCONTROL_Struct INTCONTROL ; // Base Address + 0xa0 1140 volatile uint32_t INTCONTROL_SET; 1141 volatile uint32_t INTCONTROL_CLR; 1142 uint32_t reserved18; 1143 struct SI32_I2S_A_STATUS_Struct STATUS ; // Base Address + 0xb0 1144 volatile uint32_t STATUS_SET; 1145 volatile uint32_t STATUS_CLR; 1146 uint32_t reserved19; 1147 struct SI32_I2S_A_DMACONTROL_Struct DMACONTROL ; // Base Address + 0xc0 1148 volatile uint32_t DMACONTROL_SET; 1149 volatile uint32_t DMACONTROL_CLR; 1150 uint32_t reserved20; 1151 struct SI32_I2S_A_DBGCONTROL_Struct DBGCONTROL ; // Base Address + 0xd0 1152 volatile uint32_t DBGCONTROL_SET; 1153 volatile uint32_t DBGCONTROL_CLR; 1154 uint32_t reserved21; 1155 } SI32_I2S_A_Type; 1156 1157 #ifdef __cplusplus 1158 } 1159 #endif 1160 1161 #endif // __SI32_I2S_A_REGISTERS_H__ 1162 1163 //-eof-------------------------------------------------------------------------- 1164 1165
