1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.62 24 // Version: 1 25 26 #ifndef __SI32_EPCA_A_REGISTERS_H__ 27 #define __SI32_EPCA_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_EPCA_A_MODE_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Input Clock Divider 42 volatile uint32_t CLKDIV: 10; 43 // Input Clock (F<subscript>CLKIN</subscript>) Select 44 volatile uint32_t CLKSEL: 3; 45 uint32_t reserved0: 1; 46 // High Drive Port Bank Output Select 47 volatile uint32_t HDOSEL: 2; 48 // DMA Write End Index 49 volatile uint32_t DEND: 3; 50 // DMA Write Transfer Pointer 51 volatile uint32_t DPTR: 3; 52 // DMA Target Start Index 53 volatile uint32_t DSTART: 3; 54 // DMA Busy Flag 55 volatile uint32_t DBUSYF: 1; 56 uint32_t reserved1: 1; 57 // Standard Port Bank Output Select 58 volatile uint32_t STDOSEL: 2; 59 uint32_t reserved2: 3; 60 }; 61 volatile uint32_t U32; 62 }; 63 }; 64 65 #define SI32_EPCA_A_MODE_CLKDIV_MASK 0x000003FF 66 #define SI32_EPCA_A_MODE_CLKDIV_SHIFT 0 67 68 #define SI32_EPCA_A_MODE_CLKSEL_MASK 0x00001C00 69 #define SI32_EPCA_A_MODE_CLKSEL_SHIFT 10 70 // Set the APB as the input clock (FCLKIN). 71 #define SI32_EPCA_A_MODE_CLKSEL_APB_VALUE 0 72 #define SI32_EPCA_A_MODE_CLKSEL_APB_U32 \ 73 (SI32_EPCA_A_MODE_CLKSEL_APB_VALUE << SI32_EPCA_A_MODE_CLKSEL_SHIFT) 74 // Set Timer 0 low overflows divided by 2 as the input clock (FCLKIN). 75 #define SI32_EPCA_A_MODE_CLKSEL_TIMER0_VALUE 1 76 #define SI32_EPCA_A_MODE_CLKSEL_TIMER0_U32 \ 77 (SI32_EPCA_A_MODE_CLKSEL_TIMER0_VALUE << SI32_EPCA_A_MODE_CLKSEL_SHIFT) 78 // Set high-to-low transitions on ECI divided by 2 as the input clock (FCLKIN). 79 #define SI32_EPCA_A_MODE_CLKSEL_HL_ECI_VALUE 2 80 #define SI32_EPCA_A_MODE_CLKSEL_HL_ECI_U32 \ 81 (SI32_EPCA_A_MODE_CLKSEL_HL_ECI_VALUE << SI32_EPCA_A_MODE_CLKSEL_SHIFT) 82 // Set the external oscillator module output (EXTOSCn) divided by 2 as the input 83 // clock (FCLKIN). 84 #define SI32_EPCA_A_MODE_CLKSEL_EXTOSCN_VALUE 3 85 #define SI32_EPCA_A_MODE_CLKSEL_EXTOSCN_U32 \ 86 (SI32_EPCA_A_MODE_CLKSEL_EXTOSCN_VALUE << SI32_EPCA_A_MODE_CLKSEL_SHIFT) 87 // Set ECI transitions divided by 2 as the input clock (FCLKIN). 88 #define SI32_EPCA_A_MODE_CLKSEL_ECI_VALUE 4 89 #define SI32_EPCA_A_MODE_CLKSEL_ECI_U32 \ 90 (SI32_EPCA_A_MODE_CLKSEL_ECI_VALUE << SI32_EPCA_A_MODE_CLKSEL_SHIFT) 91 92 #define SI32_EPCA_A_MODE_HDOSEL_MASK 0x0000C000 93 #define SI32_EPCA_A_MODE_HDOSEL_SHIFT 14 94 // Select three differential outputs from Channels 3, 4, and 5 for the High Drive 95 // pins. 96 #define SI32_EPCA_A_MODE_HDOSEL_THREE_DIFF_VALUE 0 97 #define SI32_EPCA_A_MODE_HDOSEL_THREE_DIFF_U32 \ 98 (SI32_EPCA_A_MODE_HDOSEL_THREE_DIFF_VALUE << SI32_EPCA_A_MODE_HDOSEL_SHIFT) 99 // Select the differential outputs from Channels 4 and 5 and non-differential 100 // outputs from Channels 2 and 3 for the High Drive pins. 101 #define SI32_EPCA_A_MODE_HDOSEL_TWO_DIFF_VALUE 1 102 #define SI32_EPCA_A_MODE_HDOSEL_TWO_DIFF_U32 \ 103 (SI32_EPCA_A_MODE_HDOSEL_TWO_DIFF_VALUE << SI32_EPCA_A_MODE_HDOSEL_SHIFT) 104 // Select the differential output from Channel 5 and non-differential outputs from 105 // Channels 1-4 for the High Drive pins. 106 #define SI32_EPCA_A_MODE_HDOSEL_ONE_DIFF_VALUE 2 107 #define SI32_EPCA_A_MODE_HDOSEL_ONE_DIFF_U32 \ 108 (SI32_EPCA_A_MODE_HDOSEL_ONE_DIFF_VALUE << SI32_EPCA_A_MODE_HDOSEL_SHIFT) 109 // Select the non-differential channel outputs (Channels 0-5) for the High Drive 110 // pins. 111 #define SI32_EPCA_A_MODE_HDOSEL_NO_DIFF_VALUE 3 112 #define SI32_EPCA_A_MODE_HDOSEL_NO_DIFF_U32 \ 113 (SI32_EPCA_A_MODE_HDOSEL_NO_DIFF_VALUE << SI32_EPCA_A_MODE_HDOSEL_SHIFT) 114 115 #define SI32_EPCA_A_MODE_DEND_MASK 0x00070000 116 #define SI32_EPCA_A_MODE_DEND_SHIFT 16 117 // Set the last register in a DMA write transfer to LIMITUPD. 118 #define SI32_EPCA_A_MODE_DEND_LIMIT_VALUE 0 119 #define SI32_EPCA_A_MODE_DEND_LIMIT_U32 \ 120 (SI32_EPCA_A_MODE_DEND_LIMIT_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 121 // Set the last register in a DMA write transfer to Channel 0 CCAPVUPD. 122 #define SI32_EPCA_A_MODE_DEND_CH0_VALUE 1 123 #define SI32_EPCA_A_MODE_DEND_CH0_U32 \ 124 (SI32_EPCA_A_MODE_DEND_CH0_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 125 // Set the last register in a DMA write transfer to Channel 1 CCAPVUPD. 126 #define SI32_EPCA_A_MODE_DEND_CH1_VALUE 2 127 #define SI32_EPCA_A_MODE_DEND_CH1_U32 \ 128 (SI32_EPCA_A_MODE_DEND_CH1_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 129 // Set the last register in a DMA write transfer to Channel 2 CCAPVUPD. 130 #define SI32_EPCA_A_MODE_DEND_CH2_VALUE 3 131 #define SI32_EPCA_A_MODE_DEND_CH2_U32 \ 132 (SI32_EPCA_A_MODE_DEND_CH2_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 133 // Set the last register in a DMA write transfer to Channel 3 CCAPVUPD. 134 #define SI32_EPCA_A_MODE_DEND_CH3_VALUE 4 135 #define SI32_EPCA_A_MODE_DEND_CH3_U32 \ 136 (SI32_EPCA_A_MODE_DEND_CH3_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 137 // Set the last register in a DMA write transfer to Channel 4 CCAPVUPD. 138 #define SI32_EPCA_A_MODE_DEND_CH4_VALUE 5 139 #define SI32_EPCA_A_MODE_DEND_CH4_U32 \ 140 (SI32_EPCA_A_MODE_DEND_CH4_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 141 // Set the last register in a DMA write transfer to Channel 5 CCAPVUPD. 142 #define SI32_EPCA_A_MODE_DEND_CH5_VALUE 6 143 #define SI32_EPCA_A_MODE_DEND_CH5_U32 \ 144 (SI32_EPCA_A_MODE_DEND_CH5_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 145 // Empty slot. 146 #define SI32_EPCA_A_MODE_DEND_EMPTY_VALUE 7 147 #define SI32_EPCA_A_MODE_DEND_EMPTY_U32 \ 148 (SI32_EPCA_A_MODE_DEND_EMPTY_VALUE << SI32_EPCA_A_MODE_DEND_SHIFT) 149 150 #define SI32_EPCA_A_MODE_DPTR_MASK 0x00380000 151 #define SI32_EPCA_A_MODE_DPTR_SHIFT 19 152 // The DMA channel will write to LIMITUPD next. 153 #define SI32_EPCA_A_MODE_DPTR_LIMIT_VALUE 0 154 #define SI32_EPCA_A_MODE_DPTR_LIMIT_U32 \ 155 (SI32_EPCA_A_MODE_DPTR_LIMIT_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 156 // The DMA channel will write to Channel 0 CCAPVUPD next. 157 #define SI32_EPCA_A_MODE_DPTR_CH0_VALUE 1 158 #define SI32_EPCA_A_MODE_DPTR_CH0_U32 \ 159 (SI32_EPCA_A_MODE_DPTR_CH0_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 160 // The DMA channel will write to Channel 1 CCAPVUPD next. 161 #define SI32_EPCA_A_MODE_DPTR_CH1_VALUE 2 162 #define SI32_EPCA_A_MODE_DPTR_CH1_U32 \ 163 (SI32_EPCA_A_MODE_DPTR_CH1_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 164 // The DMA channel will write to Channel 2 CCAPVUPD next. 165 #define SI32_EPCA_A_MODE_DPTR_CH2_VALUE 3 166 #define SI32_EPCA_A_MODE_DPTR_CH2_U32 \ 167 (SI32_EPCA_A_MODE_DPTR_CH2_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 168 // The DMA channel will write to Channel 3 CCAPVUPD next. 169 #define SI32_EPCA_A_MODE_DPTR_CH3_VALUE 4 170 #define SI32_EPCA_A_MODE_DPTR_CH3_U32 \ 171 (SI32_EPCA_A_MODE_DPTR_CH3_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 172 // The DMA channel will write to Channel 4 CCAPVUPD next. 173 #define SI32_EPCA_A_MODE_DPTR_CH4_VALUE 5 174 #define SI32_EPCA_A_MODE_DPTR_CH4_U32 \ 175 (SI32_EPCA_A_MODE_DPTR_CH4_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 176 // The DMA channel will write to Channel 5 CCAPVUPD next. 177 #define SI32_EPCA_A_MODE_DPTR_CH5_VALUE 6 178 #define SI32_EPCA_A_MODE_DPTR_CH5_U32 \ 179 (SI32_EPCA_A_MODE_DPTR_CH5_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 180 // Empty slot. 181 #define SI32_EPCA_A_MODE_DPTR_EMPTY_VALUE 7 182 #define SI32_EPCA_A_MODE_DPTR_EMPTY_U32 \ 183 (SI32_EPCA_A_MODE_DPTR_EMPTY_VALUE << SI32_EPCA_A_MODE_DPTR_SHIFT) 184 185 #define SI32_EPCA_A_MODE_DSTART_MASK 0x01C00000 186 #define SI32_EPCA_A_MODE_DSTART_SHIFT 22 187 // Set the first register in a DMA write transfer to LIMITUPD. 188 #define SI32_EPCA_A_MODE_DSTART_LIMIT_VALUE 0 189 #define SI32_EPCA_A_MODE_DSTART_LIMIT_U32 \ 190 (SI32_EPCA_A_MODE_DSTART_LIMIT_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 191 // Set the first register in a DMA write transfer to Channel 0 CCAPVUPD. 192 #define SI32_EPCA_A_MODE_DSTART_CH0_VALUE 1 193 #define SI32_EPCA_A_MODE_DSTART_CH0_U32 \ 194 (SI32_EPCA_A_MODE_DSTART_CH0_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 195 // Set the first register in a DMA write transfer to Channel 1 CCAPVUPD. 196 #define SI32_EPCA_A_MODE_DSTART_CH1_VALUE 2 197 #define SI32_EPCA_A_MODE_DSTART_CH1_U32 \ 198 (SI32_EPCA_A_MODE_DSTART_CH1_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 199 // Set the first register in a DMA write transfer to Channel 2 CCAPVUPD. 200 #define SI32_EPCA_A_MODE_DSTART_CH2_VALUE 3 201 #define SI32_EPCA_A_MODE_DSTART_CH2_U32 \ 202 (SI32_EPCA_A_MODE_DSTART_CH2_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 203 // Set the first register in a DMA write transfer to Channel 3 CCAPVUPD. 204 #define SI32_EPCA_A_MODE_DSTART_CH3_VALUE 4 205 #define SI32_EPCA_A_MODE_DSTART_CH3_U32 \ 206 (SI32_EPCA_A_MODE_DSTART_CH3_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 207 // Set the first register in a DMA write transfer to Channel 4 CCAPVUPD. 208 #define SI32_EPCA_A_MODE_DSTART_CH4_VALUE 5 209 #define SI32_EPCA_A_MODE_DSTART_CH4_U32 \ 210 (SI32_EPCA_A_MODE_DSTART_CH4_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 211 // Set the first register in a DMA write transfer to Channel 5 CCAPVUPD. 212 #define SI32_EPCA_A_MODE_DSTART_CH5_VALUE 6 213 #define SI32_EPCA_A_MODE_DSTART_CH5_U32 \ 214 (SI32_EPCA_A_MODE_DSTART_CH5_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 215 // Empty slot. 216 #define SI32_EPCA_A_MODE_DSTART_EMPTY_VALUE 7 217 #define SI32_EPCA_A_MODE_DSTART_EMPTY_U32 \ 218 (SI32_EPCA_A_MODE_DSTART_EMPTY_VALUE << SI32_EPCA_A_MODE_DSTART_SHIFT) 219 220 #define SI32_EPCA_A_MODE_DBUSYF_MASK 0x02000000 221 #define SI32_EPCA_A_MODE_DBUSYF_SHIFT 25 222 // The DMA channel is not servicing an EPCA control transfer. 223 #define SI32_EPCA_A_MODE_DBUSYF_IDLE_VALUE 0 224 #define SI32_EPCA_A_MODE_DBUSYF_IDLE_U32 \ 225 (SI32_EPCA_A_MODE_DBUSYF_IDLE_VALUE << SI32_EPCA_A_MODE_DBUSYF_SHIFT) 226 // The DMA channel is busy servicing an EPCA control transfer. 227 #define SI32_EPCA_A_MODE_DBUSYF_BUSY_VALUE 1 228 #define SI32_EPCA_A_MODE_DBUSYF_BUSY_U32 \ 229 (SI32_EPCA_A_MODE_DBUSYF_BUSY_VALUE << SI32_EPCA_A_MODE_DBUSYF_SHIFT) 230 231 #define SI32_EPCA_A_MODE_STDOSEL_MASK 0x18000000 232 #define SI32_EPCA_A_MODE_STDOSEL_SHIFT 27 233 // Select the non-differential channel outputs (Channels 0-5) for the standard PB 234 // pins. 235 #define SI32_EPCA_A_MODE_STDOSEL_NO_DIFF_VALUE 0 236 #define SI32_EPCA_A_MODE_STDOSEL_NO_DIFF_U32 \ 237 (SI32_EPCA_A_MODE_STDOSEL_NO_DIFF_VALUE << SI32_EPCA_A_MODE_STDOSEL_SHIFT) 238 // Select the differential output from Channel 2 and non-differential outputs from 239 // Channels 0, 1, 3, and 4 for the standard PB pins. 240 #define SI32_EPCA_A_MODE_STDOSEL_ONE_DIFF_VALUE 1 241 #define SI32_EPCA_A_MODE_STDOSEL_ONE_DIFF_U32 \ 242 (SI32_EPCA_A_MODE_STDOSEL_ONE_DIFF_VALUE << SI32_EPCA_A_MODE_STDOSEL_SHIFT) 243 // Select the differential outputs from Channels 1 and 2 and non-differential 244 // outputs from Channels 0 and 3 for the standard PB pins. 245 #define SI32_EPCA_A_MODE_STDOSEL_TWO_DIFF_VALUE 2 246 #define SI32_EPCA_A_MODE_STDOSEL_TWO_DIFF_U32 \ 247 (SI32_EPCA_A_MODE_STDOSEL_TWO_DIFF_VALUE << SI32_EPCA_A_MODE_STDOSEL_SHIFT) 248 // Select three differential outputs from Channels 0, 1, and 2 for the standard PB 249 // pins. 250 #define SI32_EPCA_A_MODE_STDOSEL_THREE_DIFF_VALUE 3 251 #define SI32_EPCA_A_MODE_STDOSEL_THREE_DIFF_U32 \ 252 (SI32_EPCA_A_MODE_STDOSEL_THREE_DIFF_VALUE << SI32_EPCA_A_MODE_STDOSEL_SHIFT) 253 254 255 256 struct SI32_EPCA_A_CONTROL_Struct 257 { 258 union 259 { 260 struct 261 { 262 // EPCA Counter Overflow/Limit Interrupt Enable 263 volatile uint32_t OVFIEN: 1; 264 // EPCA Counter Overflow/Limit DMA Request Enable 265 volatile uint32_t OVFDEN: 1; 266 // EPCA Counter Overflow/Limit Synchronization Signal Enable 267 volatile uint32_t OVFSEN: 1; 268 // EPCA Halt Input Interrupt Enable 269 volatile uint32_t HALTIEN: 1; 270 // Internal Register Update Inhibit 271 volatile uint32_t NOUPD: 1; 272 uint32_t reserved0: 1; 273 // EPCA Debug Mode 274 volatile uint32_t DBGMD: 1; 275 uint32_t reserved1: 2; 276 // Halt Input Enable 277 volatile uint32_t HALTEN: 1; 278 uint32_t reserved2: 1; 279 // Synchronous Input Trigger Select 280 volatile uint32_t STSEL: 2; 281 // Synchronous Input Trigger Edge Select 282 volatile uint32_t STESEL: 1; 283 // Synchronous Input Trigger Enable 284 volatile uint32_t STEN: 1; 285 uint32_t reserved3: 6; 286 // Clock Divider Output State 287 volatile uint32_t DIVST: 1; 288 // Current Clock Divider Count 289 volatile uint32_t DIV: 10; 290 }; 291 volatile uint32_t U32; 292 }; 293 }; 294 295 #define SI32_EPCA_A_CONTROL_OVFIEN_MASK 0x00000001 296 #define SI32_EPCA_A_CONTROL_OVFIEN_SHIFT 0 297 // Disable the EPCA counter overflow/limit event interrupt. 298 #define SI32_EPCA_A_CONTROL_OVFIEN_DISABLED_VALUE 0 299 #define SI32_EPCA_A_CONTROL_OVFIEN_DISABLED_U32 \ 300 (SI32_EPCA_A_CONTROL_OVFIEN_DISABLED_VALUE << SI32_EPCA_A_CONTROL_OVFIEN_SHIFT) 301 // Enable the EPCA counter overflow/limit event interrupt. 302 #define SI32_EPCA_A_CONTROL_OVFIEN_ENABLED_VALUE 1 303 #define SI32_EPCA_A_CONTROL_OVFIEN_ENABLED_U32 \ 304 (SI32_EPCA_A_CONTROL_OVFIEN_ENABLED_VALUE << SI32_EPCA_A_CONTROL_OVFIEN_SHIFT) 305 306 #define SI32_EPCA_A_CONTROL_OVFDEN_MASK 0x00000002 307 #define SI32_EPCA_A_CONTROL_OVFDEN_SHIFT 1 308 // Do not request DMA data when a EPCA counter overflow/limit event occurs. 309 #define SI32_EPCA_A_CONTROL_OVFDEN_DISABLED_VALUE 0 310 #define SI32_EPCA_A_CONTROL_OVFDEN_DISABLED_U32 \ 311 (SI32_EPCA_A_CONTROL_OVFDEN_DISABLED_VALUE << SI32_EPCA_A_CONTROL_OVFDEN_SHIFT) 312 // Request DMA data when a EPCA counter overflow/limit event occurs. 313 #define SI32_EPCA_A_CONTROL_OVFDEN_ENABLED_VALUE 1 314 #define SI32_EPCA_A_CONTROL_OVFDEN_ENABLED_U32 \ 315 (SI32_EPCA_A_CONTROL_OVFDEN_ENABLED_VALUE << SI32_EPCA_A_CONTROL_OVFDEN_SHIFT) 316 317 #define SI32_EPCA_A_CONTROL_OVFSEN_MASK 0x00000004 318 #define SI32_EPCA_A_CONTROL_OVFSEN_SHIFT 2 319 // Do not send a synchronization signal when a EPCA counter overflow/limit event 320 // occurs. 321 #define SI32_EPCA_A_CONTROL_OVFSEN_DISABLED_VALUE 0 322 #define SI32_EPCA_A_CONTROL_OVFSEN_DISABLED_U32 \ 323 (SI32_EPCA_A_CONTROL_OVFSEN_DISABLED_VALUE << SI32_EPCA_A_CONTROL_OVFSEN_SHIFT) 324 // Send a synchronization signal when a EPCA counter overflow/limit event occurs. 325 #define SI32_EPCA_A_CONTROL_OVFSEN_ENABLED_VALUE 1 326 #define SI32_EPCA_A_CONTROL_OVFSEN_ENABLED_U32 \ 327 (SI32_EPCA_A_CONTROL_OVFSEN_ENABLED_VALUE << SI32_EPCA_A_CONTROL_OVFSEN_SHIFT) 328 329 #define SI32_EPCA_A_CONTROL_HALTIEN_MASK 0x00000008 330 #define SI32_EPCA_A_CONTROL_HALTIEN_SHIFT 3 331 // Do not generate an interrupt if the EPCA halt input is high. 332 #define SI32_EPCA_A_CONTROL_HALTIEN_DISABLED_VALUE 0 333 #define SI32_EPCA_A_CONTROL_HALTIEN_DISABLED_U32 \ 334 (SI32_EPCA_A_CONTROL_HALTIEN_DISABLED_VALUE << SI32_EPCA_A_CONTROL_HALTIEN_SHIFT) 335 // Generate an interrupt if the EPCA halt input is high. 336 #define SI32_EPCA_A_CONTROL_HALTIEN_ENABLED_VALUE 1 337 #define SI32_EPCA_A_CONTROL_HALTIEN_ENABLED_U32 \ 338 (SI32_EPCA_A_CONTROL_HALTIEN_ENABLED_VALUE << SI32_EPCA_A_CONTROL_HALTIEN_SHIFT) 339 340 #define SI32_EPCA_A_CONTROL_NOUPD_MASK 0x00000010 341 #define SI32_EPCA_A_CONTROL_NOUPD_SHIFT 4 342 // The EPCA registers will automatically load any new update values after an 343 // overflow/limit event occurs. 344 #define SI32_EPCA_A_CONTROL_NOUPD_INACTIVE_VALUE 0 345 #define SI32_EPCA_A_CONTROL_NOUPD_INACTIVE_U32 \ 346 (SI32_EPCA_A_CONTROL_NOUPD_INACTIVE_VALUE << SI32_EPCA_A_CONTROL_NOUPD_SHIFT) 347 // The EPCA registers will not load any new update values after an overflow/limit 348 // event occurs. 349 #define SI32_EPCA_A_CONTROL_NOUPD_ACTIVE_VALUE 1 350 #define SI32_EPCA_A_CONTROL_NOUPD_ACTIVE_U32 \ 351 (SI32_EPCA_A_CONTROL_NOUPD_ACTIVE_VALUE << SI32_EPCA_A_CONTROL_NOUPD_SHIFT) 352 353 #define SI32_EPCA_A_CONTROL_DBGMD_MASK 0x00000040 354 #define SI32_EPCA_A_CONTROL_DBGMD_SHIFT 6 355 // A debug breakpoint will stop the EPCA counter/timer. 356 #define SI32_EPCA_A_CONTROL_DBGMD_HALT_VALUE 0 357 #define SI32_EPCA_A_CONTROL_DBGMD_HALT_U32 \ 358 (SI32_EPCA_A_CONTROL_DBGMD_HALT_VALUE << SI32_EPCA_A_CONTROL_DBGMD_SHIFT) 359 // The EPCA will continue to operate while the core is halted in debug mode. 360 #define SI32_EPCA_A_CONTROL_DBGMD_RUN_VALUE 1 361 #define SI32_EPCA_A_CONTROL_DBGMD_RUN_U32 \ 362 (SI32_EPCA_A_CONTROL_DBGMD_RUN_VALUE << SI32_EPCA_A_CONTROL_DBGMD_SHIFT) 363 364 #define SI32_EPCA_A_CONTROL_HALTEN_MASK 0x00000200 365 #define SI32_EPCA_A_CONTROL_HALTEN_SHIFT 9 366 // The Halt input (PB_HDKill) does not affect the EPCA counter/timer. 367 #define SI32_EPCA_A_CONTROL_HALTEN_DISABLED_VALUE 0 368 #define SI32_EPCA_A_CONTROL_HALTEN_DISABLED_U32 \ 369 (SI32_EPCA_A_CONTROL_HALTEN_DISABLED_VALUE << SI32_EPCA_A_CONTROL_HALTEN_SHIFT) 370 // An assertion of the Halt input (PB_HDKill) will stop the EPCA counter/timer. 371 #define SI32_EPCA_A_CONTROL_HALTEN_ENABLED_VALUE 1 372 #define SI32_EPCA_A_CONTROL_HALTEN_ENABLED_U32 \ 373 (SI32_EPCA_A_CONTROL_HALTEN_ENABLED_VALUE << SI32_EPCA_A_CONTROL_HALTEN_SHIFT) 374 375 #define SI32_EPCA_A_CONTROL_STSEL_MASK 0x00001800 376 #define SI32_EPCA_A_CONTROL_STSEL_SHIFT 11 377 // Select input trigger 0, Comparator0 output. 378 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT0_VALUE 0 379 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT0_U32 \ 380 (SI32_EPCA_A_CONTROL_STSEL_EPCANT0_VALUE << SI32_EPCA_A_CONTROL_STSEL_SHIFT) 381 // Select input trigger 1, Comparator1 output. 382 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT1_VALUE 1 383 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT1_U32 \ 384 (SI32_EPCA_A_CONTROL_STSEL_EPCANT1_VALUE << SI32_EPCA_A_CONTROL_STSEL_SHIFT) 385 // Select input trigger 2, Timer 0 high overflow. 386 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT2_VALUE 2 387 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT2_U32 \ 388 (SI32_EPCA_A_CONTROL_STSEL_EPCANT2_VALUE << SI32_EPCA_A_CONTROL_STSEL_SHIFT) 389 // Select input trigger 3, Timer 1 high overflow. 390 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT3_VALUE 3 391 #define SI32_EPCA_A_CONTROL_STSEL_EPCANT3_U32 \ 392 (SI32_EPCA_A_CONTROL_STSEL_EPCANT3_VALUE << SI32_EPCA_A_CONTROL_STSEL_SHIFT) 393 394 #define SI32_EPCA_A_CONTROL_STESEL_MASK 0x00002000 395 #define SI32_EPCA_A_CONTROL_STESEL_SHIFT 13 396 // A high-to-low transition (falling edge) on EPCAnTx will start the counter/timer. 397 #define SI32_EPCA_A_CONTROL_STESEL_FALLING_VALUE 0 398 #define SI32_EPCA_A_CONTROL_STESEL_FALLING_U32 \ 399 (SI32_EPCA_A_CONTROL_STESEL_FALLING_VALUE << SI32_EPCA_A_CONTROL_STESEL_SHIFT) 400 // A low-to-high transition (rising edge) on EPCAnTx will start the counter/timer. 401 #define SI32_EPCA_A_CONTROL_STESEL_RISING_VALUE 1 402 #define SI32_EPCA_A_CONTROL_STESEL_RISING_U32 \ 403 (SI32_EPCA_A_CONTROL_STESEL_RISING_VALUE << SI32_EPCA_A_CONTROL_STESEL_SHIFT) 404 405 #define SI32_EPCA_A_CONTROL_STEN_MASK 0x00004000 406 #define SI32_EPCA_A_CONTROL_STEN_SHIFT 14 407 // Disable the input trigger (EPCAnTx). The EPCA counter/timer will continue to run 408 // if the RUN bit is set regardless of the value on the input trigger. 409 #define SI32_EPCA_A_CONTROL_STEN_DISABLED_VALUE 0 410 #define SI32_EPCA_A_CONTROL_STEN_DISABLED_U32 \ 411 (SI32_EPCA_A_CONTROL_STEN_DISABLED_VALUE << SI32_EPCA_A_CONTROL_STEN_SHIFT) 412 // Enable the input trigger (EPCAnTx). If RUN is set to 1, the EPCA counter/timer 413 // will start running when the selected input trigger (STSEL) meets the criteria 414 // set by STESEL. It will not stop running if the criteria is no longer met. 415 #define SI32_EPCA_A_CONTROL_STEN_ENABLED_VALUE 1 416 #define SI32_EPCA_A_CONTROL_STEN_ENABLED_U32 \ 417 (SI32_EPCA_A_CONTROL_STEN_ENABLED_VALUE << SI32_EPCA_A_CONTROL_STEN_SHIFT) 418 419 #define SI32_EPCA_A_CONTROL_DIVST_MASK 0x00200000 420 #define SI32_EPCA_A_CONTROL_DIVST_SHIFT 21 421 // The clock divider is currently in the first half-cycle. 422 #define SI32_EPCA_A_CONTROL_DIVST_OUTPUT_HIGH_VALUE 0 423 #define SI32_EPCA_A_CONTROL_DIVST_OUTPUT_HIGH_U32 \ 424 (SI32_EPCA_A_CONTROL_DIVST_OUTPUT_HIGH_VALUE << SI32_EPCA_A_CONTROL_DIVST_SHIFT) 425 // The clock divider is currently in the second half-cycle. 426 #define SI32_EPCA_A_CONTROL_DIVST_OUTPUT_LOW_VALUE 1 427 #define SI32_EPCA_A_CONTROL_DIVST_OUTPUT_LOW_U32 \ 428 (SI32_EPCA_A_CONTROL_DIVST_OUTPUT_LOW_VALUE << SI32_EPCA_A_CONTROL_DIVST_SHIFT) 429 430 #define SI32_EPCA_A_CONTROL_DIV_MASK 0xFFC00000 431 #define SI32_EPCA_A_CONTROL_DIV_SHIFT 22 432 433 434 435 struct SI32_EPCA_A_STATUS_Struct 436 { 437 union 438 { 439 struct 440 { 441 // Channel 0 Capture/Compare Interrupt Flag 442 volatile uint32_t C0CCI: 1; 443 // Channel 1 Capture/Compare Interrupt Flag 444 volatile uint32_t C1CCI: 1; 445 // Channel 2 Capture/Compare Interrupt Flag 446 volatile uint32_t C2CCI: 1; 447 // Channel 3 Capture/Compare Interrupt Flag 448 volatile uint32_t C3CCI: 1; 449 // Channel 4 Capture/Compare Interrupt Flag 450 volatile uint32_t C4CCI: 1; 451 // Channel 5 Capture/Compare Interrupt Flag 452 volatile uint32_t C5CCI: 1; 453 // Counter/Timer Run 454 volatile uint32_t RUN: 1; 455 // Counter/Timer Overflow/Limit Interrupt Flag 456 volatile uint32_t OVFI: 1; 457 // Register Update Complete Flag 458 volatile uint32_t UPDCF: 1; 459 // Halt Input Interrupt Flag 460 volatile uint32_t HALTI: 1; 461 // Channel 0 Intermediate Overflow Interrupt Flag 462 volatile uint32_t C0IOVFI: 1; 463 // Channel 1 Intermediate Overflow Interrupt Flag 464 volatile uint32_t C1IOVFI: 1; 465 // Channel 2 Intermediate Overflow Interrupt Flag 466 volatile uint32_t C2IOVFI: 1; 467 // Channel 3 Intermediate Overflow Interrupt Flag 468 volatile uint32_t C3IOVFI: 1; 469 // Channel 4 Intermediate Overflow Interrupt Flag 470 volatile uint32_t C4IOVFI: 1; 471 // Channel 5 Intermediate Overflow Interrupt Flag 472 volatile uint32_t C5IOVFI: 1; 473 uint32_t reserved0: 16; 474 }; 475 volatile uint32_t U32; 476 }; 477 }; 478 479 #define SI32_EPCA_A_STATUS_C0CCI_MASK 0x00000001 480 #define SI32_EPCA_A_STATUS_C0CCI_SHIFT 0 481 // A Channel 0 match or capture event did not occur. 482 #define SI32_EPCA_A_STATUS_C0CCI_NOT_SET_VALUE 0 483 #define SI32_EPCA_A_STATUS_C0CCI_NOT_SET_U32 \ 484 (SI32_EPCA_A_STATUS_C0CCI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C0CCI_SHIFT) 485 // A Channel 0 match or capture event occurred. 486 #define SI32_EPCA_A_STATUS_C0CCI_SET_VALUE 1 487 #define SI32_EPCA_A_STATUS_C0CCI_SET_U32 \ 488 (SI32_EPCA_A_STATUS_C0CCI_SET_VALUE << SI32_EPCA_A_STATUS_C0CCI_SHIFT) 489 490 #define SI32_EPCA_A_STATUS_C1CCI_MASK 0x00000002 491 #define SI32_EPCA_A_STATUS_C1CCI_SHIFT 1 492 // A Channel 1 match or capture event did not occur. 493 #define SI32_EPCA_A_STATUS_C1CCI_NOT_SET_VALUE 0 494 #define SI32_EPCA_A_STATUS_C1CCI_NOT_SET_U32 \ 495 (SI32_EPCA_A_STATUS_C1CCI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C1CCI_SHIFT) 496 // A Channel 1 match or capture event occurred. 497 #define SI32_EPCA_A_STATUS_C1CCI_SET_VALUE 1 498 #define SI32_EPCA_A_STATUS_C1CCI_SET_U32 \ 499 (SI32_EPCA_A_STATUS_C1CCI_SET_VALUE << SI32_EPCA_A_STATUS_C1CCI_SHIFT) 500 501 #define SI32_EPCA_A_STATUS_C2CCI_MASK 0x00000004 502 #define SI32_EPCA_A_STATUS_C2CCI_SHIFT 2 503 // A Channel 2 match or capture event did not occur. 504 #define SI32_EPCA_A_STATUS_C2CCI_NOT_SET_VALUE 0 505 #define SI32_EPCA_A_STATUS_C2CCI_NOT_SET_U32 \ 506 (SI32_EPCA_A_STATUS_C2CCI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C2CCI_SHIFT) 507 // A Channel 2 match or capture event occurred. 508 #define SI32_EPCA_A_STATUS_C2CCI_SET_VALUE 1 509 #define SI32_EPCA_A_STATUS_C2CCI_SET_U32 \ 510 (SI32_EPCA_A_STATUS_C2CCI_SET_VALUE << SI32_EPCA_A_STATUS_C2CCI_SHIFT) 511 512 #define SI32_EPCA_A_STATUS_C3CCI_MASK 0x00000008 513 #define SI32_EPCA_A_STATUS_C3CCI_SHIFT 3 514 // A Channel 3 match or capture event did not occur. 515 #define SI32_EPCA_A_STATUS_C3CCI_NOT_SET_VALUE 0 516 #define SI32_EPCA_A_STATUS_C3CCI_NOT_SET_U32 \ 517 (SI32_EPCA_A_STATUS_C3CCI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C3CCI_SHIFT) 518 // A Channel 3 match or capture event occurred. 519 #define SI32_EPCA_A_STATUS_C3CCI_SET_VALUE 1 520 #define SI32_EPCA_A_STATUS_C3CCI_SET_U32 \ 521 (SI32_EPCA_A_STATUS_C3CCI_SET_VALUE << SI32_EPCA_A_STATUS_C3CCI_SHIFT) 522 523 #define SI32_EPCA_A_STATUS_C4CCI_MASK 0x00000010 524 #define SI32_EPCA_A_STATUS_C4CCI_SHIFT 4 525 // A Channel 4 match or capture event did not occur. 526 #define SI32_EPCA_A_STATUS_C4CCI_NOT_SET_VALUE 0 527 #define SI32_EPCA_A_STATUS_C4CCI_NOT_SET_U32 \ 528 (SI32_EPCA_A_STATUS_C4CCI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C4CCI_SHIFT) 529 // A Channel 4 match or capture event occurred. 530 #define SI32_EPCA_A_STATUS_C4CCI_SET_VALUE 1 531 #define SI32_EPCA_A_STATUS_C4CCI_SET_U32 \ 532 (SI32_EPCA_A_STATUS_C4CCI_SET_VALUE << SI32_EPCA_A_STATUS_C4CCI_SHIFT) 533 534 #define SI32_EPCA_A_STATUS_C5CCI_MASK 0x00000020 535 #define SI32_EPCA_A_STATUS_C5CCI_SHIFT 5 536 // A Channel 5 match or capture event did not occur. 537 #define SI32_EPCA_A_STATUS_C5CCI_NOT_SET_VALUE 0 538 #define SI32_EPCA_A_STATUS_C5CCI_NOT_SET_U32 \ 539 (SI32_EPCA_A_STATUS_C5CCI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C5CCI_SHIFT) 540 // A Channel 5 match or capture event occurred. 541 #define SI32_EPCA_A_STATUS_C5CCI_SET_VALUE 1 542 #define SI32_EPCA_A_STATUS_C5CCI_SET_U32 \ 543 (SI32_EPCA_A_STATUS_C5CCI_SET_VALUE << SI32_EPCA_A_STATUS_C5CCI_SHIFT) 544 545 #define SI32_EPCA_A_STATUS_RUN_MASK 0x00000040 546 #define SI32_EPCA_A_STATUS_RUN_SHIFT 6 547 // Stop the EPCA Counter/Timer. 548 #define SI32_EPCA_A_STATUS_RUN_STOP_VALUE 0 549 #define SI32_EPCA_A_STATUS_RUN_STOP_U32 \ 550 (SI32_EPCA_A_STATUS_RUN_STOP_VALUE << SI32_EPCA_A_STATUS_RUN_SHIFT) 551 // Start the EPCA Counter/Timer. 552 #define SI32_EPCA_A_STATUS_RUN_START_VALUE 1 553 #define SI32_EPCA_A_STATUS_RUN_START_U32 \ 554 (SI32_EPCA_A_STATUS_RUN_START_VALUE << SI32_EPCA_A_STATUS_RUN_SHIFT) 555 556 #define SI32_EPCA_A_STATUS_OVFI_MASK 0x00000080 557 #define SI32_EPCA_A_STATUS_OVFI_SHIFT 7 558 // An EPCA Counter/Timer overflow/limit event did not occur. 559 #define SI32_EPCA_A_STATUS_OVFI_NOT_SET_VALUE 0 560 #define SI32_EPCA_A_STATUS_OVFI_NOT_SET_U32 \ 561 (SI32_EPCA_A_STATUS_OVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_OVFI_SHIFT) 562 // An EPCA Counter/Timer overflow/limit event occurred. 563 #define SI32_EPCA_A_STATUS_OVFI_SET_VALUE 1 564 #define SI32_EPCA_A_STATUS_OVFI_SET_U32 \ 565 (SI32_EPCA_A_STATUS_OVFI_SET_VALUE << SI32_EPCA_A_STATUS_OVFI_SHIFT) 566 567 #define SI32_EPCA_A_STATUS_UPDCF_MASK 0x00000100 568 #define SI32_EPCA_A_STATUS_UPDCF_SHIFT 8 569 // An EPCA register update completed or is not pending. 570 #define SI32_EPCA_A_STATUS_UPDCF_EMPTY_VALUE 0 571 #define SI32_EPCA_A_STATUS_UPDCF_EMPTY_U32 \ 572 (SI32_EPCA_A_STATUS_UPDCF_EMPTY_VALUE << SI32_EPCA_A_STATUS_UPDCF_SHIFT) 573 // An EPCA register update has not completed and is still pending. 574 #define SI32_EPCA_A_STATUS_UPDCF_FULL_VALUE 1 575 #define SI32_EPCA_A_STATUS_UPDCF_FULL_U32 \ 576 (SI32_EPCA_A_STATUS_UPDCF_FULL_VALUE << SI32_EPCA_A_STATUS_UPDCF_SHIFT) 577 578 #define SI32_EPCA_A_STATUS_HALTI_MASK 0x00000200 579 #define SI32_EPCA_A_STATUS_HALTI_SHIFT 9 580 // The Halt input (PB_HDKill) was not asserted. 581 #define SI32_EPCA_A_STATUS_HALTI_NOT_SET_VALUE 0 582 #define SI32_EPCA_A_STATUS_HALTI_NOT_SET_U32 \ 583 (SI32_EPCA_A_STATUS_HALTI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_HALTI_SHIFT) 584 // The Halt input (PB_HDKill) was asserted. 585 #define SI32_EPCA_A_STATUS_HALTI_SET_VALUE 1 586 #define SI32_EPCA_A_STATUS_HALTI_SET_U32 \ 587 (SI32_EPCA_A_STATUS_HALTI_SET_VALUE << SI32_EPCA_A_STATUS_HALTI_SHIFT) 588 589 #define SI32_EPCA_A_STATUS_C0IOVFI_MASK 0x00000400 590 #define SI32_EPCA_A_STATUS_C0IOVFI_SHIFT 10 591 // Channel 0 did not count past the channel n-bit mode limit. 592 #define SI32_EPCA_A_STATUS_C0IOVFI_NOT_SET_VALUE 0 593 #define SI32_EPCA_A_STATUS_C0IOVFI_NOT_SET_U32 \ 594 (SI32_EPCA_A_STATUS_C0IOVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C0IOVFI_SHIFT) 595 // Channel 0 counted past the channel n-bit mode limit. 596 #define SI32_EPCA_A_STATUS_C0IOVFI_SET_VALUE 1 597 #define SI32_EPCA_A_STATUS_C0IOVFI_SET_U32 \ 598 (SI32_EPCA_A_STATUS_C0IOVFI_SET_VALUE << SI32_EPCA_A_STATUS_C0IOVFI_SHIFT) 599 600 #define SI32_EPCA_A_STATUS_C1IOVFI_MASK 0x00000800 601 #define SI32_EPCA_A_STATUS_C1IOVFI_SHIFT 11 602 // Channel 1 did not count past the channel n-bit mode limit. 603 #define SI32_EPCA_A_STATUS_C1IOVFI_NOT_SET_VALUE 0 604 #define SI32_EPCA_A_STATUS_C1IOVFI_NOT_SET_U32 \ 605 (SI32_EPCA_A_STATUS_C1IOVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C1IOVFI_SHIFT) 606 // Channel 1 counted past the channel n-bit mode limit. 607 #define SI32_EPCA_A_STATUS_C1IOVFI_SET_VALUE 1 608 #define SI32_EPCA_A_STATUS_C1IOVFI_SET_U32 \ 609 (SI32_EPCA_A_STATUS_C1IOVFI_SET_VALUE << SI32_EPCA_A_STATUS_C1IOVFI_SHIFT) 610 611 #define SI32_EPCA_A_STATUS_C2IOVFI_MASK 0x00001000 612 #define SI32_EPCA_A_STATUS_C2IOVFI_SHIFT 12 613 // Channel 2 did not count past the channel n-bit mode limit. 614 #define SI32_EPCA_A_STATUS_C2IOVFI_NOT_SET_VALUE 0 615 #define SI32_EPCA_A_STATUS_C2IOVFI_NOT_SET_U32 \ 616 (SI32_EPCA_A_STATUS_C2IOVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C2IOVFI_SHIFT) 617 // Channel 2 counted past the channel n-bit mode limit. 618 #define SI32_EPCA_A_STATUS_C2IOVFI_SET_VALUE 1 619 #define SI32_EPCA_A_STATUS_C2IOVFI_SET_U32 \ 620 (SI32_EPCA_A_STATUS_C2IOVFI_SET_VALUE << SI32_EPCA_A_STATUS_C2IOVFI_SHIFT) 621 622 #define SI32_EPCA_A_STATUS_C3IOVFI_MASK 0x00002000 623 #define SI32_EPCA_A_STATUS_C3IOVFI_SHIFT 13 624 // Channel 3 did not count past the channel n-bit mode limit. 625 #define SI32_EPCA_A_STATUS_C3IOVFI_NOT_SET_VALUE 0 626 #define SI32_EPCA_A_STATUS_C3IOVFI_NOT_SET_U32 \ 627 (SI32_EPCA_A_STATUS_C3IOVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C3IOVFI_SHIFT) 628 // Channel 3 counted past the channel n-bit mode limit. 629 #define SI32_EPCA_A_STATUS_C3IOVFI_SET_VALUE 1 630 #define SI32_EPCA_A_STATUS_C3IOVFI_SET_U32 \ 631 (SI32_EPCA_A_STATUS_C3IOVFI_SET_VALUE << SI32_EPCA_A_STATUS_C3IOVFI_SHIFT) 632 633 #define SI32_EPCA_A_STATUS_C4IOVFI_MASK 0x00004000 634 #define SI32_EPCA_A_STATUS_C4IOVFI_SHIFT 14 635 // Channel 4 did not count past the channel n-bit mode limit. 636 #define SI32_EPCA_A_STATUS_C4IOVFI_NOT_SET_VALUE 0 637 #define SI32_EPCA_A_STATUS_C4IOVFI_NOT_SET_U32 \ 638 (SI32_EPCA_A_STATUS_C4IOVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C4IOVFI_SHIFT) 639 // Channel 4 counted past the channel n-bit mode limit. 640 #define SI32_EPCA_A_STATUS_C4IOVFI_SET_VALUE 1 641 #define SI32_EPCA_A_STATUS_C4IOVFI_SET_U32 \ 642 (SI32_EPCA_A_STATUS_C4IOVFI_SET_VALUE << SI32_EPCA_A_STATUS_C4IOVFI_SHIFT) 643 644 #define SI32_EPCA_A_STATUS_C5IOVFI_MASK 0x00008000 645 #define SI32_EPCA_A_STATUS_C5IOVFI_SHIFT 15 646 // Channel 5 did not count past the channel n-bit mode limit. 647 #define SI32_EPCA_A_STATUS_C5IOVFI_NOT_SET_VALUE 0 648 #define SI32_EPCA_A_STATUS_C5IOVFI_NOT_SET_U32 \ 649 (SI32_EPCA_A_STATUS_C5IOVFI_NOT_SET_VALUE << SI32_EPCA_A_STATUS_C5IOVFI_SHIFT) 650 // Channel 5 counted past the channel n-bit mode limit. 651 #define SI32_EPCA_A_STATUS_C5IOVFI_SET_VALUE 1 652 #define SI32_EPCA_A_STATUS_C5IOVFI_SET_U32 \ 653 (SI32_EPCA_A_STATUS_C5IOVFI_SET_VALUE << SI32_EPCA_A_STATUS_C5IOVFI_SHIFT) 654 655 656 657 struct SI32_EPCA_A_COUNTER_Struct 658 { 659 union 660 { 661 struct 662 { 663 // Counter/Timer 664 volatile uint16_t COUNTER_BITS; 665 uint32_t reserved0: 16; 666 }; 667 volatile uint32_t U32; 668 }; 669 }; 670 671 #define SI32_EPCA_A_COUNTER_COUNTER_MASK 0x0000FFFF 672 #define SI32_EPCA_A_COUNTER_COUNTER_SHIFT 0 673 674 675 676 struct SI32_EPCA_A_LIMIT_Struct 677 { 678 union 679 { 680 struct 681 { 682 // Upper Limit 683 volatile uint16_t LIMIT_BITS; 684 uint32_t reserved0: 16; 685 }; 686 volatile uint32_t U32; 687 }; 688 }; 689 690 #define SI32_EPCA_A_LIMIT_LIMIT_MASK 0x0000FFFF 691 #define SI32_EPCA_A_LIMIT_LIMIT_SHIFT 0 692 693 694 695 struct SI32_EPCA_A_LIMITUPD_Struct 696 { 697 union 698 { 699 struct 700 { 701 // Module Upper Limit Update Value 702 volatile uint16_t LIMITUPD_BITS; 703 uint32_t reserved0: 16; 704 }; 705 volatile uint32_t U32; 706 }; 707 }; 708 709 #define SI32_EPCA_A_LIMITUPD_LIMITUPD_MASK 0x0000FFFF 710 #define SI32_EPCA_A_LIMITUPD_LIMITUPD_SHIFT 0 711 712 713 714 struct SI32_EPCA_A_DTIME_Struct 715 { 716 union 717 { 718 struct 719 { 720 // X Phase Delay Time 721 volatile uint8_t DTIMEX; 722 // Y Phase Delay Time 723 volatile uint8_t DTIMEY; 724 uint32_t reserved0: 16; 725 }; 726 volatile uint32_t U32; 727 }; 728 }; 729 730 #define SI32_EPCA_A_DTIME_DTIMEX_MASK 0x000000FF 731 #define SI32_EPCA_A_DTIME_DTIMEX_SHIFT 0 732 733 #define SI32_EPCA_A_DTIME_DTIMEY_MASK 0x0000FF00 734 #define SI32_EPCA_A_DTIME_DTIMEY_SHIFT 8 735 736 737 738 struct SI32_EPCA_A_DTARGET_Struct 739 { 740 union 741 { 742 struct 743 { 744 // DMA Transfer Target 745 volatile uint32_t DTARGET_BITS; 746 }; 747 volatile uint32_t U32; 748 }; 749 }; 750 751 #define SI32_EPCA_A_DTARGET_DTARGET_MASK 0xFFFFFFFF 752 #define SI32_EPCA_A_DTARGET_DTARGET_SHIFT 0 753 754 755 756 typedef struct SI32_EPCA_A_Struct 757 { 758 struct SI32_EPCA_A_MODE_Struct MODE ; // Base Address + 0x0 759 uint32_t reserved0; 760 uint32_t reserved1; 761 uint32_t reserved2; 762 struct SI32_EPCA_A_CONTROL_Struct CONTROL ; // Base Address + 0x10 763 volatile uint32_t CONTROL_SET; 764 volatile uint32_t CONTROL_CLR; 765 uint32_t reserved3; 766 struct SI32_EPCA_A_STATUS_Struct STATUS ; // Base Address + 0x20 767 volatile uint32_t STATUS_SET; 768 volatile uint32_t STATUS_CLR; 769 uint32_t reserved4; 770 struct SI32_EPCA_A_COUNTER_Struct COUNTER ; // Base Address + 0x30 771 uint32_t reserved5; 772 uint32_t reserved6; 773 uint32_t reserved7; 774 struct SI32_EPCA_A_LIMIT_Struct LIMIT ; // Base Address + 0x40 775 uint32_t reserved8; 776 uint32_t reserved9; 777 uint32_t reserved10; 778 struct SI32_EPCA_A_LIMITUPD_Struct LIMITUPD ; // Base Address + 0x50 779 uint32_t reserved11; 780 uint32_t reserved12; 781 uint32_t reserved13; 782 struct SI32_EPCA_A_DTIME_Struct DTIME ; // Base Address + 0x60 783 uint32_t reserved14; 784 uint32_t reserved15; 785 uint32_t reserved16; 786 uint32_t reserved17[4]; 787 struct SI32_EPCA_A_DTARGET_Struct DTARGET ; // Base Address + 0x80 788 uint32_t reserved18; 789 uint32_t reserved19; 790 uint32_t reserved20; 791 } SI32_EPCA_A_Type; 792 793 #ifdef __cplusplus 794 } 795 #endif 796 797 #endif // __SI32_EPCA_A_REGISTERS_H__ 798 799 //-eof-------------------------------------------------------------------------- 800 801
