Searched refs:SI32_EPCA_A_CONTROL_DIVST_MASK (Results 1 – 3 of 3) sorted by relevance
897 (basePointer->CONTROL_CLR = SI32_EPCA_A_CONTROL_DIVST_MASK)913 (basePointer->CONTROL_SET = SI32_EPCA_A_CONTROL_DIVST_MASK)
757 basePointer->CONTROL_CLR = SI32_EPCA_A_CONTROL_DIVST_MASK; in _SI32_EPCA_A_select_clock_divider_state_phase_1()771 basePointer->CONTROL_SET = SI32_EPCA_A_CONTROL_DIVST_MASK; in _SI32_EPCA_A_select_clock_divider_state_phase_2()
419 #define SI32_EPCA_A_CONTROL_DIVST_MASK 0x00200000 macro
