1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // This file applies to the SIM3L1XX_DMAXBAR_A module 24 // 25 // Version: 1 26 27 #ifndef __SI32_DMAXBAR_A_Support_Guard__ 28 #define __SI32_DMAXBAR_A_Support_Guard__ 29 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 //----------------------------------------------------------------------------- 37 // Define the number of DMA channels. 38 39 #define SI32_DMACTRL_NUM_CHANNELS 10 40 41 //----------------------------------------------------------------------------- 42 // Define the DMA Crossbar Channel Select Enum Type 43 44 typedef enum SI32_DMAXBAR_CHNSEL_Enum 45 { 46 SI32_DMAXBAR_CHAN0_DTM0_A = 0x00, 47 SI32_DMAXBAR_CHAN0_SPI0_TX = 0x01, 48 SI32_DMAXBAR_CHAN0_AES0_TX = 0x02, 49 SI32_DMAXBAR_CHAN0_USART0_RX = 0x03, 50 SI32_DMAXBAR_CHAN0_I2C0_RX = 0x04, 51 SI32_DMAXBAR_CHAN0_I2C0_TX = 0x05, 52 SI32_DMAXBAR_CHAN0_EPCA0_CAPTURE = 0x06, 53 SI32_DMAXBAR_CHAN0_TIMER0L = 0x07, 54 SI32_DMAXBAR_CHAN0_TIMER0H = 0x08, 55 SI32_DMAXBAR_CHAN0_DMA0T0_RISE = 0x09, 56 SI32_DMAXBAR_CHAN0_DMA0T0_FALL = 0x0A, 57 SI32_DMAXBAR_CHAN0_NONE = 0x0F, 58 59 SI32_DMAXBAR_CHAN1_DTM0_B = 0x10, 60 SI32_DMAXBAR_CHAN1_SPI0_RX = 0x11, 61 SI32_DMAXBAR_CHAN1_AES0_RX = 0x12, 62 SI32_DMAXBAR_CHAN1_USART0_TX = 0x13, 63 SI32_DMAXBAR_CHAN1_SARADC0 = 0x14, 64 SI32_DMAXBAR_CHAN1_EPCA0_CAPTURE = 0x15, 65 SI32_DMAXBAR_CHAN1_EPCA0_CONTROL = 0x16, 66 SI32_DMAXBAR_CHAN1_TIMER1L = 0x17, 67 SI32_DMAXBAR_CHAN1_TIMER1H = 0x18, 68 SI32_DMAXBAR_CHAN1_DMA0T1_RISE = 0x19, 69 SI32_DMAXBAR_CHAN1_DMA0T1_FALL = 0x1A, 70 SI32_DMAXBAR_CHAN1_NONE = 0x1F, 71 72 SI32_DMAXBAR_CHAN2_DTM0_C = 0x20, 73 SI32_DMAXBAR_CHAN2_DTM2_A = 0x21, 74 SI32_DMAXBAR_CHAN2_ENCDEC0_TX = 0x22, 75 SI32_DMAXBAR_CHAN2_AES0_XOR = 0x23, 76 SI32_DMAXBAR_CHAN2_SPI1_TX = 0x24, 77 SI32_DMAXBAR_CHAN2_USART0_RX = 0x25, 78 SI32_DMAXBAR_CHAN2_I2C0_RX = 0x26, 79 SI32_DMAXBAR_CHAN2_IDAC0 = 0x27, 80 SI32_DMAXBAR_CHAN2_TIMER0L = 0x28, 81 SI32_DMAXBAR_CHAN2_TIMER0H = 0x29, 82 SI32_DMAXBAR_CHAN2_DMA0T0_RISE = 0x2A, 83 SI32_DMAXBAR_CHAN2_DMA0T0_FALL = 0x2B, 84 SI32_DMAXBAR_CHAN2_NONE = 0x2F, 85 86 SI32_DMAXBAR_CHAN3_DTM0_D = 0x30, 87 SI32_DMAXBAR_CHAN3_DTM2_B = 0x31, 88 SI32_DMAXBAR_CHAN3_ENCDEC0_RX = 0x32, 89 SI32_DMAXBAR_CHAN3_SPI1_RX = 0x33, 90 SI32_DMAXBAR_CHAN3_USART0_TX = 0x34, 91 SI32_DMAXBAR_CHAN3_I2C0_RX = 0x35, 92 SI32_DMAXBAR_CHAN3_I2C0_TX = 0x36, 93 SI32_DMAXBAR_CHAN3_TIMER1L = 0x37, 94 SI32_DMAXBAR_CHAN3_TIMER1H = 0x38, 95 SI32_DMAXBAR_CHAN3_DMA0T1_RISE = 0x39, 96 SI32_DMAXBAR_CHAN3_DMA0T1_FALL = 0x3A, 97 SI32_DMAXBAR_CHAN3_NONE = 0x3F, 98 99 SI32_DMAXBAR_CHAN4_DTM1_A = 0x40, 100 SI32_DMAXBAR_CHAN4_DTM2_C = 0x41, 101 SI32_DMAXBAR_CHAN4_SPI0_TX = 0x42, 102 SI32_DMAXBAR_CHAN4_AES0_TX = 0x43, 103 SI32_DMAXBAR_CHAN4_SARADC0 = 0x44, 104 SI32_DMAXBAR_CHAN4_EPCA0_CAPTURE = 0x45, 105 SI32_DMAXBAR_CHAN4_EPCA0_CONTROL = 0x46, 106 SI32_DMAXBAR_CHAN4_TIMER0L = 0x47, 107 SI32_DMAXBAR_CHAN4_TIMER0H = 0x48, 108 SI32_DMAXBAR_CHAN4_DMA0T0_RISE = 0x49, 109 SI32_DMAXBAR_CHAN4_DMA0T0_FALL = 0x4A, 110 SI32_DMAXBAR_CHAN4_NONE = 0x4F, 111 112 SI32_DMAXBAR_CHAN5_DTM1_B = 0x50, 113 SI32_DMAXBAR_CHAN5_DTM2_D = 0x51, 114 SI32_DMAXBAR_CHAN5_SPI0_RX = 0x52, 115 SI32_DMAXBAR_CHAN5_AES0_RX = 0x53, 116 SI32_DMAXBAR_CHAN5_USART0_RX = 0x54, 117 SI32_DMAXBAR_CHAN5_I2C0_RX = 0x55, 118 SI32_DMAXBAR_CHAN5_IDAC0 = 0x56, 119 SI32_DMAXBAR_CHAN5_EPCA0_CONTROL = 0x57, 120 SI32_DMAXBAR_CHAN5_TIMER1L = 0x58, 121 SI32_DMAXBAR_CHAN5_TIMER1H = 0x59, 122 SI32_DMAXBAR_CHAN5_DMA0T1_RISE = 0x5A, 123 SI32_DMAXBAR_CHAN5_DMA0T1_FALL = 0x5B, 124 SI32_DMAXBAR_CHAN5_NONE = 0x5F, 125 126 SI32_DMAXBAR_CHAN6_DTM1_C = 0x60, 127 SI32_DMAXBAR_CHAN6_DTM2_A = 0x61, 128 SI32_DMAXBAR_CHAN6_ENCDEC0_TX = 0x62, 129 SI32_DMAXBAR_CHAN6_AES0_XOR = 0x63, 130 SI32_DMAXBAR_CHAN6_USART0_TX = 0x64, 131 SI32_DMAXBAR_CHAN6_I2C0_RX = 0x65, 132 SI32_DMAXBAR_CHAN6_I2C0_TX = 0x66, 133 SI32_DMAXBAR_CHAN6_SARADC0 = 0x67, 134 SI32_DMAXBAR_CHAN6_TIMER0L = 0x68, 135 SI32_DMAXBAR_CHAN6_TIMER0H = 0x69, 136 SI32_DMAXBAR_CHAN6_DMA0T0_RISE = 0x6A, 137 SI32_DMAXBAR_CHAN6_DMA0T0_FALL = 0x6B, 138 SI32_DMAXBAR_CHAN6_NONE = 0x6F, 139 140 SI32_DMAXBAR_CHAN7_DTM1_D = 0x70, 141 SI32_DMAXBAR_CHAN7_DTM2_B = 0x71, 142 SI32_DMAXBAR_CHAN7_ENCDEC0_RX = 0x72, 143 SI32_DMAXBAR_CHAN7_SPI1_TX = 0x73, 144 SI32_DMAXBAR_CHAN7_USART0_RX = 0x74, 145 SI32_DMAXBAR_CHAN7_IDAC0 = 0x75, 146 SI32_DMAXBAR_CHAN7_TIMER1L = 0x76, 147 SI32_DMAXBAR_CHAN7_TIMER1H = 0x77, 148 SI32_DMAXBAR_CHAN7_DMA0T1_RISE = 0x78, 149 SI32_DMAXBAR_CHAN7_DMA0T1_FALL = 0x79, 150 SI32_DMAXBAR_CHAN7_NONE = 0x7F, 151 152 SI32_DMAXBAR_CHAN8_DTM2_C = 0x80, 153 SI32_DMAXBAR_CHAN8_SPI0_TX = 0x81, 154 SI32_DMAXBAR_CHAN8_SPI1_RX = 0x82, 155 SI32_DMAXBAR_CHAN8_USART0_TX = 0x83, 156 SI32_DMAXBAR_CHAN8_I2C0_RX = 0x84, 157 SI32_DMAXBAR_CHAN8_SARADC0 = 0x85, 158 SI32_DMAXBAR_CHAN8_EPCA0_CAPTURE = 0x86, 159 SI32_DMAXBAR_CHAN8_TIMER0L = 0x87, 160 SI32_DMAXBAR_CHAN8_TIMER0H = 0x88, 161 SI32_DMAXBAR_CHAN8_DMA0T0_RISE = 0x89, 162 SI32_DMAXBAR_CHAN8_DMA0T0_FALL = 0x8A, 163 SI32_DMAXBAR_CHAN8_NONE = 0x8F, 164 165 SI32_DMAXBAR_CHAN9_DTM2_D = 0x90, 166 SI32_DMAXBAR_CHAN9_SPI0_RX = 0x91, 167 SI32_DMAXBAR_CHAN9_I2C0_RX = 0x92, 168 SI32_DMAXBAR_CHAN9_I2C0_TX = 0x93, 169 SI32_DMAXBAR_CHAN9_IDAC0 = 0x94, 170 SI32_DMAXBAR_CHAN9_EPCA0_CAPTURE = 0x95, 171 SI32_DMAXBAR_CHAN9_EPCA0_CONTROL = 0x96, 172 SI32_DMAXBAR_CHAN9_TIMER1L = 0x97, 173 SI32_DMAXBAR_CHAN9_TIMER1H = 0x98, 174 SI32_DMAXBAR_CHAN9_DMA0T1_RISE = 0x99, 175 SI32_DMAXBAR_CHAN9_DMA0T1_FALL = 0x9A, 176 SI32_DMAXBAR_CHAN9_NONE = 0x9F 177 } 178 SI32_DMAXBAR_CHNSEL_Enum_Type; 179 180 // Extracts DMA channel number from SI32_DMAXBAR_CHNSEL_Enum_Type 181 #define SI32_DMAXBAR_CHANNEL_OF(chsel) (((chsel) & 0xF0) >> 4) 182 183 //----------------------------------------------------------------------------- 184 // Define the DMA Endpoints 185 186 #define SI32_ADC_0_RX_ENDPOINT &SI32_ADC_0->DATA.U32 187 #define SI32_AES_0_TX_ENDPOINT &SI32_AES_0->DATAFIFO.U32 188 #define SI32_AES_0_RX_ENDPOINT &SI32_AES_0->DATAFIFO.U32 189 #define SI32_AES_0_XOR_ENDPOINT &SI32_AES_0->XORFIFO.U32 190 #define SI32_ENCDEC_0_RX_ENDPOINT &SI32_ENCDEC_0->DATAOUT.U32 191 #define SI32_ENCDEC_0_TX_ENDPOINT &SI32_ENCDEC_0->DATAIN.U32 192 #define SI32_EPCA_0_CH0_RX_ENDPOINT &SI32_EPCA_0_CH0->CCAPV.U32 193 #define SI32_EPCA_0_CH1_RX_ENDPOINT &SI32_EPCA_0_CH1->CCAPV.U32 194 #define SI32_EPCA_0_CH2_RX_ENDPOINT &SI32_EPCA_0_CH2->CCAPV.U32 195 #define SI32_EPCA_0_CH3_RX_ENDPOINT &SI32_EPCA_0_CH3->CCAPV.U32 196 #define SI32_EPCA_0_CH4_RX_ENDPOINT &SI32_EPCA_0_CH4->CCAPV.U32 197 #define SI32_EPCA_0_CH5_RX_ENDPOINT &SI32_EPCA_0_CH5->CCAPV.U32 198 #define SI32_EPCA_0_TX_ENDPOINT &SI32_EPCA_0->DTARGET.U32 199 #define SI32_EPCA_0_CH0_TX_ENDPOINT &SI32_EPCA_0_CH0->CCAPVUPD.U32 200 #define SI32_EPCA_0_CH1_TX_ENDPOINT &SI32_EPCA_0_CH1->CCAPVUPD.U32 201 #define SI32_EPCA_0_CH2_TX_ENDPOINT &SI32_EPCA_0_CH2->CCAPVUPD.U32 202 #define SI32_EPCA_0_CH3_TX_ENDPOINT &SI32_EPCA_0_CH3->CCAPVUPD.U32 203 #define SI32_EPCA_0_CH4_TX_ENDPOINT &SI32_EPCA_0_CH4->CCAPVUPD.U32 204 #define SI32_EPCA_0_CH5_TX_ENDPOINT &SI32_EPCA_0_CH5->CCAPVUPD.U32 205 #define SI32_I2C_0_RX_ENDPOINT &SI32_I2C_0->DATA.U32 206 #define SI32_I2C_0_TX_ENDPOINT &SI32_I2C_0->DATA.U32 207 #define SI32_IDAC_0_TX_ENDPOINT &SI32_IDAC_0->DATA.U32 208 #define SI32_SPI_0_RX_ENDPOINT &SI32_SPI_0->DATA.U32 209 #define SI32_SPI_0_TX_ENDPOINT &SI32_SPI_0->DATA.U32 210 #define SI32_SPI_1_RX_ENDPOINT &SI32_SPI_1->DATA.U32 211 #define SI32_SPI_1_TX_ENDPOINT &SI32_SPI_1->DATA.U32 212 #define SI32_USART_0_RX_ENDPOINT &SI32_USART_0->DATA.U32 213 #define SI32_USART_0_TX_ENDPOINT &SI32_USART_0->DATA.U32 214 215 #ifdef __cplusplus 216 } 217 #endif 218 219 #endif // __SI32_DMAXBAR_A_Support_Guard__ 220 221 //-eof-------------------------------------------------------------------------- 222
