1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_ECRC_A_REGISTERS_H__ 27 #define __SI32_ECRC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_ECRC_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Seed Initialization Enable 42 volatile uint32_t SINITEN: 1; 43 // Seed Setting 44 volatile uint32_t SEED: 1; 45 // CRC Enable 46 volatile uint32_t CRCEN: 1; 47 uint32_t reserved0: 1; 48 // Polynomial Selection 49 volatile uint32_t POLYSEL: 1; 50 uint32_t reserved1: 3; 51 // Byte Mode Enable 52 volatile uint32_t BMDEN: 1; 53 // Byte-Level Bit Reversal Enable 54 volatile uint32_t BBREN: 1; 55 // Input Processing Order 56 volatile uint32_t ORDER: 2; 57 uint32_t reserved2: 1; 58 // Automatic Seed Enable 59 volatile uint32_t ASEEDEN: 1; 60 // Automatic Seed Byte Select 61 volatile uint32_t ASEEDSEL: 1; 62 uint32_t reserved3: 17; 63 }; 64 volatile uint32_t U32; 65 }; 66 }; 67 68 #define SI32_ECRC_A_CONTROL_SINITEN_MASK 0x00000001 69 #define SI32_ECRC_A_CONTROL_SINITEN_SHIFT 0 70 // Do not initialize the CRC module to the value set by the SEED bit. 71 #define SI32_ECRC_A_CONTROL_SINITEN_DISABLED_VALUE 0 72 #define SI32_ECRC_A_CONTROL_SINITEN_DISABLED_U32 \ 73 (SI32_ECRC_A_CONTROL_SINITEN_DISABLED_VALUE << SI32_ECRC_A_CONTROL_SINITEN_SHIFT) 74 // Initialize the CRC module to the value set by the SEED bit. 75 #define SI32_ECRC_A_CONTROL_SINITEN_ENABLED_VALUE 1 76 #define SI32_ECRC_A_CONTROL_SINITEN_ENABLED_U32 \ 77 (SI32_ECRC_A_CONTROL_SINITEN_ENABLED_VALUE << SI32_ECRC_A_CONTROL_SINITEN_SHIFT) 78 79 #define SI32_ECRC_A_CONTROL_SEED_MASK 0x00000002 80 #define SI32_ECRC_A_CONTROL_SEED_SHIFT 1 81 // CRC seed value is all 0's (0x00000000) 82 #define SI32_ECRC_A_CONTROL_SEED_ALL_ZEROES_VALUE 0 83 #define SI32_ECRC_A_CONTROL_SEED_ALL_ZEROES_U32 \ 84 (SI32_ECRC_A_CONTROL_SEED_ALL_ZEROES_VALUE << SI32_ECRC_A_CONTROL_SEED_SHIFT) 85 // CRC seed value is all 1's (0xFFFFFFFF). 86 #define SI32_ECRC_A_CONTROL_SEED_ALL_ONES_VALUE 1 87 #define SI32_ECRC_A_CONTROL_SEED_ALL_ONES_U32 \ 88 (SI32_ECRC_A_CONTROL_SEED_ALL_ONES_VALUE << SI32_ECRC_A_CONTROL_SEED_SHIFT) 89 90 #define SI32_ECRC_A_CONTROL_CRCEN_MASK 0x00000004 91 #define SI32_ECRC_A_CONTROL_CRCEN_SHIFT 2 92 // Disable CRC operations. 93 #define SI32_ECRC_A_CONTROL_CRCEN_DISABLED_VALUE 0 94 #define SI32_ECRC_A_CONTROL_CRCEN_DISABLED_U32 \ 95 (SI32_ECRC_A_CONTROL_CRCEN_DISABLED_VALUE << SI32_ECRC_A_CONTROL_CRCEN_SHIFT) 96 // Enable CRC operations. 97 #define SI32_ECRC_A_CONTROL_CRCEN_ENABLED_VALUE 1 98 #define SI32_ECRC_A_CONTROL_CRCEN_ENABLED_U32 \ 99 (SI32_ECRC_A_CONTROL_CRCEN_ENABLED_VALUE << SI32_ECRC_A_CONTROL_CRCEN_SHIFT) 100 101 #define SI32_ECRC_A_CONTROL_POLYSEL_MASK 0x00000010 102 #define SI32_ECRC_A_CONTROL_POLYSEL_SHIFT 4 103 // Select the fixed 32-bit polynomial: 0x04C11DB7. 104 #define SI32_ECRC_A_CONTROL_POLYSEL_CRC32_FIXED_VALUE 0 105 #define SI32_ECRC_A_CONTROL_POLYSEL_CRC32_FIXED_U32 \ 106 (SI32_ECRC_A_CONTROL_POLYSEL_CRC32_FIXED_VALUE << SI32_ECRC_A_CONTROL_POLYSEL_SHIFT) 107 // Select the programmable 16-bit polynomial. The POLY register sets the polynomial 108 // coefficients. 109 #define SI32_ECRC_A_CONTROL_POLYSEL_CRC16_PROG_VALUE 1 110 #define SI32_ECRC_A_CONTROL_POLYSEL_CRC16_PROG_U32 \ 111 (SI32_ECRC_A_CONTROL_POLYSEL_CRC16_PROG_VALUE << SI32_ECRC_A_CONTROL_POLYSEL_SHIFT) 112 113 #define SI32_ECRC_A_CONTROL_BMDEN_MASK 0x00000100 114 #define SI32_ECRC_A_CONTROL_BMDEN_SHIFT 8 115 // Disable byte mode (word/byte width is determined automatically by the hardware). 116 #define SI32_ECRC_A_CONTROL_BMDEN_DISABLED_VALUE 0 117 #define SI32_ECRC_A_CONTROL_BMDEN_DISABLED_U32 \ 118 (SI32_ECRC_A_CONTROL_BMDEN_DISABLED_VALUE << SI32_ECRC_A_CONTROL_BMDEN_SHIFT) 119 // Enable byte mode (all writes are considered as bytes). 120 #define SI32_ECRC_A_CONTROL_BMDEN_ENABLED_VALUE 1 121 #define SI32_ECRC_A_CONTROL_BMDEN_ENABLED_U32 \ 122 (SI32_ECRC_A_CONTROL_BMDEN_ENABLED_VALUE << SI32_ECRC_A_CONTROL_BMDEN_SHIFT) 123 124 #define SI32_ECRC_A_CONTROL_BBREN_MASK 0x00000200 125 #define SI32_ECRC_A_CONTROL_BBREN_SHIFT 9 126 // No byte-level bit reversal (input is same order as written). 127 #define SI32_ECRC_A_CONTROL_BBREN_DISABLED_VALUE 0 128 #define SI32_ECRC_A_CONTROL_BBREN_DISABLED_U32 \ 129 (SI32_ECRC_A_CONTROL_BBREN_DISABLED_VALUE << SI32_ECRC_A_CONTROL_BBREN_SHIFT) 130 // Byte-level bit reversal enabled (the bits in each byte are reversed). 131 #define SI32_ECRC_A_CONTROL_BBREN_ENABLED_VALUE 1 132 #define SI32_ECRC_A_CONTROL_BBREN_ENABLED_U32 \ 133 (SI32_ECRC_A_CONTROL_BBREN_ENABLED_VALUE << SI32_ECRC_A_CONTROL_BBREN_SHIFT) 134 135 #define SI32_ECRC_A_CONTROL_ORDER_MASK 0x00000C00 136 #define SI32_ECRC_A_CONTROL_ORDER_SHIFT 10 137 // No byte reorientation (output is same order as input). 138 #define SI32_ECRC_A_CONTROL_ORDER_NO_REORDER_VALUE 0 139 #define SI32_ECRC_A_CONTROL_ORDER_NO_REORDER_U32 \ 140 (SI32_ECRC_A_CONTROL_ORDER_NO_REORDER_VALUE << SI32_ECRC_A_CONTROL_ORDER_SHIFT) 141 // Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1). 142 #define SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_16_VALUE 1 143 #define SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_16_U32 \ 144 (SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_16_VALUE << SI32_ECRC_A_CONTROL_ORDER_SHIFT) 145 // Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3). 146 #define SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_32_VALUE 2 147 #define SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_32_U32 \ 148 (SI32_ECRC_A_CONTROL_ORDER_BIG_ENDIAN_32_VALUE << SI32_ECRC_A_CONTROL_ORDER_SHIFT) 149 150 #define SI32_ECRC_A_CONTROL_ASEEDEN_MASK 0x00002000 151 #define SI32_ECRC_A_CONTROL_ASEEDEN_SHIFT 13 152 // Disable automatic seeding. 153 #define SI32_ECRC_A_CONTROL_ASEEDEN_DISABLED_VALUE 0 154 #define SI32_ECRC_A_CONTROL_ASEEDEN_DISABLED_U32 \ 155 (SI32_ECRC_A_CONTROL_ASEEDEN_DISABLED_VALUE << SI32_ECRC_A_CONTROL_ASEEDEN_SHIFT) 156 // Enable automatic seeding. Reading the byte of the DATA register selected by 157 // ASEEDSEL re-seeds the CRC result with the setting selected by SEED. 158 #define SI32_ECRC_A_CONTROL_ASEEDEN_ENABLED_VALUE 1 159 #define SI32_ECRC_A_CONTROL_ASEEDEN_ENABLED_U32 \ 160 (SI32_ECRC_A_CONTROL_ASEEDEN_ENABLED_VALUE << SI32_ECRC_A_CONTROL_ASEEDEN_SHIFT) 161 162 #define SI32_ECRC_A_CONTROL_ASEEDSEL_MASK 0x00004000 163 #define SI32_ECRC_A_CONTROL_ASEEDSEL_SHIFT 14 164 // Select a read of the least-significant byte ([7:0]) of DATA, RDATA or BRDATA for 165 // automatic re-seeding. 166 #define SI32_ECRC_A_CONTROL_ASEEDSEL_LSB_READ_VALUE 0 167 #define SI32_ECRC_A_CONTROL_ASEEDSEL_LSB_READ_U32 \ 168 (SI32_ECRC_A_CONTROL_ASEEDSEL_LSB_READ_VALUE << SI32_ECRC_A_CONTROL_ASEEDSEL_SHIFT) 169 // Select a read of the most-significant byte [31:24] for 32-bit operations, and 170 // [15:8] for 16-bit operations) of DATA, RDATA or BRDATA for automatic re-seeding. 171 #define SI32_ECRC_A_CONTROL_ASEEDSEL_MSB_READ_VALUE 1 172 #define SI32_ECRC_A_CONTROL_ASEEDSEL_MSB_READ_U32 \ 173 (SI32_ECRC_A_CONTROL_ASEEDSEL_MSB_READ_VALUE << SI32_ECRC_A_CONTROL_ASEEDSEL_SHIFT) 174 175 176 177 struct SI32_ECRC_A_POLY_Struct 178 { 179 union 180 { 181 struct 182 { 183 // 16-bit Programmable Polynomial 184 volatile uint16_t POLY_BITS; 185 uint32_t reserved0: 16; 186 }; 187 volatile uint32_t U32; 188 }; 189 }; 190 191 #define SI32_ECRC_A_POLY_POLY_MASK 0x0000FFFF 192 #define SI32_ECRC_A_POLY_POLY_SHIFT 0 193 194 195 196 struct SI32_ECRC_A_DATA_Struct 197 { 198 union 199 { 200 struct 201 { 202 // Input/Result Data 203 volatile uint32_t DATA_BITS; 204 }; 205 volatile uint32_t U32; 206 }; 207 }; 208 209 #define SI32_ECRC_A_DATA_DATA_MASK 0xFFFFFFFF 210 #define SI32_ECRC_A_DATA_DATA_SHIFT 0 211 212 213 214 struct SI32_ECRC_A_RDATA_Struct 215 { 216 union 217 { 218 struct 219 { 220 // Bit-Reversed Output Data 221 volatile uint32_t RDATA_BITS; 222 }; 223 volatile uint32_t U32; 224 }; 225 }; 226 227 #define SI32_ECRC_A_RDATA_RDATA_MASK 0xFFFFFFFF 228 #define SI32_ECRC_A_RDATA_RDATA_SHIFT 0 229 230 231 232 struct SI32_ECRC_A_BRDATA_Struct 233 { 234 union 235 { 236 struct 237 { 238 // Byte-Reversed Output Data 239 volatile uint32_t BRDATA_BITS; 240 }; 241 volatile uint32_t U32; 242 }; 243 }; 244 245 #define SI32_ECRC_A_BRDATA_BRDATA_MASK 0xFFFFFFFF 246 #define SI32_ECRC_A_BRDATA_BRDATA_SHIFT 0 247 248 249 250 struct SI32_ECRC_A_SCONTROL_Struct 251 { 252 union 253 { 254 struct 255 { 256 // Snooping Enable 257 volatile uint32_t SEN: 1; 258 // Snooping Direction Select 259 volatile uint32_t SDIRSEL: 1; 260 uint32_t reserved0: 2; 261 // Snooping Peripheral Select 262 volatile uint32_t SPERISEL: 4; 263 uint32_t reserved1: 10; 264 // Snooping Address 265 volatile uint32_t SADDR: 10; 266 uint32_t reserved2: 4; 267 }; 268 volatile uint32_t U32; 269 }; 270 }; 271 272 #define SI32_ECRC_A_SCONTROL_SEN_MASK 0x00000001 273 #define SI32_ECRC_A_SCONTROL_SEN_SHIFT 0 274 // Disable automatic bus snooping. 275 #define SI32_ECRC_A_SCONTROL_SEN_DISABLED_VALUE 0 276 #define SI32_ECRC_A_SCONTROL_SEN_DISABLED_U32 \ 277 (SI32_ECRC_A_SCONTROL_SEN_DISABLED_VALUE << SI32_ECRC_A_SCONTROL_SEN_SHIFT) 278 // Enable automatic bus snooping. 279 #define SI32_ECRC_A_SCONTROL_SEN_ENABLED_VALUE 1 280 #define SI32_ECRC_A_SCONTROL_SEN_ENABLED_U32 \ 281 (SI32_ECRC_A_SCONTROL_SEN_ENABLED_VALUE << SI32_ECRC_A_SCONTROL_SEN_SHIFT) 282 283 #define SI32_ECRC_A_SCONTROL_SDIRSEL_MASK 0x00000002 284 #define SI32_ECRC_A_SCONTROL_SDIRSEL_SHIFT 1 285 // ECRC will snoop writes to the selected peripheral. 286 #define SI32_ECRC_A_SCONTROL_SDIRSEL_WRITES_VALUE 0 287 #define SI32_ECRC_A_SCONTROL_SDIRSEL_WRITES_U32 \ 288 (SI32_ECRC_A_SCONTROL_SDIRSEL_WRITES_VALUE << SI32_ECRC_A_SCONTROL_SDIRSEL_SHIFT) 289 // ECRC will snoop reads from the selected peripheral. 290 #define SI32_ECRC_A_SCONTROL_SDIRSEL_READS_VALUE 1 291 #define SI32_ECRC_A_SCONTROL_SDIRSEL_READS_U32 \ 292 (SI32_ECRC_A_SCONTROL_SDIRSEL_READS_VALUE << SI32_ECRC_A_SCONTROL_SDIRSEL_SHIFT) 293 294 #define SI32_ECRC_A_SCONTROL_SPERISEL_MASK 0x000000F0 295 #define SI32_ECRC_A_SCONTROL_SPERISEL_SHIFT 4 296 297 #define SI32_ECRC_A_SCONTROL_SADDR_MASK 0x0FFC0000 298 #define SI32_ECRC_A_SCONTROL_SADDR_SHIFT 18 299 300 301 302 typedef struct SI32_ECRC_A_Struct 303 { 304 struct SI32_ECRC_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 305 volatile uint32_t CONTROL_SET; 306 volatile uint32_t CONTROL_CLR; 307 uint32_t reserved0; 308 struct SI32_ECRC_A_POLY_Struct POLY ; // Base Address + 0x10 309 uint32_t reserved1; 310 uint32_t reserved2; 311 uint32_t reserved3; 312 struct SI32_ECRC_A_DATA_Struct DATA ; // Base Address + 0x20 313 uint32_t reserved4; 314 uint32_t reserved5; 315 uint32_t reserved6; 316 struct SI32_ECRC_A_RDATA_Struct RDATA ; // Base Address + 0x30 317 uint32_t reserved7; 318 uint32_t reserved8; 319 uint32_t reserved9; 320 struct SI32_ECRC_A_BRDATA_Struct BRDATA ; // Base Address + 0x40 321 uint32_t reserved10; 322 uint32_t reserved11; 323 uint32_t reserved12; 324 struct SI32_ECRC_A_SCONTROL_Struct SCONTROL ; // Base Address + 0x50 325 volatile uint32_t SCONTROL_SET; 326 volatile uint32_t SCONTROL_CLR; 327 uint32_t reserved13; 328 } SI32_ECRC_A_Type; 329 330 #ifdef __cplusplus 331 } 332 #endif 333 334 #endif // __SI32_ECRC_A_REGISTERS_H__ 335 336 //-eof-------------------------------------------------------------------------- 337 338
