1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_DTM_A_REGISTERS_H__ 27 #define __SI32_DTM_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_DTM_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Active State Counter 42 volatile uint8_t STCOUNT; 43 // Active State 44 volatile uint32_t ST: 4; 45 // Last State 46 volatile uint32_t LASTST: 4; 47 // Inhibit Signal Select 48 volatile uint32_t INHSSEL: 4; 49 uint32_t reserved0: 3; 50 // Debug Mode 51 volatile uint32_t DBGMD: 1; 52 // Inhibit Status Flag 53 volatile uint32_t INHF: 1; 54 // Destination Peripheral DMA Request Status Flag 55 volatile uint32_t DSTREQF: 1; 56 // Source Peripheral DMA Request Status Flag 57 volatile uint32_t SRCREQF: 1; 58 // DTM Module Inhibit 59 volatile uint32_t DTMINH: 1; 60 // Timeout Error Interrupt Flag 61 volatile uint32_t TOERRI: 1; 62 // DMA Error Interrupt Flag 63 volatile uint32_t DMAERRI: 1; 64 // Module Interrupt Flag 65 volatile uint32_t DTMI: 1; 66 // Module Enable 67 volatile uint32_t DTMEN: 1; 68 }; 69 volatile uint32_t U32; 70 }; 71 }; 72 73 #define SI32_DTM_A_CONTROL_STCOUNT_MASK 0x000000FF 74 #define SI32_DTM_A_CONTROL_STCOUNT_SHIFT 0 75 76 #define SI32_DTM_A_CONTROL_ST_MASK 0x00000F00 77 #define SI32_DTM_A_CONTROL_ST_SHIFT 8 78 79 #define SI32_DTM_A_CONTROL_LASTST_MASK 0x0000F000 80 #define SI32_DTM_A_CONTROL_LASTST_SHIFT 12 81 82 #define SI32_DTM_A_CONTROL_INHSSEL_MASK 0x000F0000 83 #define SI32_DTM_A_CONTROL_INHSSEL_SHIFT 16 84 // Select inhibit signal source DTMnINH.0. 85 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH0_VALUE 0 86 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH0_U32 \ 87 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH0_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 88 // Select inhibit signal source DTMnINH.1. 89 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH1_VALUE 1 90 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH1_U32 \ 91 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH1_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 92 // Select inhibit signal source DTMnINH.2. 93 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH2_VALUE 2 94 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH2_U32 \ 95 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH2_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 96 // Select inhibit signal source DTMnINH.3. 97 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH3_VALUE 3 98 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH3_U32 \ 99 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH3_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 100 // Select inhibit signal source DTMnINH.4. 101 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH4_VALUE 4 102 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH4_U32 \ 103 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH4_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 104 // Select inhibit signal source DTMnINH.5. 105 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH5_VALUE 5 106 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH5_U32 \ 107 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH5_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 108 // Select inhibit signal source DTMnINH.6. 109 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH6_VALUE 6 110 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH6_U32 \ 111 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH6_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 112 // Select inhibit signal source DTMnINH.7. 113 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH7_VALUE 7 114 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH7_U32 \ 115 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH7_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 116 // Select inhibit signal source DTMnINH.8. 117 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH8_VALUE 8 118 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH8_U32 \ 119 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH8_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 120 // Select inhibit signal source DTMnINH.9. 121 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH9_VALUE 9 122 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH9_U32 \ 123 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH9_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 124 // Select inhibit signal source DTMnINH.10. 125 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH10_VALUE 10 126 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH10_U32 \ 127 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH10_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 128 // Select inhibit signal source DTMnINH.11. 129 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH11_VALUE 11 130 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH11_U32 \ 131 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH11_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 132 // Select inhibit signal source DTMnINH.12. 133 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH12_VALUE 12 134 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH12_U32 \ 135 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH12_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 136 // Select inhibit signal source DTMnINH.13. 137 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH13_VALUE 13 138 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH13_U32 \ 139 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH13_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 140 // Select inhibit signal source DTMnINH.14. 141 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH14_VALUE 14 142 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH14_U32 \ 143 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH14_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 144 // Select inhibit signal source DTMnINH.15. 145 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH15_VALUE 15 146 #define SI32_DTM_A_CONTROL_INHSSEL_DTMNINH15_U32 \ 147 (SI32_DTM_A_CONTROL_INHSSEL_DTMNINH15_VALUE << SI32_DTM_A_CONTROL_INHSSEL_SHIFT) 148 149 #define SI32_DTM_A_CONTROL_DBGMD_MASK 0x00800000 150 #define SI32_DTM_A_CONTROL_DBGMD_SHIFT 23 151 // The DTM module will continue to operate while the core is halted in debug mode. 152 #define SI32_DTM_A_CONTROL_DBGMD_RUN_VALUE 0 153 #define SI32_DTM_A_CONTROL_DBGMD_RUN_U32 \ 154 (SI32_DTM_A_CONTROL_DBGMD_RUN_VALUE << SI32_DTM_A_CONTROL_DBGMD_SHIFT) 155 // A debug breakpoint will cause the DTM module to halt. 156 #define SI32_DTM_A_CONTROL_DBGMD_HALT_VALUE 1 157 #define SI32_DTM_A_CONTROL_DBGMD_HALT_U32 \ 158 (SI32_DTM_A_CONTROL_DBGMD_HALT_VALUE << SI32_DTM_A_CONTROL_DBGMD_SHIFT) 159 160 #define SI32_DTM_A_CONTROL_INHF_MASK 0x01000000 161 #define SI32_DTM_A_CONTROL_INHF_SHIFT 24 162 // The inhibit signal is inactive. 163 #define SI32_DTM_A_CONTROL_INHF_NOT_SET_VALUE 0 164 #define SI32_DTM_A_CONTROL_INHF_NOT_SET_U32 \ 165 (SI32_DTM_A_CONTROL_INHF_NOT_SET_VALUE << SI32_DTM_A_CONTROL_INHF_SHIFT) 166 // The inhibit signal is active. 167 #define SI32_DTM_A_CONTROL_INHF_SET_VALUE 1 168 #define SI32_DTM_A_CONTROL_INHF_SET_U32 \ 169 (SI32_DTM_A_CONTROL_INHF_SET_VALUE << SI32_DTM_A_CONTROL_INHF_SHIFT) 170 171 #define SI32_DTM_A_CONTROL_DSTREQF_MASK 0x02000000 172 #define SI32_DTM_A_CONTROL_DSTREQF_SHIFT 25 173 // The destination peripheral did not request a DMA transfer. 174 #define SI32_DTM_A_CONTROL_DSTREQF_NOT_SET_VALUE 0 175 #define SI32_DTM_A_CONTROL_DSTREQF_NOT_SET_U32 \ 176 (SI32_DTM_A_CONTROL_DSTREQF_NOT_SET_VALUE << SI32_DTM_A_CONTROL_DSTREQF_SHIFT) 177 // The destination peripheral requested a DMA transfer. 178 #define SI32_DTM_A_CONTROL_DSTREQF_SET_VALUE 1 179 #define SI32_DTM_A_CONTROL_DSTREQF_SET_U32 \ 180 (SI32_DTM_A_CONTROL_DSTREQF_SET_VALUE << SI32_DTM_A_CONTROL_DSTREQF_SHIFT) 181 182 #define SI32_DTM_A_CONTROL_SRCREQF_MASK 0x04000000 183 #define SI32_DTM_A_CONTROL_SRCREQF_SHIFT 26 184 // The source peripheral did not request a DMA transfer. 185 #define SI32_DTM_A_CONTROL_SRCREQF_NOT_SET_VALUE 0 186 #define SI32_DTM_A_CONTROL_SRCREQF_NOT_SET_U32 \ 187 (SI32_DTM_A_CONTROL_SRCREQF_NOT_SET_VALUE << SI32_DTM_A_CONTROL_SRCREQF_SHIFT) 188 // The source peripheral requested a DMA transfer. 189 #define SI32_DTM_A_CONTROL_SRCREQF_SET_VALUE 1 190 #define SI32_DTM_A_CONTROL_SRCREQF_SET_U32 \ 191 (SI32_DTM_A_CONTROL_SRCREQF_SET_VALUE << SI32_DTM_A_CONTROL_SRCREQF_SHIFT) 192 193 #define SI32_DTM_A_CONTROL_DTMINH_MASK 0x08000000 194 #define SI32_DTM_A_CONTROL_DTMINH_SHIFT 27 195 // The DTM module does not ignore DMA requests. 196 #define SI32_DTM_A_CONTROL_DTMINH_INACTIVE_VALUE 0 197 #define SI32_DTM_A_CONTROL_DTMINH_INACTIVE_U32 \ 198 (SI32_DTM_A_CONTROL_DTMINH_INACTIVE_VALUE << SI32_DTM_A_CONTROL_DTMINH_SHIFT) 199 // The DTM module ignores DMA requests until this bit is cleared. 200 #define SI32_DTM_A_CONTROL_DTMINH_ACTIVE_VALUE 1 201 #define SI32_DTM_A_CONTROL_DTMINH_ACTIVE_U32 \ 202 (SI32_DTM_A_CONTROL_DTMINH_ACTIVE_VALUE << SI32_DTM_A_CONTROL_DTMINH_SHIFT) 203 204 #define SI32_DTM_A_CONTROL_TOERRI_MASK 0x10000000 205 #define SI32_DTM_A_CONTROL_TOERRI_SHIFT 28 206 // A timeout error has not occurred. 207 #define SI32_DTM_A_CONTROL_TOERRI_NOT_SET_VALUE 0 208 #define SI32_DTM_A_CONTROL_TOERRI_NOT_SET_U32 \ 209 (SI32_DTM_A_CONTROL_TOERRI_NOT_SET_VALUE << SI32_DTM_A_CONTROL_TOERRI_SHIFT) 210 // A timeout error occurred. 211 #define SI32_DTM_A_CONTROL_TOERRI_SET_VALUE 1 212 #define SI32_DTM_A_CONTROL_TOERRI_SET_U32 \ 213 (SI32_DTM_A_CONTROL_TOERRI_SET_VALUE << SI32_DTM_A_CONTROL_TOERRI_SHIFT) 214 215 #define SI32_DTM_A_CONTROL_DMAERRI_MASK 0x20000000 216 #define SI32_DTM_A_CONTROL_DMAERRI_SHIFT 29 217 // A DMA error has not occurred. 218 #define SI32_DTM_A_CONTROL_DMAERRI_NOT_SET_VALUE 0 219 #define SI32_DTM_A_CONTROL_DMAERRI_NOT_SET_U32 \ 220 (SI32_DTM_A_CONTROL_DMAERRI_NOT_SET_VALUE << SI32_DTM_A_CONTROL_DMAERRI_SHIFT) 221 // A DMA error occurred. 222 #define SI32_DTM_A_CONTROL_DMAERRI_SET_VALUE 1 223 #define SI32_DTM_A_CONTROL_DMAERRI_SET_U32 \ 224 (SI32_DTM_A_CONTROL_DMAERRI_SET_VALUE << SI32_DTM_A_CONTROL_DMAERRI_SHIFT) 225 226 #define SI32_DTM_A_CONTROL_DTMI_MASK 0x40000000 227 #define SI32_DTM_A_CONTROL_DTMI_SHIFT 30 228 // A state transition or timeout has not occurred. 229 #define SI32_DTM_A_CONTROL_DTMI_NOT_SET_VALUE 0 230 #define SI32_DTM_A_CONTROL_DTMI_NOT_SET_U32 \ 231 (SI32_DTM_A_CONTROL_DTMI_NOT_SET_VALUE << SI32_DTM_A_CONTROL_DTMI_SHIFT) 232 // A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) 233 // occurred. 234 #define SI32_DTM_A_CONTROL_DTMI_SET_VALUE 1 235 #define SI32_DTM_A_CONTROL_DTMI_SET_U32 \ 236 (SI32_DTM_A_CONTROL_DTMI_SET_VALUE << SI32_DTM_A_CONTROL_DTMI_SHIFT) 237 238 #define SI32_DTM_A_CONTROL_DTMEN_MASK 0x80000000 239 #define SI32_DTM_A_CONTROL_DTMEN_SHIFT 31 240 // Disable the DTM module. 241 #define SI32_DTM_A_CONTROL_DTMEN_DISABLED_VALUE 0U 242 #define SI32_DTM_A_CONTROL_DTMEN_DISABLED_U32 \ 243 (SI32_DTM_A_CONTROL_DTMEN_DISABLED_VALUE << SI32_DTM_A_CONTROL_DTMEN_SHIFT) 244 // Enable the DTM module. 245 #define SI32_DTM_A_CONTROL_DTMEN_ENABLED_VALUE 1U 246 #define SI32_DTM_A_CONTROL_DTMEN_ENABLED_U32 \ 247 (SI32_DTM_A_CONTROL_DTMEN_ENABLED_VALUE << SI32_DTM_A_CONTROL_DTMEN_SHIFT) 248 249 250 251 struct SI32_DTM_A_TIMEOUT_Struct 252 { 253 union 254 { 255 struct 256 { 257 // Timeout Counter Reload 258 volatile uint16_t TORELOAD; 259 // Timeout Counter 260 volatile uint16_t TOCOUNT; 261 }; 262 volatile uint32_t U32; 263 }; 264 }; 265 266 #define SI32_DTM_A_TIMEOUT_TORELOAD_MASK 0x0000FFFF 267 #define SI32_DTM_A_TIMEOUT_TORELOAD_SHIFT 0 268 269 #define SI32_DTM_A_TIMEOUT_TOCOUNT_MASK 0xFFFF0000 270 #define SI32_DTM_A_TIMEOUT_TOCOUNT_SHIFT 16 271 272 273 274 struct SI32_DTM_A_MSTCOUNT_Struct 275 { 276 union 277 { 278 struct 279 { 280 // Master Counter 281 volatile uint16_t MSTCOUNT_BITS; 282 uint32_t reserved0: 16; 283 }; 284 volatile uint32_t U32; 285 }; 286 }; 287 288 #define SI32_DTM_A_MSTCOUNT_MSTCOUNT_MASK 0x0000FFFF 289 #define SI32_DTM_A_MSTCOUNT_MSTCOUNT_SHIFT 0 290 291 292 293 struct SI32_DTM_A_STATEADDR_Struct 294 { 295 union 296 { 297 struct 298 { 299 uint32_t reserved0: 2; 300 // State Address 301 volatile uint32_t STATEADDR_BITS: 30; 302 }; 303 volatile uint32_t U32; 304 }; 305 }; 306 307 #define SI32_DTM_A_STATEADDR_STATEADDR_MASK 0xFFFFFFFC 308 #define SI32_DTM_A_STATEADDR_STATEADDR_SHIFT 2 309 310 311 312 struct SI32_DTM_A_STATE_Struct 313 { 314 union 315 { 316 struct 317 { 318 // Active State Counter Reload 319 volatile uint8_t STRELOAD; 320 // Secondary State 321 volatile uint32_t SECST: 4; 322 // Primary State 323 volatile uint32_t PRIST: 4; 324 // Destination Module 325 volatile uint32_t DSTMOD: 4; 326 // Source Module 327 volatile uint32_t SRCMOD: 4; 328 // DTM Channel Select 329 volatile uint32_t DTMCHSEL: 2; 330 // Inhibit Signal Polarity 331 volatile uint32_t INHSPOL: 1; 332 // Module Inhibit Enable 333 volatile uint32_t DTMINH: 1; 334 // Master Decrement Enable 335 volatile uint32_t MSTDECEN: 1; 336 // Timeout Enable 337 volatile uint32_t TOERRIEN: 1; 338 // Secondary State Transition Interrupt Enable 339 volatile uint32_t SECSTIEN: 1; 340 // Primary State Transition Interrupt Enable 341 volatile uint32_t PRISTIEN: 1; 342 }; 343 volatile uint32_t U32; 344 }; 345 }; 346 347 #define SI32_DTM_A_STATE_STRELOAD_MASK 0x000000FF 348 #define SI32_DTM_A_STATE_STRELOAD_SHIFT 0 349 350 #define SI32_DTM_A_STATE_SECST_MASK 0x00000F00 351 #define SI32_DTM_A_STATE_SECST_SHIFT 8 352 353 #define SI32_DTM_A_STATE_PRIST_MASK 0x0000F000 354 #define SI32_DTM_A_STATE_PRIST_SHIFT 12 355 356 #define SI32_DTM_A_STATE_DSTMOD_MASK 0x000F0000 357 #define SI32_DTM_A_STATE_DSTMOD_SHIFT 16 358 // Select destination module DTMnDST.0. 359 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST0_VALUE 0 360 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST0_U32 \ 361 (SI32_DTM_A_STATE_DSTMOD_DTMNDST0_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 362 // Select destination module DTMnDST.1. 363 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST1_VALUE 1 364 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST1_U32 \ 365 (SI32_DTM_A_STATE_DSTMOD_DTMNDST1_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 366 // Select destination module DTMnDST.2. 367 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST2_VALUE 2 368 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST2_U32 \ 369 (SI32_DTM_A_STATE_DSTMOD_DTMNDST2_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 370 // Select destination module DTMnDST.3. 371 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST3_VALUE 3 372 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST3_U32 \ 373 (SI32_DTM_A_STATE_DSTMOD_DTMNDST3_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 374 // Select destination module DTMnDST.4. 375 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST4_VALUE 4 376 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST4_U32 \ 377 (SI32_DTM_A_STATE_DSTMOD_DTMNDST4_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 378 // Select destination module DTMnDST.5. 379 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST5_VALUE 5 380 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST5_U32 \ 381 (SI32_DTM_A_STATE_DSTMOD_DTMNDST5_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 382 // Select destination module DTMnDST.6. 383 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST6_VALUE 6 384 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST6_U32 \ 385 (SI32_DTM_A_STATE_DSTMOD_DTMNDST6_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 386 // Select destination module DTMnDST.7. 387 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST7_VALUE 7 388 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST7_U32 \ 389 (SI32_DTM_A_STATE_DSTMOD_DTMNDST7_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 390 // Select destination module DTMnDST.8. 391 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST8_VALUE 8 392 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST8_U32 \ 393 (SI32_DTM_A_STATE_DSTMOD_DTMNDST8_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 394 // Select destination module DTMnDST.9. 395 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST9_VALUE 9 396 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST9_U32 \ 397 (SI32_DTM_A_STATE_DSTMOD_DTMNDST9_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 398 // Select destination module DTMnDST.10. 399 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST10_VALUE 10 400 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST10_U32 \ 401 (SI32_DTM_A_STATE_DSTMOD_DTMNDST10_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 402 // Select destination module DTMnDST.11. 403 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST11_VALUE 11 404 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST11_U32 \ 405 (SI32_DTM_A_STATE_DSTMOD_DTMNDST11_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 406 // Select destination module DTMnDST.12. 407 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST12_VALUE 12 408 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST12_U32 \ 409 (SI32_DTM_A_STATE_DSTMOD_DTMNDST12_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 410 // Select destination module DTMnDST.13. 411 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST13_VALUE 13 412 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST13_U32 \ 413 (SI32_DTM_A_STATE_DSTMOD_DTMNDST13_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 414 // Select destination module DTMnDST.14. 415 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST14_VALUE 14 416 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST14_U32 \ 417 (SI32_DTM_A_STATE_DSTMOD_DTMNDST14_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 418 // Select no destination module (DTMnDST.15). 419 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST15_VALUE 15 420 #define SI32_DTM_A_STATE_DSTMOD_DTMNDST15_U32 \ 421 (SI32_DTM_A_STATE_DSTMOD_DTMNDST15_VALUE << SI32_DTM_A_STATE_DSTMOD_SHIFT) 422 423 #define SI32_DTM_A_STATE_SRCMOD_MASK 0x00F00000 424 #define SI32_DTM_A_STATE_SRCMOD_SHIFT 20 425 // Select source module DTMnSRC.0. 426 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC0_VALUE 0 427 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC0_U32 \ 428 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC0_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 429 // Select source module DTMnSRC.1. 430 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC1_VALUE 1 431 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC1_U32 \ 432 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC1_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 433 // Select source module DTMnSRC.2. 434 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC2_VALUE 2 435 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC2_U32 \ 436 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC2_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 437 // Select source module DTMnSRC.3. 438 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC3_VALUE 3 439 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC3_U32 \ 440 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC3_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 441 // Select source module DTMnSRC.4. 442 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC4_VALUE 4 443 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC4_U32 \ 444 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC4_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 445 // Select source module DTMnSRC.5. 446 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC5_VALUE 5 447 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC5_U32 \ 448 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC5_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 449 // Select source module DTMnSRC.6. 450 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC6_VALUE 6 451 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC6_U32 \ 452 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC6_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 453 // Select source module DTMnSRC.7. 454 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC7_VALUE 7 455 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC7_U32 \ 456 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC7_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 457 // Select source module DTMnSRC.8. 458 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC8_VALUE 8 459 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC8_U32 \ 460 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC8_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 461 // Select source module DTMnSRC.9. 462 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC9_VALUE 9 463 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC9_U32 \ 464 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC9_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 465 // Select source module DTMnSRC.10. 466 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC10_VALUE 10 467 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC10_U32 \ 468 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC10_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 469 // Select source module DTMnSRC.11. 470 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC11_VALUE 11 471 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC11_U32 \ 472 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC11_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 473 // Select source module DTMnSRC.12. 474 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC12_VALUE 12 475 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC12_U32 \ 476 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC12_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 477 // Select source module DTMnSRC.13. 478 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC13_VALUE 13 479 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC13_U32 \ 480 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC13_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 481 // Select source module DTMnSRC.14. 482 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC14_VALUE 14 483 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC14_U32 \ 484 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC14_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 485 // Select no source module (DTMnSRC.15). 486 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC15_VALUE 15 487 #define SI32_DTM_A_STATE_SRCMOD_DTMNSRC15_U32 \ 488 (SI32_DTM_A_STATE_SRCMOD_DTMNSRC15_VALUE << SI32_DTM_A_STATE_SRCMOD_SHIFT) 489 490 #define SI32_DTM_A_STATE_DTMCHSEL_MASK 0x03000000 491 #define SI32_DTM_A_STATE_DTMCHSEL_SHIFT 24 492 // Select DTMn channel A for this state. 493 #define SI32_DTM_A_STATE_DTMCHSEL_CH_A_VALUE 0 494 #define SI32_DTM_A_STATE_DTMCHSEL_CH_A_U32 \ 495 (SI32_DTM_A_STATE_DTMCHSEL_CH_A_VALUE << SI32_DTM_A_STATE_DTMCHSEL_SHIFT) 496 // Select DTMn channel B for this state. 497 #define SI32_DTM_A_STATE_DTMCHSEL_CH_B_VALUE 1 498 #define SI32_DTM_A_STATE_DTMCHSEL_CH_B_U32 \ 499 (SI32_DTM_A_STATE_DTMCHSEL_CH_B_VALUE << SI32_DTM_A_STATE_DTMCHSEL_SHIFT) 500 // Select DTMn channel C for this state. 501 #define SI32_DTM_A_STATE_DTMCHSEL_CH_C_VALUE 2 502 #define SI32_DTM_A_STATE_DTMCHSEL_CH_C_U32 \ 503 (SI32_DTM_A_STATE_DTMCHSEL_CH_C_VALUE << SI32_DTM_A_STATE_DTMCHSEL_SHIFT) 504 // Select DTMn channel D for this state. 505 #define SI32_DTM_A_STATE_DTMCHSEL_CH_D_VALUE 3 506 #define SI32_DTM_A_STATE_DTMCHSEL_CH_D_U32 \ 507 (SI32_DTM_A_STATE_DTMCHSEL_CH_D_VALUE << SI32_DTM_A_STATE_DTMCHSEL_SHIFT) 508 509 #define SI32_DTM_A_STATE_INHSPOL_MASK 0x04000000 510 #define SI32_DTM_A_STATE_INHSPOL_SHIFT 26 511 // A logic low on the pin selected by INHSEL will allow the DTM to proceed. 512 #define SI32_DTM_A_STATE_INHSPOL_ACTIVE_LOW_VALUE 0 513 #define SI32_DTM_A_STATE_INHSPOL_ACTIVE_LOW_U32 \ 514 (SI32_DTM_A_STATE_INHSPOL_ACTIVE_LOW_VALUE << SI32_DTM_A_STATE_INHSPOL_SHIFT) 515 // A logic high on the pin selected by INHSEL will allow the DTM to proceed. 516 #define SI32_DTM_A_STATE_INHSPOL_ACTIVE_HIGH_VALUE 1 517 #define SI32_DTM_A_STATE_INHSPOL_ACTIVE_HIGH_U32 \ 518 (SI32_DTM_A_STATE_INHSPOL_ACTIVE_HIGH_VALUE << SI32_DTM_A_STATE_INHSPOL_SHIFT) 519 520 #define SI32_DTM_A_STATE_DTMINH_MASK 0x08000000 521 #define SI32_DTM_A_STATE_DTMINH_SHIFT 27 522 // The DTM module does not ignore any DMA requests. 523 #define SI32_DTM_A_STATE_DTMINH_INACTIVE_VALUE 0 524 #define SI32_DTM_A_STATE_DTMINH_INACTIVE_U32 \ 525 (SI32_DTM_A_STATE_DTMINH_INACTIVE_VALUE << SI32_DTM_A_STATE_DTMINH_SHIFT) 526 // The DTM module ignores all DMA requests until the inhibit signal selected by 527 // INHSSEL matches the polarity polarity set by INHSPOL. 528 #define SI32_DTM_A_STATE_DTMINH_ACTIVE_VALUE 1 529 #define SI32_DTM_A_STATE_DTMINH_ACTIVE_U32 \ 530 (SI32_DTM_A_STATE_DTMINH_ACTIVE_VALUE << SI32_DTM_A_STATE_DTMINH_SHIFT) 531 532 #define SI32_DTM_A_STATE_MSTDECEN_MASK 0x10000000 533 #define SI32_DTM_A_STATE_MSTDECEN_SHIFT 28 534 // Disable master counter decrements. 535 #define SI32_DTM_A_STATE_MSTDECEN_DISABLED_VALUE 0 536 #define SI32_DTM_A_STATE_MSTDECEN_DISABLED_U32 \ 537 (SI32_DTM_A_STATE_MSTDECEN_DISABLED_VALUE << SI32_DTM_A_STATE_MSTDECEN_SHIFT) 538 // Enable master counter decrements. 539 #define SI32_DTM_A_STATE_MSTDECEN_ENABLED_VALUE 1 540 #define SI32_DTM_A_STATE_MSTDECEN_ENABLED_U32 \ 541 (SI32_DTM_A_STATE_MSTDECEN_ENABLED_VALUE << SI32_DTM_A_STATE_MSTDECEN_SHIFT) 542 543 #define SI32_DTM_A_STATE_TOERRIEN_MASK 0x20000000 544 #define SI32_DTM_A_STATE_TOERRIEN_SHIFT 29 545 // Disable timeouts and timeout interrupts. 546 #define SI32_DTM_A_STATE_TOERRIEN_DISABLED_VALUE 0 547 #define SI32_DTM_A_STATE_TOERRIEN_DISABLED_U32 \ 548 (SI32_DTM_A_STATE_TOERRIEN_DISABLED_VALUE << SI32_DTM_A_STATE_TOERRIEN_SHIFT) 549 // Enable timeouts and timeout interrupts. 550 #define SI32_DTM_A_STATE_TOERRIEN_ENABLED_VALUE 1 551 #define SI32_DTM_A_STATE_TOERRIEN_ENABLED_U32 \ 552 (SI32_DTM_A_STATE_TOERRIEN_ENABLED_VALUE << SI32_DTM_A_STATE_TOERRIEN_SHIFT) 553 554 #define SI32_DTM_A_STATE_SECSTIEN_MASK 0x40000000 555 #define SI32_DTM_A_STATE_SECSTIEN_SHIFT 30 556 // Disable secondary state transition interrupts. 557 #define SI32_DTM_A_STATE_SECSTIEN_DISABLED_VALUE 0 558 #define SI32_DTM_A_STATE_SECSTIEN_DISABLED_U32 \ 559 (SI32_DTM_A_STATE_SECSTIEN_DISABLED_VALUE << SI32_DTM_A_STATE_SECSTIEN_SHIFT) 560 // Enable secondary state transition interrupts. 561 #define SI32_DTM_A_STATE_SECSTIEN_ENABLED_VALUE 1 562 #define SI32_DTM_A_STATE_SECSTIEN_ENABLED_U32 \ 563 (SI32_DTM_A_STATE_SECSTIEN_ENABLED_VALUE << SI32_DTM_A_STATE_SECSTIEN_SHIFT) 564 565 #define SI32_DTM_A_STATE_PRISTIEN_MASK 0x80000000 566 #define SI32_DTM_A_STATE_PRISTIEN_SHIFT 31 567 // Disable primary state transition interrupts. 568 #define SI32_DTM_A_STATE_PRISTIEN_DISABLED_VALUE 0U 569 #define SI32_DTM_A_STATE_PRISTIEN_DISABLED_U32 \ 570 (SI32_DTM_A_STATE_PRISTIEN_DISABLED_VALUE << SI32_DTM_A_STATE_PRISTIEN_SHIFT) 571 // Enable primary state transition interrupts. 572 #define SI32_DTM_A_STATE_PRISTIEN_ENABLED_VALUE 1U 573 #define SI32_DTM_A_STATE_PRISTIEN_ENABLED_U32 \ 574 (SI32_DTM_A_STATE_PRISTIEN_ENABLED_VALUE << SI32_DTM_A_STATE_PRISTIEN_SHIFT) 575 576 577 578 typedef struct SI32_DTM_A_Struct 579 { 580 struct SI32_DTM_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 581 volatile uint32_t CONTROL_SET; 582 volatile uint32_t CONTROL_CLR; 583 uint32_t reserved0; 584 struct SI32_DTM_A_TIMEOUT_Struct TIMEOUT ; // Base Address + 0x10 585 uint32_t reserved1; 586 uint32_t reserved2; 587 uint32_t reserved3; 588 struct SI32_DTM_A_MSTCOUNT_Struct MSTCOUNT ; // Base Address + 0x20 589 uint32_t reserved4; 590 uint32_t reserved5; 591 uint32_t reserved6; 592 struct SI32_DTM_A_STATEADDR_Struct STATEADDR ; // Base Address + 0x30 593 uint32_t reserved7; 594 uint32_t reserved8; 595 uint32_t reserved9; 596 struct SI32_DTM_A_STATE_Struct STATE ; // Base Address + 0x40 597 uint32_t reserved10; 598 uint32_t reserved11; 599 uint32_t reserved12; 600 } SI32_DTM_A_Type; 601 602 #ifdef __cplusplus 603 } 604 #endif 605 606 #endif // __SI32_DTM_A_REGISTERS_H__ 607 608 //-eof-------------------------------------------------------------------------- 609 610
