1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_CRC_A_REGISTERS_H__ 27 #define __SI32_CRC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_CRC_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Seed Initialization Enable 42 volatile uint32_t SINITEN: 1; 43 // Seed Setting 44 volatile uint32_t SEED: 1; 45 // CRC Enable 46 volatile uint32_t CRCEN: 1; 47 uint32_t reserved0: 1; 48 // Polynomial Selection 49 volatile uint32_t POLYSEL: 2; 50 uint32_t reserved1: 2; 51 // Byte Mode Enable 52 volatile uint32_t BMDEN: 1; 53 // Byte-Level Bit Reversal Enable 54 volatile uint32_t BBREN: 1; 55 // Input Processing Order 56 volatile uint32_t ORDER: 2; 57 uint32_t reserved2: 20; 58 }; 59 volatile uint32_t U32; 60 }; 61 }; 62 63 #define SI32_CRC_A_CONTROL_SINITEN_MASK 0x00000001 64 #define SI32_CRC_A_CONTROL_SINITEN_SHIFT 0 65 // Do not initialize the CRC module to the value set by the SEED bit. 66 #define SI32_CRC_A_CONTROL_SINITEN_DISABLED_VALUE 0 67 #define SI32_CRC_A_CONTROL_SINITEN_DISABLED_U32 \ 68 (SI32_CRC_A_CONTROL_SINITEN_DISABLED_VALUE << SI32_CRC_A_CONTROL_SINITEN_SHIFT) 69 // Initialize the CRC module to the value set by the SEED bit. 70 #define SI32_CRC_A_CONTROL_SINITEN_ENABLED_VALUE 1 71 #define SI32_CRC_A_CONTROL_SINITEN_ENABLED_U32 \ 72 (SI32_CRC_A_CONTROL_SINITEN_ENABLED_VALUE << SI32_CRC_A_CONTROL_SINITEN_SHIFT) 73 74 #define SI32_CRC_A_CONTROL_SEED_MASK 0x00000002 75 #define SI32_CRC_A_CONTROL_SEED_SHIFT 1 76 // CRC seed value is all 0's (0x00000000) 77 #define SI32_CRC_A_CONTROL_SEED_ALL_ZEROES_VALUE 0 78 #define SI32_CRC_A_CONTROL_SEED_ALL_ZEROES_U32 \ 79 (SI32_CRC_A_CONTROL_SEED_ALL_ZEROES_VALUE << SI32_CRC_A_CONTROL_SEED_SHIFT) 80 // CRC seed value is all 1's (0xFFFFFFFF). 81 #define SI32_CRC_A_CONTROL_SEED_ALL_ONES_VALUE 1 82 #define SI32_CRC_A_CONTROL_SEED_ALL_ONES_U32 \ 83 (SI32_CRC_A_CONTROL_SEED_ALL_ONES_VALUE << SI32_CRC_A_CONTROL_SEED_SHIFT) 84 85 #define SI32_CRC_A_CONTROL_CRCEN_MASK 0x00000004 86 #define SI32_CRC_A_CONTROL_CRCEN_SHIFT 2 87 // Disable CRC operations. 88 #define SI32_CRC_A_CONTROL_CRCEN_DISABLED_VALUE 0 89 #define SI32_CRC_A_CONTROL_CRCEN_DISABLED_U32 \ 90 (SI32_CRC_A_CONTROL_CRCEN_DISABLED_VALUE << SI32_CRC_A_CONTROL_CRCEN_SHIFT) 91 // Enable CRC operations. 92 #define SI32_CRC_A_CONTROL_CRCEN_ENABLED_VALUE 1 93 #define SI32_CRC_A_CONTROL_CRCEN_ENABLED_U32 \ 94 (SI32_CRC_A_CONTROL_CRCEN_ENABLED_VALUE << SI32_CRC_A_CONTROL_CRCEN_SHIFT) 95 96 #define SI32_CRC_A_CONTROL_POLYSEL_MASK 0x00000030 97 #define SI32_CRC_A_CONTROL_POLYSEL_SHIFT 4 98 // Select 32-bit polynomial: 0x04C11DB7. 99 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_32_04C11DB7_VALUE 0 100 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_32_04C11DB7_U32 \ 101 (SI32_CRC_A_CONTROL_POLYSEL_CRC_32_04C11DB7_VALUE << SI32_CRC_A_CONTROL_POLYSEL_SHIFT) 102 // Select 16-bit polynomial: 0x1021. 103 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_16_1021_VALUE 1 104 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_16_1021_U32 \ 105 (SI32_CRC_A_CONTROL_POLYSEL_CRC_16_1021_VALUE << SI32_CRC_A_CONTROL_POLYSEL_SHIFT) 106 // Select 16-bit polynomial: 0x3D65. 107 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_16_3D65_VALUE 2 108 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_16_3D65_U32 \ 109 (SI32_CRC_A_CONTROL_POLYSEL_CRC_16_3D65_VALUE << SI32_CRC_A_CONTROL_POLYSEL_SHIFT) 110 // Select 16-bit polynomial: 0x8005. 111 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_16_8005_VALUE 3 112 #define SI32_CRC_A_CONTROL_POLYSEL_CRC_16_8005_U32 \ 113 (SI32_CRC_A_CONTROL_POLYSEL_CRC_16_8005_VALUE << SI32_CRC_A_CONTROL_POLYSEL_SHIFT) 114 115 #define SI32_CRC_A_CONTROL_BMDEN_MASK 0x00000100 116 #define SI32_CRC_A_CONTROL_BMDEN_SHIFT 8 117 // Disable byte mode (word/byte width is determined automatically by the hardware). 118 #define SI32_CRC_A_CONTROL_BMDEN_DISABLED_VALUE 0 119 #define SI32_CRC_A_CONTROL_BMDEN_DISABLED_U32 \ 120 (SI32_CRC_A_CONTROL_BMDEN_DISABLED_VALUE << SI32_CRC_A_CONTROL_BMDEN_SHIFT) 121 // Enable byte mode (all writes are considered as bytes). 122 #define SI32_CRC_A_CONTROL_BMDEN_ENABLED_VALUE 1 123 #define SI32_CRC_A_CONTROL_BMDEN_ENABLED_U32 \ 124 (SI32_CRC_A_CONTROL_BMDEN_ENABLED_VALUE << SI32_CRC_A_CONTROL_BMDEN_SHIFT) 125 126 #define SI32_CRC_A_CONTROL_BBREN_MASK 0x00000200 127 #define SI32_CRC_A_CONTROL_BBREN_SHIFT 9 128 // No byte-level bit reversal (input is same order as written). 129 #define SI32_CRC_A_CONTROL_BBREN_DISABLED_VALUE 0 130 #define SI32_CRC_A_CONTROL_BBREN_DISABLED_U32 \ 131 (SI32_CRC_A_CONTROL_BBREN_DISABLED_VALUE << SI32_CRC_A_CONTROL_BBREN_SHIFT) 132 // Byte-level bit reversal enabled (the bits in each byte are reversed). 133 #define SI32_CRC_A_CONTROL_BBREN_ENABLED_VALUE 1 134 #define SI32_CRC_A_CONTROL_BBREN_ENABLED_U32 \ 135 (SI32_CRC_A_CONTROL_BBREN_ENABLED_VALUE << SI32_CRC_A_CONTROL_BBREN_SHIFT) 136 137 #define SI32_CRC_A_CONTROL_ORDER_MASK 0x00000C00 138 #define SI32_CRC_A_CONTROL_ORDER_SHIFT 10 139 // No byte reorientation (output is same order as input). 140 #define SI32_CRC_A_CONTROL_ORDER_NO_REORDER_VALUE 0 141 #define SI32_CRC_A_CONTROL_ORDER_NO_REORDER_U32 \ 142 (SI32_CRC_A_CONTROL_ORDER_NO_REORDER_VALUE << SI32_CRC_A_CONTROL_ORDER_SHIFT) 143 // Swap for 16-bit big endian order (input: B3 B2 B1 B0, output: B2 B3 B0 B1). 144 #define SI32_CRC_A_CONTROL_ORDER_BIG_ENDIAN_16_VALUE 1 145 #define SI32_CRC_A_CONTROL_ORDER_BIG_ENDIAN_16_U32 \ 146 (SI32_CRC_A_CONTROL_ORDER_BIG_ENDIAN_16_VALUE << SI32_CRC_A_CONTROL_ORDER_SHIFT) 147 // Swap for 32-bit big endian order (input: B3 B2 B1 B0, output: B0 B1 B2 B3). 148 #define SI32_CRC_A_CONTROL_ORDER_BIG_ENDIAN_32_VALUE 2 149 #define SI32_CRC_A_CONTROL_ORDER_BIG_ENDIAN_32_U32 \ 150 (SI32_CRC_A_CONTROL_ORDER_BIG_ENDIAN_32_VALUE << SI32_CRC_A_CONTROL_ORDER_SHIFT) 151 152 153 154 struct SI32_CRC_A_DATA_Struct 155 { 156 union 157 { 158 struct 159 { 160 // Input/Result Data 161 volatile uint32_t DATA_BITS; 162 }; 163 volatile uint32_t U32; 164 }; 165 }; 166 167 #define SI32_CRC_A_DATA_DATA_MASK 0xFFFFFFFF 168 #define SI32_CRC_A_DATA_DATA_SHIFT 0 169 170 171 172 struct SI32_CRC_A_RDATA_Struct 173 { 174 union 175 { 176 struct 177 { 178 // Bit-Reversed Output Data 179 volatile uint32_t RDATA_BITS; 180 }; 181 volatile uint32_t U32; 182 }; 183 }; 184 185 #define SI32_CRC_A_RDATA_RDATA_MASK 0xFFFFFFFF 186 #define SI32_CRC_A_RDATA_RDATA_SHIFT 0 187 188 189 190 typedef struct SI32_CRC_A_Struct 191 { 192 struct SI32_CRC_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 193 volatile uint32_t CONTROL_SET; 194 volatile uint32_t CONTROL_CLR; 195 uint32_t reserved0; 196 struct SI32_CRC_A_DATA_Struct DATA ; // Base Address + 0x10 197 uint32_t reserved1; 198 uint32_t reserved2; 199 uint32_t reserved3; 200 struct SI32_CRC_A_RDATA_Struct RDATA ; // Base Address + 0x20 201 uint32_t reserved4; 202 uint32_t reserved5; 203 uint32_t reserved6; 204 } SI32_CRC_A_Type; 205 206 #ifdef __cplusplus 207 } 208 #endif 209 210 #endif // __SI32_CRC_A_REGISTERS_H__ 211 212 //-eof-------------------------------------------------------------------------- 213 214
