1 /******************************************************************************
2 * @file rsi_rom_clks.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 //Includes
31
32 /**
33 * @defgroup RSI_SPECIFIC_DRIVERS SoC Device-Specific Drivers
34 * @ingroup SOC
35 * @section Description
36 * RSI specific drivers are unique to a specific device. RSI specific drivers may use an IP driver as it's base driver or a custom implementation if that
37 * peripheral or IP on the chip is unique (ie, clocking)
38 */
39
40 /**
41 * \ingroup RSI_SPECIFIC_DRIVERS
42 */
43
44 /**
45 * \defgroup RSI_CHIP_CLOCK_DRIVERS
46 * @{
47 *
48 */
49
50 /**
51 * \defgroup RSI_M4SS_CLOCK_DRIVERS M4SS CLOCK
52 * @{
53 *
54 */
55
56 #ifndef __RSI_ROM_CLK_H_
57 #define __RSI_ROM_CLK_H_
58
59 #include "rsi_ccp_user_config.h"
60 #include "rsi_packing.h"
61 #if defined(A11_ROM)
62 #include "rsi_rom_table_si91x.h"
63 #else
64 #include "rsi_rom_table_RS1xxxx.h"
65 #endif
66
67 #if SL_WIFI_COMPONENT_INCLUDED
68 #include "sl_rsi_utility.h"
69 #include "rsi_m4.h"
70 #endif
71
72 #ifdef __cplusplus
73 extern "C" {
74 #endif
75
76 /**
77 * @fn STATIC INLINE boolean_t RSI_CLK_CheckPllLock(PLL_TYPE_T pllType)
78 * @brief This API is used to check the lock status of pll
79 * @param[in] pllType : To select the soc_pll, intf_pll and i2s_pll. See # PLL_TYPE_T for more info
80 * \n structure member is below.
81 * - SOC_PLL : soc_pll clk
82 * - INTF_PLL : intf_pll clk
83 * - I2S_PLL : i2s_pll clk
84 * @return return 1 then for lock status high(enable) and return 0 then for lock status low(disable)
85 *
86 */
RSI_CLK_CheckPllLock(PLL_TYPE_T pllType)87 STATIC INLINE boolean_t RSI_CLK_CheckPllLock(PLL_TYPE_T pllType)
88 {
89 #if defined(CLOCK_ROMDRIVER_PRESENT)
90 return ROMAPI_M4SS_CLK_API->clk_check_pll_lock(pllType);
91 #else
92 return clk_check_pll_lock(pllType);
93 #endif
94 }
95
96 /**
97 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable)
98 * @brief This API is used to enable the SoC-PLL output clock
99 * @param[in] clkEnable : Enum value to enable or disable the clock
100 * - Enable : Enables clock
101 * - Disable : Disables clock
102 * @return returns zero \ref RSI_OK on success ,on failure return error code.
103 */
RSI_CLK_SocPllClkEnable(boolean_t clkEnable)104 STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable)
105 {
106 #if defined(CLOCK_ROMDRIVER_PRESENT)
107 return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_enable(clkEnable);
108 #else
109 return clk_soc_pll_clk_enable(clkEnable);
110 #endif
111 }
112
113 /**
114 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn()
115 * @brief This API is used to TurnOn the SOC_PLL
116 * @return returns zero \ref RSI_OK on success ,on failure return error code.
117 */
RSI_CLK_SocPllTurnOn()118 STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn()
119 {
120 #if defined(CLOCK_ROMDRIVER_PRESENT)
121 return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_on();
122 #else
123 return clk_soc_pll_turn_on();
124 #endif
125 }
126 /**
127 * @fn STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK,uint32_t socPllFreq,uint32_t pllRefClk)
128 * @brief This API is used to set the Soc PLL clock to particular frequency
129 * @param[in] pCLK : Pointer to the pll register instance
130 * @param[in] socPllFreq : Frequency value in Mhz for Soc_Pll_Clk .
131 * @param[in] pllRefClk : Frequency value in Mhz for Reference clk. Please refer # NOTE
132 * @return returns zero \ref RSI_OK on success ,on failure return error code.
133 * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported
134 */
RSI_CLK_SetSocPllFreq(const M4CLK_Type * pCLK,uint32_t socPllFreq,uint32_t pllRefClk)135 STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk)
136 {
137 rsi_error_t ret = (rsi_error_t)0;
138 system_clocks.soc_pll_clock = socPllFreq;
139
140 /* TurnON the SOC_PLL */
141 RSI_CLK_SocPllTurnOn();
142 if (pllRefClk == XTAL_CLK_FREQ) //avoid if XTAL req is already done
143 {
144 #if SL_WIFI_COMPONENT_INCLUDED
145 /* Notify NWP that M4 requires XTAL clock source */
146 sli_si91x_xtal_turn_on_request_from_m4_to_TA();
147 #endif
148 PLL_REF_CLK_CONFIG_REG &= SELECT_XTAL_MHZ_CLOCK; // Selecting the XTAL as PLL reference clock
149 }
150
151 SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = 0xD900;
152 #if defined(CLOCK_ROMDRIVER_PRESENT)
153 ret = ROMAPI_M4SS_CLK_API->clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk);
154 #else
155
156 ret = clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk);
157 #endif
158 if (ret != RSI_OK) {
159 return ret;
160 } else {
161 socPllFreq /= 1000000;
162 /*if SOC PLL frequency is greater than 90Mhz */
163 if (socPllFreq < 90) {
164 /* Change the power state from PS4 to PS3 */
165 RSI_PS_PowerStateChangePs4toPs3();
166 /* Configure DCDC to give lower output voltage */
167 RSI_PS_SetDcDcToLowerVoltage();
168 }
169 if ((socPllFreq > 90) && (!(BATT_FF->MCU_PMU_LDO_CTRL_CLEAR & MCU_SOC_LDO_LVL))) {
170 /* Change the power state from PS3 to PS4 */
171 RSI_PS_SetDcDcToHigerVoltage();
172 /* Configure DCDC to give higher output voltage.*/
173 RSI_PS_PowerStateChangePs3toPs4();
174 }
175 }
176 return RSI_OK;
177 }
178
179 /**
180 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK , boolean_t clk_en,uint16_t
181 * divFactor,uint16_t nFactor,uint16_t mFactor,uint16_t fCwf,
182 * uint16_t dcofixsel,uint16_t ldoprog)
183 * @brief This API is used to configure the SOC PLL clock frequency
184 * @param[in] pCLK : Pointer to the pll register instance
185 * @param[in] clk_en : To enable the soc_pll_clk output enable
186 * @param[in] divFactor : PLL post division factor
187 * @param[in] nFactor : N factor of PLL
188 * @param[in] mFactor : M factor of PLL
189 * @param[in] fCwf : Fractional Frequency Control Word. For below 200MHz fcwF is 0 and above 200Mhz if the frequency is odd program FCW_F as 8192
190 * @param[in] dcofixsel : Dco Fixed Ring select. Please refer # Note
191 * @param[in] ldoprog : SOCPLL LDO output voltage select. Please refer # Note
192 * @return returns zero \ref RSI_OK (0) on success ,on failure return error code.
193 * @note For <= 200Mhz ---> ldo_prog =4 and dco_fix_sel=1
194 * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0
195 * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2
196 */
RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type * pCLK,boolean_t clk_en,uint16_t divFactor,uint16_t nFactor,uint16_t mFactor,uint16_t fCwf,uint16_t dcofixsel,uint16_t ldoprog)197 STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK,
198 boolean_t clk_en,
199 uint16_t divFactor,
200 uint16_t nFactor,
201 uint16_t mFactor,
202 uint16_t fCwf,
203 uint16_t dcofixsel,
204 uint16_t ldoprog)
205 {
206 #if defined(CLOCK_ROMDRIVER_PRESENT)
207 return ROMAPI_M4SS_CLK_API
208 ->clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog);
209 #else
210 return clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog);
211 #endif
212 }
213
214 /**
215 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK)
216 * @brief This API is used to Enables the SoC-PLL
217 * @param[in] pCLK : Pointer to the pll register instance
218 * @return returns zero \ref RSI_OK on success ,on failure return error code.
219 */
RSI_CLK_SocPllClkSet(const M4CLK_Type * pCLK)220 STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK)
221 {
222 #if defined(CLOCK_ROMDRIVER_PRESENT)
223 return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_set(pCLK);
224 #else
225 return clk_soc_pll_clk_set(pCLK);
226 #endif
227 }
228
229 /**
230 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable)
231 * @brief This API is used to enable bypass clock
232 * @param[in] clkEnable : Enum value to enable or disable the clock
233 * - Enable (1) : Enables bypass clock
234 * - Disable (0) : Disables bypass clock
235 * @return returns zero \ref RSI_OK on success ,on failure return error code.
236 */
RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable)237 STATIC INLINE rsi_error_t RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable)
238 {
239 #if defined(CLOCK_ROMDRIVER_PRESENT)
240 return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_bypass_enable(clkEnable);
241 #else
242 return clk_soc_pll_clk_bypass_enable(clkEnable);
243 #endif
244 }
245
246 /**
247 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkReset()
248 * @brief This API is used to Reset the Soc_pll_clk
249 * @return returns zero \ref RSI_OK on success ,on failure return error code.
250 */
RSI_CLK_SocPllClkReset()251 STATIC INLINE rsi_error_t RSI_CLK_SocPllClkReset()
252 {
253 #if defined(CLOCK_ROMDRIVER_PRESENT)
254 return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_reset();
255 #else
256 return clk_soc_pll_clk_reset();
257 #endif
258 }
259
260 /**
261 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllPdEnable(boolean_t en)
262 * @brief This API is used to enable the PdEnable(power down)
263 * @param[in] en : Enable or disable the PdEnable
264 * - Enable : Enables bypass clock
265 * - Disable : Disables bypass clock
266 * @return returns zero \ref RSI_OK on success ,on failure return error code.
267 */
RSI_CLK_SocPllPdEnable(boolean_t en)268 STATIC INLINE rsi_error_t RSI_CLK_SocPllPdEnable(boolean_t en)
269 {
270 #if defined(CLOCK_ROMDRIVER_PRESENT)
271 return ROMAPI_M4SS_CLK_API->clk_soc_pll_pd_enable(en);
272 #else
273 return clk_soc_pll_pd_enable(en);
274 #endif
275 }
276
277 /**
278 * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff()
279 * @brief This API is used to TurnOff the SOC_PLL
280 * @return returns zero \ref RSI_OK on success ,on failure return error code.
281 */
RSI_CLK_SocPllTurnOff()282 STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff()
283 {
284 #if defined(CLOCK_ROMDRIVER_PRESENT)
285 return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_off();
286 #else
287 return clk_soc_pll_turn_off();
288 #endif
289 }
290
291 /**
292 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable)
293 * @brief This API is used to enable the I2s_PLL output clock
294 * @param[in] clkEnable : Enum value to enable or disable the clock
295 * - Enable(1) : Enables clock for i2s
296 * - Disable(0) : Disables clock for i2s
297 * @return returns zero \ref RSI_OK on success ,on failure return error code.
298 */
RSI_CLK_I2sPllClkEnable(boolean_t clkEnable)299 STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable)
300 {
301 #if defined(CLOCK_ROMDRIVER_PRESENT)
302 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_enable(clkEnable);
303 #else
304 return clk_i2s_pll_clk_enable(clkEnable);
305 #endif
306 }
307
308 /**
309 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable)
310 * @brief This API is used to enable bypass clock
311 * @param[in] clkEnable : Enum value to enable or disable the clock
312 * - Enable : Enables bypass clock for i2s
313 * - Disable : Disables bypass clock for i2s
314 * @return returns zero \ref RSI_OK on success ,on failure return error code.
315 */
RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable)316 STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable)
317 {
318 #if defined(CLOCK_ROMDRIVER_PRESENT)
319 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_bypass_enable(clkEnable);
320 #else
321 return clk_i2s_pll_clk_bypass_enable(clkEnable);
322 #endif
323 }
324
325 /**
326 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllPdEnable(boolean_t en)
327 * @brief This API is used to enable the PdEnable(power down)
328 * @param[in] en : Enable or disable the PdEnable
329 * @return returns zero \ref RSI_OK on success ,on failure return error code.
330 */
RSI_CLK_I2sPllPdEnable(boolean_t en)331 STATIC INLINE rsi_error_t RSI_CLK_I2sPllPdEnable(boolean_t en)
332 {
333 #if defined(CLOCK_ROMDRIVER_PRESENT)
334 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_pd_enable(en);
335 #else
336 return clk_i2s_pll_pd_enable(en);
337 #endif
338 }
339
340 /**
341 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOff()
342 * @brief This API is used to TurnOff the I2s_PLL
343 * @return returns zero \ref RSI_OK on success ,on failure return error code.
344 */
RSI_CLK_I2sPllTurnOff()345 STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOff()
346 {
347 #if defined(CLOCK_ROMDRIVER_PRESENT)
348 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_turn_off();
349 #else
350 return clk_i2s_pll_turn_off();
351 #endif
352 }
353
354 /**
355 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn()
356 * @brief This API is used to TurnOn the I2s_PLL
357 * @return returns zero \ref RSI_OK on success ,on failure return error code.
358 */
RSI_CLK_I2sPllTurnOn()359 STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn()
360 {
361 #if defined(CLOCK_ROMDRIVER_PRESENT)
362 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_turn_on();
363 #else
364 return clk_i2s_pll_turn_on();
365 #endif
366 }
367
368 /**
369 * @fn STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK,uint32_t i2sPllFreq, uint32_t fXtal)
370 * @brief This API is used to set the I2s_pll clock to particular frequency
371 * @param[in] pCLK : Pointer to the pll register instance
372 * @param[in] i2sPllFreq : Frequency value in Mhz for I2S_PLL Clk .
373 * @param[in] fXtal : Frequency value in Mhz for crystal oscillator frequency.
374 * @return returns zero \ref RSI_OK on success ,on failure return error code.
375 */
RSI_CLK_SetI2sPllFreq(const M4CLK_Type * pCLK,uint32_t i2sPllFreq,uint32_t fXtal)376 STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal)
377 {
378 system_clocks.i2s_pll_clock = i2sPllFreq;
379 /* TurnON the I2S_PLL */
380 RSI_CLK_I2sPllTurnOn();
381 #if SL_WIFI_COMPONENT_INCLUDED
382 /* Notify NWP that M4 requires XTAL clock source */
383 sli_si91x_xtal_turn_on_request_from_m4_to_TA();
384 #endif
385 SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG9) = 0xD900;
386 #if defined(CLOCK_ROMDRIVER_PRESENT)
387 return ROMAPI_M4SS_CLK_API->clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal);
388 #else
389 return clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal);
390 #endif
391 }
392
393 /**
394 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type *pCLK,uint16_t u16DivFactor1,
395 * uint16_t u16DivFactor2,uint16_t nFactor,uint16_t mFactor,
396 * uint16_t fcwF)
397 * @brief This API is used to divide I2s_PLL Clock
398 * @param[in] pCLK : Pointer to the pll register instance
399 * @param[in] u16DivFactor1 : Post Division factor1. See user manual for more info.
400 * @param[in] u16DivFactor2 : Post Division factor2. See user manual for more info.
401 * @param[in] nFactor : N factor for PLL. See user manual for more info.
402 * @param[in] mFactor : M factor for PLL. See user manual for more info.
403 * @param[in] fcwF : Fractional Frequency Control Word.
404 * @return returns zero \ref RSI_OK on success ,on failure return error code.
405 */
RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type * pCLK,uint16_t u16DivFactor1,uint16_t u16DivFactor2,uint16_t nFactor,uint16_t mFactor,uint16_t fcwF)406 STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type *pCLK,
407 uint16_t u16DivFactor1,
408 uint16_t u16DivFactor2,
409 uint16_t nFactor,
410 uint16_t mFactor,
411 uint16_t fcwF)
412 {
413 #if defined(CLOCK_ROMDRIVER_PRESENT)
414 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_set_freq_div(pCLK, u16DivFactor1, u16DivFactor2, nFactor, mFactor, fcwF);
415 #else
416 return clk_i2s_pll_set_freq_div(pCLK, u16DivFactor1, u16DivFactor2, nFactor, mFactor, fcwF);
417 #endif
418 }
419
420 /**
421 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(const M4CLK_Type *pCLK)
422 * @brief This API is used to set the I2s_pll_clk
423 * @param[in] pCLK : Pointer to the pll register instance
424 * @return returns zero \ref RSI_OK on success ,on failure return error code.
425 */
RSI_CLK_I2sPllClkSet(const M4CLK_Type * pCLK)426 STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(const M4CLK_Type *pCLK)
427 {
428 #if defined(CLOCK_ROMDRIVER_PRESENT)
429 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_set(pCLK);
430 #else
431 return clk_i2s_pll_clk_set(pCLK);
432 #endif
433 }
434
435 /**
436 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkReset()
437 * @brief This API is used to reset the I2s_pll_clk
438 * @return returns zero \ref RSI_OK on success ,on failure return error code.
439 */
RSI_CLK_I2sPllClkReset()440 STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkReset()
441 {
442 #if defined(CLOCK_ROMDRIVER_PRESENT)
443 return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_reset();
444 #else
445 return clk_i2s_pll_clk_reset();
446 #endif
447 }
448
449 /**
450 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkEnable(boolean_t clkEnable)
451 * @brief This API is used to enable the Intf_PLL output clock
452 * @param[in] clkEnable : Enum value to enable or disable the clock
453 * - Enable(1) : Enables clock
454 * - Disable(0) : Disables clock
455 * @return returns zero \ref RSI_OK on success ,on failure return error code.
456 */
RSI_CLK_IntfPllClkEnable(boolean_t clkEnable)457 STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkEnable(boolean_t clkEnable)
458 {
459 #if defined(CLOCK_ROMDRIVER_PRESENT)
460 return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_enable(clkEnable);
461 #else
462 return clk_intf_pll_clk_enable(clkEnable);
463 #endif
464 }
465
466 /**
467 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllPdEnable(boolean_t en)
468 * @brief This API is used to enable the PdEnable(power down)
469 * @param[in] en : Enable or disable the PdEnable
470 * @return returns zero \ref RSI_OK on success ,on failure return error code.
471 */
RSI_CLK_IntfPllPdEnable(boolean_t en)472 STATIC INLINE rsi_error_t RSI_CLK_IntfPllPdEnable(boolean_t en)
473 {
474 #if defined(CLOCK_ROMDRIVER_PRESENT)
475 return ROMAPI_M4SS_CLK_API->clk_intf_pll_pd_enable(en);
476 #else
477 return clk_intf_pll_pd_enable(en);
478 #endif
479 }
480
481 /**
482 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff()
483 * @brief This API is used to TurnOff the Intf_PLL
484 * @return returns zero \ref RSI_OK on success ,on failure return error code.
485 */
RSI_CLK_IntfPLLTurnOff()486 STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff()
487 {
488 #if defined(CLOCK_ROMDRIVER_PRESENT)
489 return ROMAPI_M4SS_CLK_API->clk_intf_pll_turn_off();
490 #else
491 return clk_intf_pll_turn_off();
492 #endif
493 }
494
495 /**
496 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOn()
497 * @brief This API is used to TurnOn the Intf_PLL
498 * @return returns zero \ref RSI_OK on success ,on failure return error code.
499 */
RSI_CLK_IntfPLLTurnOn()500 STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOn()
501 {
502 #if defined(CLOCK_ROMDRIVER_PRESENT)
503 return ROMAPI_M4SS_CLK_API->clk_intf_pll_turn_on();
504 #else
505 return clk_intf_pll_turn_on();
506 #endif
507 }
508 /**
509 * @fn STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(const M4CLK_Type *pCLK,uint32_t intfPllFreq,uint32_t pllRefClk)
510 * @brief This API is used to set the INTFPLL clock to particular frequency
511 * @param[in] pCLK : Pointer to the pll register instance
512 * @param[in] intfPllFreq : Frequency value in Mhz for INTFPLL Clk .
513 * @param[in] pllRefClk : Frequency value in Mhz for Reference clk. Please refer # NOTE
514 * @return returns zero \ref RSI_OK on success ,on failure return error code.
515 * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported
516 */
RSI_CLK_SetIntfPllFreq(const M4CLK_Type * pCLK,uint32_t intfPllFreq,uint32_t pllRefClk)517 STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk)
518 {
519 rsi_error_t error = (rsi_error_t)0;
520 system_clocks.intf_pll_clock = intfPllFreq;
521 /* TurnON the INTF_PLL */
522 RSI_CLK_IntfPLLTurnOn();
523
524 #if SL_WIFI_COMPONENT_INCLUDED
525 if (pllRefClk == XTAL_CLK_FREQ) //avoid if XTAL req is already done
526 {
527 /* Notify NWP that M4 requires XTAL clock source */
528 sli_si91x_xtal_turn_on_request_from_m4_to_TA();
529 PLL_REF_CLK_CONFIG_REG &= SELECT_XTAL_MHZ_CLOCK; // Selecting the XTAL as PLL reference clock
530 }
531 #endif
532 SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG9) = 0xD900;
533 #if defined(CLOCK_ROMDRIVER_PRESENT)
534 error = ROMAPI_M4SS_CLK_API->clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk);
535 #else
536 error = clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk);
537 #endif
538 if (error != RSI_OK) {
539 return error;
540 } else {
541 /*if SOC PLL frequency is greater than 90Mhz */
542 if (intfPllFreq < 90) {
543 /* Change the power state from PS4 to PS3 */
544 RSI_PS_PowerStateChangePs4toPs3();
545 /* Configure DCDC to give lower output voltage */
546 RSI_PS_SetDcDcToLowerVoltage();
547 }
548 if ((intfPllFreq > 90) && (!(BATT_FF->MCU_PMU_LDO_CTRL_CLEAR & MCU_SOC_LDO_LVL))) {
549 /* Change the power state from PS3 to PS4 */
550 RSI_PS_SetDcDcToHigerVoltage();
551 /* Configure DCDC to give higher output voltage.*/
552 RSI_PS_PowerStateChangePs3toPs4();
553 }
554 }
555 return RSI_OK;
556 }
557
558 /**
559 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type *pCLK , boolean_t clk_en,
560 * uint16_t divFactor,uint16_t nFactor,uint16_t mFactor,
561 * uint16_t fcwF,uint16_t dcoFixSel,uint16_t ldoProg)
562 * @brief This API is used to divide the Intf PLL clock frequency
563 * @param[in] pCLK : Pointer to the pll register instance
564 * @param[in] clk_en : Enble the intf_pll_clk output enale
565 * @param[in] divFactor : PLL post division factor ,see user for more info
566 * @param[in] nFactor : N factor of PLL , see user manual for more info
567 * @param[in] mFactor : M factor of PLL , see user manual for more info
568 * @param[in] fcwF : Fractional Frequency Control Word. For below 200MHz fcwF is 0 and above 200Mhz if the frequency is odd program FCW_F as 8192
569 * @param[in] dcoFixSel : Dco Fixed Ring select. Please refer # Note
570 * @param[in] ldoProg : INTFPLL LDO output voltage select. Please refer # Note
571 * @return returns zero \ref RSI_OK on success ,on failure return error code.
572 * @note For <= 200Mhz ---> ldo_prog =4 and dco_fix_sel=1
573 * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0
574 * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2
575 */
RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type * pCLK,boolean_t clk_en,uint16_t divFactor,uint16_t nFactor,uint16_t mFactor,uint16_t fcwF,uint16_t dcoFixSel,uint16_t ldoProg)576 STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type *pCLK,
577 boolean_t clk_en,
578 uint16_t divFactor,
579 uint16_t nFactor,
580 uint16_t mFactor,
581 uint16_t fcwF,
582 uint16_t dcoFixSel,
583 uint16_t ldoProg)
584 {
585 #if defined(CLOCK_ROMDRIVER_PRESENT)
586 return ROMAPI_M4SS_CLK_API
587 ->clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg);
588 #else
589 return clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg);
590 #endif
591 }
592
593 /**
594 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable)
595 * @brief This API is used to enable bypass clock
596 * @param[in] clkEnable : is enum value to enable or disable the clock
597 * - Enable : Enables bypass clock
598 * - Disable : Disables bypass clock
599 * @return returns zero \ref RSI_OK on success ,on failure return error code.
600 */
RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable)601 STATIC INLINE rsi_error_t RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable)
602 {
603 #if defined(CLOCK_ROMDRIVER_PRESENT)
604 return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_bypass_enable(clkEnable);
605 #else
606 return clk_intf_pll_clk_bypass_enable(clkEnable);
607 #endif
608 }
609
610 /**
611
612 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset()
613 * @brief This API is used to Reset the Intf_pll_clk
614 * @return returns zero \ref RSI_OK on success ,on failure return error code.
615 */
RSI_CLK_IntfPllClkReset()616 STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset()
617 {
618 #if defined(CLOCK_ROMDRIVER_PRESENT)
619 return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_reset();
620 #else
621 return clk_intf_pll_clk_reset();
622 #endif
623 }
624
625 /**
626 * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(const M4CLK_Type *pCLK)
627 * @brief This API is used to Enables the Intf-PLL
628 * @param[in] pCLK : Pointer to the pll register instance
629 * @return returns zero \ref RSI_OK on success ,on failure return error code.
630 */
RSI_CLK_IntfPllClkSet(const M4CLK_Type * pCLK)631 STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(const M4CLK_Type *pCLK)
632 {
633 #if defined(CLOCK_ROMDRIVER_PRESENT)
634 return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_set(pCLK);
635 #else
636 return clk_intf_pll_clk_set(pCLK);
637 #endif
638 }
639
640 /**
641 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable1(M4CLK_Type *pCLK ,uint32_t flags)
642 * @brief This API is used to enable the peripheral clocks for SET1 register
643 * @param[in] pCLK : Pointer to the pll register instance
644 * @param[in] flags : ORed values of peripheral bits to be enbled.
645 * - \ref USART1_PCLK_ENABLE
646 * - \ref USART1_SCLK_ENABLE
647 * - \ref USART2_PCLK_ENABLE
648 * - \ref USART2_SCLK_ENABLE
649 * - \ref CT_CLK_ENABLE
650 * - \ref CT_PCLK_ENABLE
651 * - \ref ICACHE_CLK_ENABLE
652 * - \ref ICACHE_CLK_2X_ENABLE
653 * - \ref GPDMA_HCLK_ENABLE
654 * - \ref SOC_PLL_SPI_CLK_ENABLE
655 * - \ref IID_CLK_ENABLE
656 * - \ref SDIO_SYS_HCLK_ENABLE
657 * - \ref CRC_CLK_ENABLE_M4
658 * - \ref M4SS_UM_CLK_STATIC_EN
659 * - \ref ETH_HCLK_ENABLE
660 * - \ref HWRNG_PCLK_ENABLE
661 * - \ref GNSS_MEM_CLK_ENABLE
662 * - \ref CCI_PCLK_ENABLE
663 * - \ref CCI_HCLK_ENABLE
664 * - \ref CCI_CLK_ENABLE
665 * - \ref MASK_HOST_CLK_WAIT_FIX
666 * - \ref MASK31_HOST_CLK_CNT
667 * - \ref SD_MEM_INTF_CLK_ENABLE
668 * - \ref MASK_HOST_CLK_AVAILABLE_FIX
669 * @return returns zero \ref RSI_OK on success ,on failure return error code.
670 *
671 * @b Example
672 * - RSI_Clk_PeripheralClkEnable1(&M4CLK ,(USART1_PCLK_ENABLE | USART1_SCLK_ENABLE ));
673 */
RSI_CLK_PeripheralClkEnable1(M4CLK_Type * pCLK,uint32_t flags)674 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable1(M4CLK_Type *pCLK, uint32_t flags)
675 {
676 #if defined(CLOCK_ROMDRIVER_PRESENT)
677 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable1(pCLK, flags);
678 #else
679 return clk_peripheral_clk_enable1(pCLK, flags);
680 #endif
681 }
682
683 /**
684 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable1(M4CLK_Type *pCLK ,uint32_t flags)
685 * @brief This API is used to disable the peripheral clocks for CLR1 register
686 * @param[in] pCLK : Pointer to the pll register instance
687 * @param[in] flags : ORed values of peripheral bits to be enbled.
688 * - \ref USART1_PCLK_ENABLE
689 * - \ref USART1_SCLK_ENABLE
690 * - \ref USART2_PCLK_ENABLE
691 * - \ref USART2_SCLK_ENABLE
692 * - \ref CT_CLK_ENABLE
693 * - \ref CT_PCLK_ENABLE
694 * - \ref ICACHE_CLK_ENABLE
695 * - \ref ICACHE_CLK_2X_ENABLE
696 * - \ref GPDMA_HCLK_ENABLE
697 * - \ref SOC_PLL_SPI_CLK_ENABLE
698 * - \ref IID_CLK_ENABLE
699 * - \ref SDIO_SYS_HCLK_ENABLE
700 * - \ref CRC_CLK_ENABLE_M4
701 * - \ref M4SS_UM_CLK_STATIC_EN
702 * - \ref ETH_HCLK_ENABLE
703 * - \ref HWRNG_PCLK_ENABLE
704 * - \ref GNSS_MEM_CLK_ENABLE
705 * - \ref CCI_PCLK_ENABLE
706 * - \ref CCI_HCLK_ENABLE
707 * - \ref CCI_CLK_ENABLE
708 * - \ref MASK_HOST_CLK_WAIT_FIX
709 * - \ref MASK31_HOST_CLK_CNT
710 * - \ref SD_MEM_INTF_CLK_ENABLE
711 * - \ref MASK_HOST_CLK_AVAILABLE_FIX
712 * @return returns zero \ref RSI_OK on success ,on failure return error code.
713 *
714 * @b Example
715 * - RSI_Clk_PeripheralClkDisable1(&M4CLK ,(USART1_PCLK_ENABLE | USART1_SCLK_ENABLE ));
716 */
RSI_CLK_PeripheralClkDisable1(M4CLK_Type * pCLK,uint32_t flags)717 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable1(M4CLK_Type *pCLK, uint32_t flags)
718 {
719 #if defined(CLOCK_ROMDRIVER_PRESENT)
720 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable1(pCLK, flags);
721 #else
722 return clk_peripheral_clk_disable1(pCLK, flags);
723 #endif
724 }
725
726 /**
727 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable2(M4CLK_Type *pCLK ,uint32_t flags)
728 * @brief This API is used to enable the peripheral clocks for SET2 register
729 * @param[in] pCLK : Pointer to the pll register instance
730 * @param[in] flags : ORed values of peripheral bits to be enabled.
731 * - \ref GEN_SPI_MST1_HCLK_ENABLE
732 * - \ref CAN1_PCLK_ENABLE
733 * - \ref CAN1_CLK_ENABLE
734 * - \ref UDMA_HCLK_ENABLE
735 * - \ref I2C_BUS_CLK_ENABLE
736 * - \ref I2C_2_BUS_CLK_ENABLE
737 * - \ref SSI_SLV_PCLK_ENABLE
738 * - \ref SSI_SLV_SCLK_ENABLE
739 * - \ref QSPI_CLK_ENABLE
740 * - \ref QSPI_HCLK_ENABLE
741 * - \ref I2SM_INTF_SCLK_ENABLE
742 * - \ref I2SM_PCLK_ENABLE
743 * - \ref QE_PCLK_ENABLE
744 * - \ref MCPWM_PCLK_ENABLE
745 * - \ref SGPIO_PCLK_ENABLE
746 * - \ref EGPIO_PCLK_ENABLE
747 * - \ref ARM_CLK_ENABLE
748 * - \ref SSI_MST_PCLK_ENABLE
749 * - \ref SSI_MST_SCLK_ENABLE
750 * - \ref MEM2_CLK_ENABLE
751 * - \ref MEM_CLK_ULP_ENABLE
752 * - \ref ROM_CLK_ENABLE
753 * - \ref PLL_INTF_CLK_ENABLE
754 * - \ref SEMAPHORE_CLK_ENABLE
755 * - \ref TOT_CLK_ENABLE
756 * - \ref RMII_SOFT_RESET
757 * @return returns zero \ref RSI_OK on success ,on failure return error code.
758 *
759 * @b Example
760 * - RSI_Clk_PeripheralClkEnable2(M4CLK ,(GEN_SPI_MST1_HCLK_ENABLE | SSI_MST_PCLK_ENABLE));
761 */
RSI_CLK_PeripheralClkEnable2(M4CLK_Type * pCLK,uint32_t flags)762 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable2(M4CLK_Type *pCLK, uint32_t flags)
763 {
764 #if defined(CLOCK_ROMDRIVER_PRESENT)
765 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable2(pCLK, flags);
766 #else
767 return clk_peripheral_clk_enable2(pCLK, flags);
768 #endif
769 }
770
771 /**
772 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable2(M4CLK_Type *pCLK ,uint32_t flags)
773 * @brief This API is used to disable the peripheral clocks for CLR2 register
774 * @param[in] pCLK : Pointer to the pll register instance
775 * @param[in] flags : ORed values of peripheral bits to be enabled.
776 * - \ref GEN_SPI_MST1_HCLK_ENABLE
777 * - \ref CAN1_PCLK_ENABLE
778 * - \ref CAN1_CLK_ENABLE
779 * - \ref UDMA_HCLK_ENABLE
780 * - \ref I2C_BUS_CLK_ENABLE
781 * - \ref I2C_2_BUS_CLK_ENABLE
782 * - \ref SSI_SLV_PCLK_ENABLE
783 * - \ref SSI_SLV_SCLK_ENABLE
784 * - \ref QSPI_CLK_ENABLE
785 * - \ref QSPI_HCLK_ENABLE
786 * - \ref I2SM_INTF_SCLK_ENABLE
787 * - \ref I2SM_PCLK_ENABLE
788 * - \ref QE_PCLK_ENABLE
789 * - \ref MCPWM_PCLK_ENABLE
790 * - \ref SGPIO_PCLK_ENABLE
791 * - \ref EGPIO_PCLK_ENABLE
792 * - \ref ARM_CLK_ENABLE
793 * - \ref SSI_MST_PCLK_ENABLE
794 * - \ref SSI_MST_SCLK_ENABLE
795 * - \ref MEM2_CLK_ENABLE
796 * - \ref MEM_CLK_ULP_ENABLE
797 * - \ref ROM_CLK_ENABLE
798 * - \ref PLL_INTF_CLK_ENABLE
799 * - \ref SEMAPHORE_CLK_ENABLE
800 * - \ref TOT_CLK_ENABLE
801 * - \ref RMII_SOFT_RESET
802 * @return returns zero \ref RSI_OK on success ,on failure return error code.
803 *
804 * @b Example
805 * - RSI_Clk_PeripheralClkDisable2(M4CLK ,(GEN_SPI_MST1_HCLK_ENABLE | SSI_MST_PCLK_ENABLE));
806 */
RSI_CLK_PeripheralClkDisable2(M4CLK_Type * pCLK,uint32_t flags)807 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable2(M4CLK_Type *pCLK, uint32_t flags)
808 {
809 #if defined(CLOCK_ROMDRIVER_PRESENT)
810 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable2(pCLK, flags);
811 #else
812 return clk_peripheral_clk_disable2(pCLK, flags);
813 #endif
814 }
815
816 /**
817 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable3(M4CLK_Type *pCLK ,uint32_t flags)
818 * @brief This API is used to enable the peripheral clocks for SET3 register
819 * @param[in] pCLK : Pointer to the pll register instance
820 * @param[in] flags : ORed values of peripheral bits to be enabled.
821 * - \ref BUS_CLK_ENABLE
822 * - \ref M4_CORE_CLK_ENABLE
823 * - \ref CM_BUS_CLK_ENABLE
824 * - \ref MISC_CONFIG_PCLK_ENABLE
825 * - \ref EFUSE_CLK_ENABLE
826 * - \ref ICM_CLK_ENABLE
827 * - \ref MEM1_CLK_ENABLE
828 * - \ref MEM3_CLK_ENABLE
829 * - \ref USB_PHY_CLK_IN_ENABLE
830 * - \ref QSPI_CLK_ONEHOT_ENABLE
831 * - \ref QSPI_M4_SOC_SYNC
832 * - \ref EGPIO_CLK_ENABLE
833 * - \ref I2C_CLK_ENABLE
834 * - \ref I2C_2_CLK_ENABLE
835 * - \ref EFUSE_PCLK_ENABLE
836 * - \ref SGPIO_PCLK_ENABLE
837 * - \ref TASS_M4SS_64K_SWITCH_CLK_ENABLE
838 * - \ref TASS_M4SS_128K_SWITCH_CLK_ENABLE
839 * - \ref TASS_M4SS_SDIO_SWITCH_CLK_ENABLE
840 * - \ref TASS_M4SS_USB_SWITCH_CLK_ENABLE
841 * - \ref ROM_MISC_STATIC_ENABLE
842 * - \ref M4_SOC_CLK_FOR_OTHER_ENABLE
843 * - \ref ICACHE_ENABLE
844 * @return returns zero \ref RSI_OK on success ,on failure return error code.
845 *
846 * @b Example
847 * - RSI_Clk_PeripheralClkEnable3(M4CLK ,(M4_SOC_CLK_FOR_OTHER_ENABLE | ROM_MISC_STATIC_ENABLE));
848 */
RSI_CLK_PeripheralClkEnable3(M4CLK_Type * pCLK,uint32_t flags)849 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable3(M4CLK_Type *pCLK, uint32_t flags)
850 {
851 #if defined(CLOCK_ROMDRIVER_PRESENT)
852 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable3(pCLK, flags);
853 #else
854 return clk_peripheral_clk_enable3(pCLK, flags);
855 #endif
856 }
857
858 /**
859 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable3(M4CLK_Type *pCLK ,uint32_t flags)
860 * @brief This API is used to disable the peripheral clocks for CLR3 register
861 * @param[in] pCLK : Pointer to the pll register instance
862 * @param[in] flags : ORed values of peripheral bits to be enbled.
863 * - \ref BUS_CLK_ENABLE
864 * - \ref M4_CORE_CLK_ENABLE
865 * - \ref CM_BUS_CLK_ENABLE
866 * - \ref MISC_CONFIG_PCLK_ENABLE
867 * - \ref EFUSE_CLK_ENABLE
868 * - \ref ICM_CLK_ENABLE
869 * - \ref MEM1_CLK_ENABLE
870 * - \ref MEM3_CLK_ENABLE
871 * - \ref USB_PHY_CLK_IN_ENABLE
872 * - \ref QSPI_CLK_ONEHOT_ENABLE
873 * - \ref QSPI_M4_SOC_SYNC
874 * - \ref EGPIO_CLK_ENABLE
875 * - \ref I2C_CLK_ENABLE
876 * - \ref I2C_2_CLK_ENABLE
877 * - \ref EFUSE_PCLK_ENABLE
878 * - \ref SGPIO_PCLK_ENABLE
879 * - \ref TASS_M4SS_64K_SWITCH_CLK_ENABLE
880 * - \ref TASS_M4SS_128K_SWITCH_CLK_ENABLE
881 * - \ref TASS_M4SS_SDIO_SWITCH_CLK_ENABLE
882 * - \ref TASS_M4SS_USB_SWITCH_CLK_ENABLE
883 * - \ref ROM_MISC_STATIC_ENABLE
884 * - \ref M4_SOC_CLK_FOR_OTHER_ENABLE
885 * - \ref ICACHE_ENABLE
886 * @return returns zero \ref RSI_OK on success ,on failure return error code.
887 *
888 * @b Example
889 * - RSI_Clk_PeripheralClkDisable3(M4CLK ,(M4_SOC_CLK_FOR_OTHER_ENABLE | ROM_MISC_STATIC_ENABLE));
890 */
RSI_CLK_PeripheralClkDisable3(M4CLK_Type * pCLK,uint32_t flags)891 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable3(M4CLK_Type *pCLK, uint32_t flags)
892 {
893 #if defined(CLOCK_ROMDRIVER_PRESENT)
894 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable3(pCLK, flags);
895 #else
896 return clk_peripheral_clk_disable3(pCLK, flags);
897 #endif
898 }
899
900 /**
901 * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable(M4CLK_Type *pCLK ,uint32_t flags)
902 * @brief This API is used to disable the dynamic clock gate for peripherals
903 * @param[in] pCLK : Pointer to the pll register instance
904 * @param[in] flags : ORed value of the register bits
905 * - \ref SDIO_SYS_HCLK_DYN_CTRL_DISABLE
906 * - \ref BUS_CLK_DYN_CTRL_DISABLE
907 * - \ref GPDMA_HCLK_DYN_CTRL_DISABLE
908 * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE
909 * - \ref SGPIO_PCLK_DYN_CTRL_DISABLE
910 * - \ref TOT_CLK_DYN_CTRL_DISABLE
911 * - \ref HWRNG_PCLK_DYN_CTRL_DISABLE
912 * - \ref USART1_SCLK_DYN_CTRL_DISABLE
913 * - \ref USART1_PCLK_DYN_CTRL_DISABLE
914 * - \ref USART2_SCLK_DYN_CTRL_DISABLE
915 * - \ref USART2_PCLK_DYN_CTRL_DISABLE
916 * - \ref SSI_SLV_SCLK_DYN_CTRL_DISABLE
917 * - \ref SSI_SLV_PCLK_DYN_CTRL_DISABLE
918 * - \ref I2SM_INTF_SCLK_DYN_CTRL_DISABLE
919 * - \ref SEMAPHORE_CLK_DYN_CTRL_DISABLE
920 * - \ref ARM_CLK_DYN_CTRL_DISABLE
921 * - \ref SSI_MST_SCLK_DYN_CTRL_DISABLE
922 * - \ref MEM1_CLK_DYN_CTRL_DISABLE
923 * - \ref MEM2_CLK_DYN_CTRL_DISABLE
924 * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE
925 * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE
926 * - \ref SSI_MST_PCLK_DYN_CTRL_DISABLE
927 * - \ref ICACHE_DYN_GATING_DISABLE
928 * - \ref CCI_PCLK_DYN_CTRL_DISABLE
929 * - \ref MISC_CONFIG_PCLK_DYN_CTRL_DISABLE
930 * @return returns zero \ref RSI_OK on success ,on failure return error code.
931 *
932 * @b Example
933 * - RSI_Clk_DynamicClkGateDisable(M4CLK , (SDIO_SYS_HCLK_DYN_CTRL_DISABLE | BUS_CLK_DYN_CTRL_DISABLE));
934 */
RSI_CLK_DynamicClkGateDisable(M4CLK_Type * pCLK,uint32_t flags)935 STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable(M4CLK_Type *pCLK, uint32_t flags)
936 {
937 #if defined(CLOCK_ROMDRIVER_PRESENT)
938 return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_disable(pCLK, flags);
939 #else
940 return clk_dynamic_clk_gate_disable(pCLK, flags);
941 #endif
942 }
943
944 /**
945 * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable2(M4CLK_Type *pCLK ,uint32_t flags)
946 * @brief This API is used to disable the dynamic clock gate for peripherals
947 * @param[in] pCLK : Pointer to the pll register instance
948 * @param[in] flags : ORed value of the register bits
949 * - \ref SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE
950 * - \ref I2C_BUS_DYN_CTRL_DISABLE
951 * - \ref I2C_2_BUS_CLK_DYN_CTRL_DISABLE
952 * - \ref CT_PCLK_DYN_CTRL_DISABLE
953 * - \ref CAN1_PCLK_DYN_CTRL_DISABLE
954 * - \ref EFUSE_CLK_DYN_CTRL_DISABLE
955 * - \ref EFUSE_PCLK_DYN_CTRL_DISABLE
956 * - \ref PWR_CTRL_CLK_DYN_CTRL_DISABLE
957 * @return returns zero \ref RSI_OK on success ,on failure return error code.
958 *
959 * @b Example
960 * - RSI_CLK_DynamicClkGateDisable2(M4CLK , (EFUSE_CLK_DYN_CTRL_DISABLE | EFUSE_PCLK_DYN_CTRL_DISABLE));
961 */
RSI_CLK_DynamicClkGateDisable2(M4CLK_Type * pCLK,uint32_t flags)962 STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable2(M4CLK_Type *pCLK, uint32_t flags)
963 {
964 #if defined(CLOCK_ROMDRIVER_PRESENT)
965 return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_disable2(pCLK, flags);
966 #else
967 return clk_dynamic_clk_gate_disable2(pCLK, flags);
968 #endif
969 }
970
971 /**
972 * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable(M4CLK_Type *pCLK ,uint32_t flags)
973 * @brief This API is used to enable the dynamic clock gate for peripherals
974 * @param[in] pCLK : Pointer to the pll register instance
975 * @param[in] flags : ORed value of the register bits
976 * - \ref SDIO_SYS_HCLK_DYN_CTRL_DISABLE
977 * - \ref BUS_CLK_DYN_CTRL_DISABLE
978 * - \ref GPDMA_HCLK_DYN_CTRL_DISABLE
979 * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE
980 * - \ref SGPIO_PCLK_DYN_CTRL_DISABLE
981 * - \ref TOT_CLK_DYN_CTRL_DISABLE
982 * - \ref HWRNG_PCLK_DYN_CTRL_DISABLE
983 * - \ref USART1_SCLK_DYN_CTRL_DISABLE
984 * - \ref USART1_PCLK_DYN_CTRL_DISABLE
985 * - \ref USART2_SCLK_DYN_CTRL_DISABLE
986 * - \ref USART2_PCLK_DYN_CTRL_DISABLE
987 * - \ref SSI_SLV_SCLK_DYN_CTRL_DISABLE
988 * - \ref SSI_SLV_PCLK_DYN_CTRL_DISABLE
989 * - \ref I2SM_INTF_SCLK_DYN_CTRL_DISABLE
990 * - \ref SEMAPHORE_CLK_DYN_CTRL_DISABLE
991 * - \ref ARM_CLK_DYN_CTRL_DISABLE
992 * - \ref SSI_MST_SCLK_DYN_CTRL_DISABLE
993 * - \ref MEM1_CLK_DYN_CTRL_DISABLE
994 * - \ref MEM2_CLK_DYN_CTRL_DISABLE
995 * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE
996 * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE
997 * - \ref SSI_MST_PCLK_DYN_CTRL_DISABLE
998 * - \ref ICACHE_DYN_GATING_DISABLE
999 * - \ref CCI_PCLK_DYN_CTRL_DISABLE
1000 * - \ref MISC_CONFIG_PCLK_DYN_CTRL_DISABLE
1001 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1002 *
1003 * @b Example
1004 * - RSI_Clk_DynamicClkGateEnable(M4CLK , (SDIO_SYS_HCLK_DYN_CTRL_DISABLE | BUS_CLK_DYN_CTRL_DISABLE));
1005 */
RSI_CLK_DynamicClkGateEnable(M4CLK_Type * pCLK,uint32_t flags)1006 STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable(M4CLK_Type *pCLK, uint32_t flags)
1007 {
1008 #if defined(CLOCK_ROMDRIVER_PRESENT)
1009 return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_enable(pCLK, flags);
1010 #else
1011 return clk_dynamic_clk_gate_enable(pCLK, flags);
1012 #endif
1013 }
1014
1015 /**
1016 * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable2(M4CLK_Type *pCLK ,uint32_t flags)
1017 * @brief This API is used to enable the dynamic clock gate for peripherals
1018 * @param[in] pCLK : Pointer to the pll register instance
1019 * @param[in] flags : ORed value of the register bits
1020 * - \ref SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE
1021 * - \ref I2C_BUS_DYN_CTRL_DISABLE
1022 * - \ref I2C_2_BUS_CLK_DYN_CTRL_DISABLE
1023 * - \ref CT_PCLK_DYN_CTRL_DISABLE
1024 * - \ref CAN1_PCLK_DYN_CTRL_DISABLE
1025 * - \ref EFUSE_CLK_DYN_CTRL_DISABLE
1026 * - \ref EFUSE_PCLK_DYN_CTRL_DISABLE
1027 * - \ref PWR_CTRL_CLK_DYN_CTRL_DISABLE
1028 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1029 *
1030 * @b Example
1031 * - RSI_Clk_DynamicClkGateEnable2(M4CLK , (EFUSE_CLK_DYN_CTRL_DISABLE | EFUSE_PCLK_DYN_CTRL_DISABLE));
1032 */
RSI_CLK_DynamicClkGateEnable2(M4CLK_Type * pCLK,uint32_t flags)1033 STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable2(M4CLK_Type *pCLK, uint32_t flags)
1034 {
1035 #if defined(CLOCK_ROMDRIVER_PRESENT)
1036 return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_enable2(pCLK, flags);
1037 #else
1038 return clk_dynamic_clk_gate_enable2(pCLK, flags);
1039 #endif
1040 }
1041
1042 /**
1043 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType,cdDelay delayFn)
1044 * @brief This API is used to enable the ULP reference clocks and provide delay for clock starting
1045 * @param[in] enable : To enable the particular reference clock. See \ref REF_CLK_ENABLE_T for more info
1046 * @param[in] srcType : To select the pheripheral clock or processor clk. See \ref SRC_TYPE_T for more info
1047 * @param[in] delayFn : Call back fuction used to create delay by using loops or timers in application code
1048 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1049 */
RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable,SRC_TYPE_T srcType,cdDelay delayFn)1050 STATIC INLINE rsi_error_t RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn)
1051 {
1052 #if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT)
1053 return ROMAPI_M4SS_CLK_API->ulpss_enable_ref_clks(enable, srcType, delayFn);
1054 #else
1055 return ulpss_enable_ref_clks(enable, srcType, delayFn);
1056 #endif
1057 }
1058
1059 /**
1060 * @fn STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type)
1061 * @brief This API is used to disable the ULP reference clocks
1062 * @param[in] clk_type : To enable the particular reference clock. See \ref REF_CLK_ENABLE_T for more info
1063 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1064 */
RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type)1065 STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type)
1066 {
1067 #if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT)
1068 return ROMAPI_M4SS_CLK_API->ulpss_disable_ref_clks(clk_type);
1069 #else
1070 return ulpss_disable_ref_clks(clk_type);
1071 #endif
1072 }
1073
1074 /**
1075 * @fn STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(const M4CLK_Type *pCLK ,M4SS_REF_CLK_SEL_T clkSource)
1076 * @brief This API is used to configure the m4ss_ref clocks
1077 * @param[in] pCLK : Pointer to the pll register instance
1078 * @param[in] clkSource : Enum values of different M4 ref source clocks \ref M4SS_REF_CLK_SEL_T
1079 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1080 */
RSI_CLK_M4ssRefClkConfig(const M4CLK_Type * pCLK,M4SS_REF_CLK_SEL_T clkSource)1081 STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource)
1082 {
1083 #if SL_WIFI_COMPONENT_INCLUDED
1084 if (clkSource == EXT_40MHZ_CLK) {
1085 /* Notify NWP that M4 requires XTAL clock source */
1086 sli_si91x_xtal_turn_on_request_from_m4_to_TA();
1087 }
1088 #endif
1089 return clk_m4ss_ref_clk_config(pCLK, clkSource);
1090 }
1091
1092 /**
1093 * @fn STATIC INLINE rsi_error_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK ,M4_SOC_CLK_SRC_SEL_T clkSource ,
1094 uint32_t divFactor)
1095 * @brief This API is used to configure the m4_soc clocks
1096 * @param[in] pCLK : Pointer to the pll register instance
1097 * @param[in] clkSource : Enum values of different SOC source clocks.See #M4_SOC_CLK_SRC_SEL_T and NOTE for more info
1098 * @param[in] divFactor : division value for M4SOC clock
1099 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1100 * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first
1101 * - For using SocPllCLK clksource need to configure SocPll frequency. For that need to call \ref RSI_CLK_SetSocPllFreq Api first
1102 * - For using IntfPllCLK clksource need to configure IntfPll frequency. For that need to call \ref RSI_CLK_SetIntfPllFreq Api first
1103 * - For using Sleep clksource need to configure Sleep Clock. For that need to call \ref RSI_CLK_SlpClkConfig Api first
1104 */
RSI_CLK_M4SocClkConfig(M4CLK_Type * pCLK,M4_SOC_CLK_SRC_SEL_T clkSource,uint32_t divFactor)1105 STATIC INLINE rsi_error_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor)
1106 {
1107 return clk_m4_soc_clk_config(pCLK, clkSource, divFactor);
1108 }
1109
1110 /**
1111 * @fn STATIC INLINE rsi_error_t RSI_CLK_QspiClkConfig(M4CLK_Type *pCLK ,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn,
1112 boolean_t OddDivEn,uint32_t divFactor)
1113 * @brief This API is used to configure the Qspi clocks
1114 * @param[in] pCLK : Pointer to the pll register instance
1115 * @param[in] clkSource : Enum valuse for Qspi clock sources to be selected.
1116 see possible Qspi clock sources at \ref QSPI_CLK_SRC_SEL_T
1117 * @param[in] swalloEn : To enable or disable the swallo functionality. See user manual for more info
1118 * - 1 : swalloEn enabled
1119 * - 0 : swalloEn disabled
1120 * @param[in] OddDivEn : To enable or disable the odd div functionality. See user manual for more info
1121 * - 1 : OddDivEn enabled
1122 * - 0 : OddDivEn disabled
1123 * @param[in] divFactor : Division value for Qspi Clock
1124 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1125 * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency.
1126 \n For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first
1127 */
RSI_CLK_QspiClkConfig(M4CLK_Type * pCLK,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn,boolean_t OddDivEn,uint32_t divFactor)1128 STATIC INLINE rsi_error_t RSI_CLK_QspiClkConfig(M4CLK_Type *pCLK,
1129 QSPI_CLK_SRC_SEL_T clkSource,
1130 boolean_t swalloEn,
1131 boolean_t OddDivEn,
1132 uint32_t divFactor)
1133 {
1134 #if defined(CLOCK_ROMDRIVER_PRESENT)
1135 return ROMAPI_M4SS_CLK_API->clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor);
1136 #else
1137 return clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor);
1138 #endif
1139 }
1140 #if defined(SLI_SI917B0) || defined(SLI_SI915)
1141
1142 /**
1143 * @fn STATIC INLINE rsi_error_t RSI_CLK_Qspi2ClkConfig(M4CLK_Type *pCLK ,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn,
1144 boolean_t OddDivEn,uint32_t divFactor)
1145 * @brief This API is used to configure the Qspi clocks
1146 * @param[in] pCLK : Pointer to the pll register instance
1147 * @param[in] clkSource : Enum valuse for Qspi clock sources to be selected.
1148 see possible Qspi clock sources at \ref QSPI_CLK_SRC_SEL_T
1149 * @param[in] swalloEn : To enable or disable the swallo functionality. See user manual for more info
1150 * - 1 : swalloEn enabled
1151 * - 0 : swalloEn disabled
1152 * @param[in] OddDivEn : To enable or disable the odd div functionality. See user manual for more info
1153 * - 1 : OddDivEn enabled
1154 * - 0 : OddDivEn disabled
1155 * @param[in] divFactor : Division value for Qspi Clock
1156 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1157 * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency.
1158 \n For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first
1159 */
RSI_CLK_Qspi2ClkConfig(M4CLK_Type * pCLK,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn,boolean_t OddDivEn,uint32_t divFactor)1160 STATIC INLINE rsi_error_t RSI_CLK_Qspi2ClkConfig(M4CLK_Type *pCLK,
1161 QSPI_CLK_SRC_SEL_T clkSource,
1162 boolean_t swalloEn,
1163 boolean_t OddDivEn,
1164 uint32_t divFactor)
1165 {
1166 #if defined(CLOCK_ROMDRIVER_PRESENT)
1167 return ROMAPI_M4SS_CLK_API->clk_qspi_2_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor);
1168 #else
1169 return clk_qspi_2_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor);
1170 #endif
1171 }
1172 #endif
1173 /**
1174 * @fn STATIC INLINE rsi_error_t RSI_CLK_UsartClkConfig(M4CLK_Type *pCLK ,CLK_ENABLE_T clkType,boolean_t FracDivEn,
1175 EN_USART_T enUsart,USART_CLK_SRC_SEL_T clkSource,uint32_t divFactor)
1176 * @brief This API is used to configure the Usart clocks
1177 * @param[in] pCLK : Pointer to the pll register instance
1178 * @param[in] clkType : Boolean value to enable or disable clock mode
1179 * - 1 Enable : Enables the Usart clock
1180 * - 0 Disable: Disables the Usart clock
1181 * @param[in] FracDivEn : To enable or disable Fractional Division functionality
1182 * - 1 : FracDivEn enabled
1183 * - 0 : FracDivEn disabled
1184 * @param[in] enUsart : Enum values for different Usart instances see possible bypass clock sources at \ref EN_USART_T
1185 * @param[in] clkSource : Enum values for Usart clock sources to be selected. see possible Usart clock sources at #USART_CLK_SRC_SEL_T
1186 * @param[in] divFactor is the division value for Usart Clock
1187 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1188 * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call #ROM_CLK_M4ssRefClkConfig Api first
1189 */
RSI_CLK_UsartClkConfig(M4CLK_Type * pCLK,CLK_ENABLE_T clkType,boolean_t FracDivEn,EN_USART_T enUsart,USART_CLK_SRC_SEL_T clkSource,uint32_t divFactor)1190 STATIC INLINE rsi_error_t RSI_CLK_UsartClkConfig(M4CLK_Type *pCLK,
1191 CLK_ENABLE_T clkType,
1192 boolean_t FracDivEn,
1193 EN_USART_T enUsart,
1194 USART_CLK_SRC_SEL_T clkSource,
1195 uint32_t divFactor)
1196 {
1197 #if defined(CLOCK_ROMDRIVER_PRESENT)
1198 return ROMAPI_M4SS_CLK_API->clk_usart_clk_config(pCLK, clkType, FracDivEn, enUsart, clkSource, divFactor);
1199 #else
1200 return clk_usart_clk_config(pCLK, clkType, FracDivEn, enUsart, clkSource, divFactor);
1201 #endif
1202 }
1203
1204 /**
1205 * @fn STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkConfig(M4CLK_Type *pCLK ,CLK_ENABLE_T clkType ,
1206 SSI_MST_CLK_SRC_SEL_T clkSource ,uint32_t divFactor)
1207 * @brief This API is used to configure the SSI clocks
1208 * @param[in] pCLK : Pointer to the pll register instance
1209 * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info.
1210 * @param[in] clkSource : Enum values for SSI clock sources to be selected. see possible SSI clock sources at #SSI_MST_CLK_SRC_SEL_T
1211 * @param[in] divFactor : is the division value for SSI Clock
1212 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1213 */
RSI_CLK_SsiMstClkConfig(M4CLK_Type * pCLK,CLK_ENABLE_T clkType,SSI_MST_CLK_SRC_SEL_T clkSource,uint32_t divFactor)1214 STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkConfig(M4CLK_Type *pCLK,
1215 CLK_ENABLE_T clkType,
1216 SSI_MST_CLK_SRC_SEL_T clkSource,
1217 uint32_t divFactor)
1218 {
1219 #if defined(CLOCK_ROMDRIVER_PRESENT)
1220 return ROMAPI_M4SS_CLK_API->clk_ssi_mst_clk_config(pCLK, clkType, clkSource, divFactor);
1221 #else
1222 return clk_ssi_mst_clk_config(pCLK, clkType, clkSource, divFactor);
1223 #endif
1224 }
1225
1226 #ifdef CHIP_9118
1227 /**
1228 * @fn STATIC INLINE rsi_error_t RSI_CLK_SdMemClkConfig(M4CLK_Type *pCLK ,boolean_t swalloEn ,SDMEM_CLK_SRC_SEL_T clkSource ,
1229 uint32_t divFactor)
1230 * @brief This API is used to configure the SdMem clocks
1231 * @param[in] pCLK : Pointer to pll register instance
1232 * @param[in] swalloEn : Enable or disable the swallo functionality
1233 * - 1 : swalloEn enabled
1234 * - 0 : swalloEn disabled
1235 * @param[in] clkSource : Enum values for SdMem clock sources to be selected. see possible SdMem clock sources at #SDMEM_CLK_SRC_SEL_T
1236 * @param[in] divFactor : Division value for SdMem Clock
1237 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1238 */
RSI_CLK_SdMemClkConfig(M4CLK_Type * pCLK,boolean_t swalloEn,SDMEM_CLK_SRC_SEL_T clkSource,uint32_t divFactor)1239 STATIC INLINE rsi_error_t RSI_CLK_SdMemClkConfig(M4CLK_Type *pCLK,
1240 boolean_t swalloEn,
1241 SDMEM_CLK_SRC_SEL_T clkSource,
1242 uint32_t divFactor)
1243 {
1244 #if defined(CLOCK_ROMDRIVER_PRESENT)
1245 return ROMAPI_M4SS_CLK_API->clk_sd_mem_clk_config(pCLK, swalloEn, clkSource, divFactor);
1246 #else
1247 return clk_sd_mem_clk_config(pCLK, swalloEn, clkSource, divFactor);
1248 #endif
1249 }
1250 #endif
1251
1252 /**
1253 * @fn STATIC INLINE rsi_error_t RSI_CLK_CtClkConfig(M4CLK_Type *pCLK ,CT_CLK_SRC_SEL_T clkSource ,uint32_t divFactor,
1254 CLK_ENABLE_T clkType)
1255 * @brief This API is used to configure the CT clocks
1256 * @param[in] pCLK : Pointer to the pll register instance
1257 * @param[in] clkSource : Enum values for CT clock sources to be selected. see possible CT clock
1258 sources at \ref CT_CLK_SRC_SEL_T
1259 * @param[in] divFactor : Division value for CT Clock
1260 * @param[in] clkType : Enum value to select static clock or dynamic clock. See \ref CLK_ENABLE_T for more info.
1261 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1262 */
RSI_CLK_CtClkConfig(M4CLK_Type * pCLK,CT_CLK_SRC_SEL_T clkSource,uint32_t divFactor,CLK_ENABLE_T clkType)1263 STATIC INLINE rsi_error_t RSI_CLK_CtClkConfig(M4CLK_Type *pCLK,
1264 CT_CLK_SRC_SEL_T clkSource,
1265 uint32_t divFactor,
1266 CLK_ENABLE_T clkType)
1267 {
1268 #if defined(CLOCK_ROMDRIVER_PRESENT)
1269 return ROMAPI_M4SS_CLK_API->clk_ct_clk_config(pCLK, clkSource, divFactor, clkType);
1270 #else
1271 return clk_ct_clk_config(pCLK, clkSource, divFactor, clkType);
1272 #endif
1273 }
1274
1275 #ifdef CHIP_9118
1276 /**
1277 * @fn STATIC INLINE rsi_error_t RSI_CLK_CciClkConfig(M4CLK_Type *pCLK ,CCI_CLK_SRC_SEL_T clkSource ,uint32_t divFactor,
1278 CLK_ENABLE_T clkType)
1279 * @brief This API is used to configure the CCI clocks
1280 * @param[in] pCLK : Pointer to the pll register instance
1281 * @param[in] clkSource : Enum values for CCI clock sources to be selected. see possible CCI clock sources at #CCI_CLK_SRC_SEL_T
1282 * @param[in] divFactor : Division value for CCI Clock
1283 * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info.
1284 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1285 */
RSI_CLK_CciClkConfig(M4CLK_Type * pCLK,CCI_CLK_SRC_SEL_T clkSource,uint32_t divFactor,CLK_ENABLE_T clkType)1286 STATIC INLINE rsi_error_t RSI_CLK_CciClkConfig(M4CLK_Type *pCLK,
1287 CCI_CLK_SRC_SEL_T clkSource,
1288 uint32_t divFactor,
1289 CLK_ENABLE_T clkType)
1290 {
1291 #if defined(CLOCK_ROMDRIVER_PRESENT)
1292 return ROMAPI_M4SS_CLK_API->clk_cci_clk_config(pCLK, clkSource, divFactor, clkType);
1293 #else
1294 return clk_cci_clk_config(pCLK, clkSource, divFactor, clkType);
1295 #endif
1296 }
1297 #endif
1298
1299 /**
1300 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sClkConfig(M4CLK_Type *pCLK ,I2S_CLK_SRC_SEL_T clkSource ,
1301 uint32_t divFactor)
1302 * @brief This API is used to configure the I2S clocks
1303 * @param[in] pCLK : Pointer to the pll register instance
1304 * @param[in] clkSource : Enum valuse for I2S clock sources to be selected. see possible I2S clock sources at #I2S_CLK_SRC_SEL_T
1305 * @param[in] divFactor : Division value for I2S Clock
1306 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1307 */
RSI_CLK_I2sClkConfig(M4CLK_Type * pCLK,I2S_CLK_SRC_SEL_T clkSource,uint32_t divFactor)1308 STATIC INLINE rsi_error_t RSI_CLK_I2sClkConfig(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor)
1309 {
1310 #if defined(CLOCK_ROMDRIVER_PRESENT)
1311 return ROMAPI_M4SS_CLK_API->clk_i2s_clk_config(pCLK, clkSource, divFactor);
1312 #else
1313 return clk_i2s_clk_config(pCLK, clkSource, divFactor);
1314 #endif
1315 }
1316
1317 /**
1318 * @fn STATIC INLINE rsi_error_t RSI_CLK_McuClkOutConfig(M4CLK_Type *pCLK ,MCU_CLKOUT_SRC_SEL_T clkSource ,
1319 uint32_t divFactor)
1320 * @brief This API is used to configure the McuClkOut clocks
1321 * @param[in] pCLK : Pointer to the pll register instance
1322 * @param[in] clkSource : Enum values of MCU_CLKOUT. See possible mcu_clk sources at #MCU_CLKOUT_SRC_SEL_T
1323 * @param[in] divFactor : Division value for McuClkOut Clock
1324 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1325 */
RSI_CLK_McuClkOutConfig(M4CLK_Type * pCLK,MCU_CLKOUT_SRC_SEL_T clkSource,uint32_t divFactor)1326 STATIC INLINE rsi_error_t RSI_CLK_McuClkOutConfig(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor)
1327 {
1328 #if defined(CLOCK_ROMDRIVER_PRESENT)
1329 return ROMAPI_M4SS_CLK_API->clk_mcu_clk_cut_config(pCLK, clkSource, divFactor);
1330 #else
1331 return clk_mcu_clk_cut_config(pCLK, clkSource, divFactor);
1332 #endif
1333 }
1334
1335 #ifdef CHIP_9118
1336 /**
1337 * @fn STATIC INLINE rsi_error_t RSI_CLK_CanClkConfig(M4CLK_Type *pCLK , uint32_t divFactor,CLK_ENABLE_T clkType)
1338 * @brief This API is used to configure the Can clocks
1339 * @param[in] pCLK : Pointer to the pll register instance
1340 * @param[in] divFactor : Division value for Can Clock
1341 * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info.
1342 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1343 */
RSI_CLK_CanClkConfig(M4CLK_Type * pCLK,uint32_t divFactor,CLK_ENABLE_T clkType)1344 STATIC INLINE rsi_error_t RSI_CLK_CanClkConfig(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType)
1345 {
1346 #if defined(CLOCK_ROMDRIVER_PRESENT)
1347 return ROMAPI_M4SS_CLK_API->clk_can_clk_config(pCLK, divFactor, clkType);
1348 #else
1349 return clk_can_clk_config(pCLK, divFactor, clkType);
1350 #endif
1351 }
1352
1353 /**
1354 * @fn STATIC INLINE rsi_error_t RSI_CLK_EthernetClkConfig(M4CLK_Type *pCLK ,boolean_t swalloEn ,ETHERNET_CLK_SRC_SEL_T clkSource,
1355 uint32_t divFactor)
1356 * @brief This API is used to configure the PLL_INTF clocks
1357 * @param[in] pCLK : Pointer to the pll register instance
1358 * @param[in] swalloEn : Enable or disable the swallo functionality
1359 * - 1 : Swallo enabled
1360 * - 0 : Swallo disabled
1361 * @param[in] clkSource : Enum values for PLL_Intf clock sources to be selected. see possible PLl clock sources at #ETHERNET_CLK_SRC_SEL_T
1362 * @param[in] divFactor : PLL_INTF clock division value
1363 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1364 */
RSI_CLK_EthernetClkConfig(M4CLK_Type * pCLK,boolean_t swalloEn,ETHERNET_CLK_SRC_SEL_T clkSource,uint32_t divFactor)1365 STATIC INLINE rsi_error_t RSI_CLK_EthernetClkConfig(M4CLK_Type *pCLK,
1366 boolean_t swalloEn,
1367 ETHERNET_CLK_SRC_SEL_T clkSource,
1368 uint32_t divFactor)
1369 {
1370 #if defined(CLOCK_ROMDRIVER_PRESENT)
1371 return ROMAPI_M4SS_CLK_API->clk_ethernet_clk_config(pCLK, swalloEn, clkSource, divFactor);
1372 #else
1373 return clk_ethernet_clk_config(pCLK, swalloEn, clkSource, divFactor);
1374 #endif
1375 }
1376 #endif
1377
1378 /**
1379 * @fn STATIC INLINE rsi_error_t RSI_CLK_M4SocClkDiv(M4CLK_Type *pCLK ,uint32_t divFactor)
1380 * @brief This API is used to divide the M4soc clock
1381 * @param[in] pCLK : Pointer to the pll register instance
1382 * @param[in] divFactor : M4Soc clock division value
1383 * @return returns 0 on success
1384 * \n Error code on failure
1385 */
RSI_CLK_M4SocClkDiv(M4CLK_Type * pCLK,uint32_t divFactor)1386 STATIC INLINE rsi_error_t RSI_CLK_M4SocClkDiv(M4CLK_Type *pCLK, uint32_t divFactor)
1387 {
1388 #if defined(CLOCK_ROMDRIVER_PRESENT)
1389 return ROMAPI_M4SS_CLK_API->clk_m4_soc_clk_div(pCLK, divFactor);
1390 #else
1391 return clk_m4_soc_clk_div(pCLK, divFactor);
1392 #endif
1393 }
1394
1395 /**
1396 * @fn RSI_CLK_QspiClkDiv(M4CLK_Type *pCLK , boolean_t u8SwallowEn ,
1397 boolean_t u8OddDivEn , uint32_t divFactor )
1398 * @brief This API is used to divide the QSPI clock
1399 * @param[in] pCLK : Pointer to the pll register instance
1400 * @param[in] u8SwallowEn : To enable or disable the swallo functionality
1401 * - 1 : Swallo enabled
1402 * - 0 : Swallo disabled
1403 * @param[in] u8OddDivEn : To enable or disable the odd division functionality
1404 * - 1 : Odd division enabled
1405 * - 0 : Odd division disabled
1406 * @param[in] divFactor : QSPI clock division value
1407 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1408 */
RSI_CLK_QspiClkDiv(M4CLK_Type * pCLK,boolean_t u8SwallowEn,boolean_t u8OddDivEn,uint32_t divFactor)1409 STATIC INLINE rsi_error_t RSI_CLK_QspiClkDiv(M4CLK_Type *pCLK,
1410 boolean_t u8SwallowEn,
1411 boolean_t u8OddDivEn,
1412 uint32_t divFactor)
1413 {
1414 #if defined(CLOCK_ROMDRIVER_PRESENT)
1415 return ROMAPI_M4SS_CLK_API->clk_qspi_clk_div(pCLK, u8SwallowEn, u8OddDivEn, divFactor);
1416 #else
1417 return clk_qspi_clk_div(pCLK, u8SwallowEn, u8OddDivEn, divFactor);
1418 #endif
1419 }
1420
1421 /**
1422 * @fn STATIC INLINE rsi_error_t RSI_CLK_CtClkDiv(M4CLK_Type *pCLK , uint32_t divFactor)
1423 * @brief This API is used to divide the CT clock
1424 * @param[in] pCLK : Pointer to the pll register instance
1425 * @param[in] divFactor : CT clock division value
1426 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1427 */
RSI_CLK_CtClkDiv(M4CLK_Type * pCLK,uint32_t divFactor)1428 STATIC INLINE rsi_error_t RSI_CLK_CtClkDiv(M4CLK_Type *pCLK, uint32_t divFactor)
1429 {
1430 #if defined(CLOCK_ROMDRIVER_PRESENT)
1431 return ROMAPI_M4SS_CLK_API->clk_ct_clk_div(pCLK, divFactor);
1432 #else
1433 return clk_ct_clk_div(pCLK, divFactor);
1434 #endif
1435 }
1436
1437 /**
1438 * @fn STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkDiv(M4CLK_Type *pCLK , uint32_t divFactor )
1439 * @brief This API is used to divide the SSI clock
1440 * @param[in] pCLK : Pointer to the pll register instance
1441 * @param[in] divFactor : SSI clock division value
1442 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1443 */
RSI_CLK_SsiMstClkDiv(M4CLK_Type * pCLK,uint32_t divFactor)1444 STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkDiv(M4CLK_Type *pCLK, uint32_t divFactor)
1445 {
1446 #if defined(CLOCK_ROMDRIVER_PRESENT)
1447 return ROMAPI_M4SS_CLK_API->clk_ssi_mst_clk_div(pCLK, divFactor);
1448 #else
1449 return clk_ssi_mst_clk_div(pCLK, divFactor);
1450 #endif
1451 }
1452
1453 #ifdef CHIP_9118
1454 /**
1455 * @fn STATIC INLINE rsi_error_t RSI_CLK_CciClkDiv(M4CLK_Type *pCLK , uint32_t divFactor )
1456 * @brief This API is used to divide the CCI clock
1457 * @param[in] pCLK : Pointer to the pll register instance
1458 * @param[in] divFactor : CCI clock division value
1459 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1460 */
RSI_CLK_CciClkDiv(M4CLK_Type * pCLK,uint32_t divFactor)1461 STATIC INLINE rsi_error_t RSI_CLK_CciClkDiv(M4CLK_Type *pCLK, uint32_t divFactor)
1462 {
1463 #if defined(CLOCK_ROMDRIVER_PRESENT)
1464 return ROMAPI_M4SS_CLK_API->clk_cci_clk_div(pCLK, divFactor);
1465 #else
1466 return clk_cci_clk_div(pCLK, divFactor);
1467 #endif
1468 }
1469 #endif
1470
1471 /**
1472 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sClkDiv(M4CLK_Type *pCLK , uint32_t divFactor )
1473 * @brief This API is used to divide the I2S clock
1474 * @param[in] pCLK : Pointer to the pll register instance
1475 * @param[in] divFactor : I2S clock division value
1476 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1477 */
RSI_CLK_I2sClkDiv(M4CLK_Type * pCLK,uint32_t divFactor)1478 STATIC INLINE rsi_error_t RSI_CLK_I2sClkDiv(M4CLK_Type *pCLK, uint32_t divFactor)
1479 {
1480 #if defined(CLOCK_ROMDRIVER_PRESENT)
1481 return ROMAPI_M4SS_CLK_API->clk_i2s_clk_div(pCLK, divFactor);
1482 #else
1483 return clk_i2s_clk_div(pCLK, divFactor);
1484 #endif
1485 }
1486
1487 #ifdef CHIP_9118
1488 /**
1489 * @fn STATIC INLINE rsi_error_t RSI_CLK_SdmemClkDiv(M4CLK_Type *pCLK , boolean_t u8SwallowEn , uint32_t divFactor)
1490 * @brief This API is used to divide the SDMEM clock
1491 * @param[in] pCLK : Pointer to the pll register instance
1492 * @param[in] u8SwallowEn : To enable or disable the swallo functionality
1493 * - 1 : Swallo enabled
1494 * - 0 : Swallo disabled
1495 * @param[in] divFactor : SDMEM clock division value
1496 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1497 */
RSI_CLK_SdmemClkDiv(M4CLK_Type * pCLK,boolean_t u8SwallowEn,uint32_t divFactor)1498 STATIC INLINE rsi_error_t RSI_CLK_SdmemClkDiv(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor)
1499 {
1500 #if defined(CLOCK_ROMDRIVER_PRESENT)
1501 return ROMAPI_M4SS_CLK_API->clk_sd_mem_clk_div(pCLK, u8SwallowEn, divFactor);
1502 #else
1503 return clk_sd_mem_clk_div(pCLK, u8SwallowEn, divFactor);
1504 #endif
1505 }
1506 #endif
1507
1508 /**
1509 * @fn STATIC INLINE rsi_error_t RSI_CLK_UsartClkDiv(M4CLK_Type *pCLK , EN_USART_T EN_USART_T ,
1510 uint8_t u8FracDivEn, uint32_t divFactor)
1511 * @brief This API is used to divide the USART/UART clock
1512 * @param[in] pCLK : Pointer to the pll register instance
1513 * @param[in] EN_USART_T : Enum of uart numbers. See #EN_USART_T for more info
1514 * @param[in] u8FracDivEn : To enable or disable fractional division feature
1515 * - 1 : Clock Swallo type divider is selected
1516 * - 0 : Fractional Divider typed is selected
1517 * @param[in] divFactor : USART/UART clock division value
1518 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1519 */
RSI_CLK_UsartClkDiv(M4CLK_Type * pCLK,EN_USART_T EN_USART,uint8_t u8FracDivEn,uint32_t divFactor)1520 STATIC INLINE rsi_error_t RSI_CLK_UsartClkDiv(M4CLK_Type *pCLK,
1521 EN_USART_T EN_USART,
1522 uint8_t u8FracDivEn,
1523 uint32_t divFactor)
1524 {
1525 #if defined(CLOCK_ROMDRIVER_PRESENT)
1526 return ROMAPI_M4SS_CLK_API->clk_usart_clk_div(pCLK, EN_USART, u8FracDivEn, divFactor);
1527 #else
1528 return clk_usart_clk_div(pCLK, EN_USART, u8FracDivEn, divFactor);
1529 #endif
1530 }
1531
1532 /**
1533 * @fn uint32_t RSI_CLK_SlpClkCalibConfig(M4CLK_Type *pCLK , uint8_t clkCycles)
1534 * @brief This API is used to calibrate the sleep clock
1535 * @param[in] pCLK : Pointer to the pll register instance
1536 * @param[in] clkCycles : These bits are used to program the number of clock cycles over which
1537 clock calibration is to be done.
1538 * - 00 => 1 Cycle
1539 * - 01 => 2 Cycles
1540 * - 10 => 3 Cycles
1541 * - 11 => 4 Cycles
1542 * @return Returns the calibration duration.
1543 */
RSI_CLK_SlpClkCalibConfig(M4CLK_Type * pCLK,uint8_t clkCycles)1544 STATIC INLINE uint32_t RSI_CLK_SlpClkCalibConfig(M4CLK_Type *pCLK, uint8_t clkCycles)
1545 {
1546 #if defined(CLOCK_ROMDRIVER_PRESENT)
1547 return ROMAPI_M4SS_CLK_API->clk_slp_clk_calib_config(pCLK, clkCycles);
1548 #else
1549 return clk_slp_clk_calib_config(pCLK, clkCycles);
1550 #endif
1551 }
1552
1553 /**
1554 * @fn STATIC INLINE rsi_error_t RSI_CLK_GspiClkConfig(M4CLK_Type *pCLK ,GSPI_CLK_SRC_SEL_T clkSel )
1555 * @brief This API is used to configure the GSPI Clocks
1556 * @param[in] pCLK : Pointer to the pll register instance
1557 * @param[in] clkSel : Enum values to select the clock sources. See possible values at \ref GSPI_CLK_SRC_SEL_T
1558 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1559 */
RSI_CLK_GspiClkConfig(M4CLK_Type * pCLK,GSPI_CLK_SRC_SEL_T clkSel)1560 STATIC INLINE rsi_error_t RSI_CLK_GspiClkConfig(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel)
1561 {
1562 #if defined(CLOCK_ROMDRIVER_PRESENT)
1563 return ROMAPI_M4SS_CLK_API->clk_gspi_clk_config(pCLK, clkSel);
1564 #else
1565 return clk_gspi_clk_config(pCLK, clkSel);
1566 #endif
1567 }
1568
1569 /**
1570 * @fn STATIC INLINE rsi_error_t RSI_CLK_SlpClkConfig(M4CLK_Type *pCLK , SLEEP_CLK_SRC_SEL_T clkSrc)
1571 * @brief This API is used to configure the SLEEP Clocks
1572 * @param[in] pCLK : Pointer to the pll register instance
1573 * @param[in] clkSrc : Enum values to select the clock sources for sleep clock. See \ref SLEEP_CLK_SRC_SEL_T for more info
1574 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1575 */
RSI_CLK_SlpClkConfig(M4CLK_Type * pCLK,SLEEP_CLK_SRC_SEL_T clkSrc)1576 STATIC INLINE rsi_error_t RSI_CLK_SlpClkConfig(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc)
1577 {
1578 #if defined(CLOCK_ROMDRIVER_PRESENT)
1579 return ROMAPI_M4SS_CLK_API->clk_slp_clk_config(pCLK, clkSrc);
1580 #else
1581 return clk_slp_clk_config(pCLK, clkSrc);
1582 #endif
1583 }
1584
1585 /**
1586 * @fn STATIC INLINE rsi_error_t RSI_CLK_I2CClkConfig(M4CLK_Type *pCLK , boolean_t clkEnable,EN_I2C_T enI2C)
1587 * @brief This API is used to configure the I2C clock
1588 * @param[in] pCLK : Pointer to the pll register instance
1589 * @param[in] clkEnable : Boolean value to enable or disable clock mode
1590 * - 1 clkEnable : Enables the I2C clock
1591 * - 0 Disable : Disables the I2C clock
1592 * @param[in] enI2C : Enum values. See \ref EN_I2C_T for more infomation
1593 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1594 */
RSI_CLK_I2CClkConfig(M4CLK_Type * pCLK,boolean_t clkEnable,EN_I2C_T enI2C)1595 STATIC INLINE rsi_error_t RSI_CLK_I2CClkConfig(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C)
1596 {
1597 #if defined(CLOCK_ROMDRIVER_PRESENT)
1598 return ROMAPI_M4SS_CLK_API->clk_i2c_clk_config(pCLK, clkEnable, enI2C);
1599 #else
1600 return clk_i2c_clk_config(pCLK, clkEnable, enI2C);
1601 #endif
1602 }
1603
1604 /**
1605 * @fn STATIC INLINE rsi_error_t RSI_CLK_XtalClkConfig(uint8_t xtalPin)
1606 * @brief This API is used to configure the Xtal clock
1607 * @param[in] xtalPin : Pin number of NPSS_GPIO. Possible values are 0,1,2,3,4
1608 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1609 */
RSI_CLK_XtalClkConfig(uint8_t xtalPin)1610 STATIC INLINE rsi_error_t RSI_CLK_XtalClkConfig(uint8_t xtalPin)
1611 {
1612 #if defined(CLOCK_ROMDRIVER_PRESENT)
1613 return ROMAPI_M4SS_CLK_API->clk_xtal_clk_config(xtalPin);
1614 #else
1615 return clk_xtal_clk_config(xtalPin);
1616 #endif
1617 }
1618
1619 #ifdef CHIP_9118
1620 /**
1621 * @fn STATIC INLINE rsi_error_t RSI_CLK_USBClkConfig(M4CLK_Type *pCLK ,USB_CLK_SRC_SEL_T clkSource ,uint16_t divFactor)
1622 * @brief This API is used to configure the USB clock
1623 * @param[in] pCLK : Pointer to the pll register instance
1624 * @param[in] clkSource : Different clock sources for USB_PHY_CLK. See #USB_CLK_SRC_SEL_T for more info
1625 * @param[in] divFactor : USB clock division value
1626 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1627 */
RSI_CLK_USBClkConfig(M4CLK_Type * pCLK,USB_CLK_SRC_SEL_T clkSource,uint16_t divFactor)1628 STATIC INLINE rsi_error_t RSI_CLK_USBClkConfig(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor)
1629 {
1630 #if defined(CLOCK_ROMDRIVER_PRESENT)
1631 return ROMAPI_M4SS_CLK_API->clk_usb_clk_config(pCLK, clkSource, divFactor);
1632 #else
1633 return clk_usb_clk_config(pCLK, clkSource, divFactor);
1634 #endif
1635 }
1636 #endif
1637
1638 /**
1639 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable(M4CLK_Type *pCLK ,PERIPHERALS_CLK_T module,CLK_ENABLE_T clkType)
1640 * @brief This API is used to enable the particular clock
1641 * @param[in] pCLK : Pointer to the pll register instance
1642 * @param[in] module : To select particular pheripheral.
1643 * @param[in] clkType : To select the clock as dynamic or static clock.
1644 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1645 */
RSI_CLK_PeripheralClkEnable(M4CLK_Type * pCLK,PERIPHERALS_CLK_T module,CLK_ENABLE_T clkType)1646 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType)
1647 {
1648 #if defined(CLOCK_ROMDRIVER_PRESENT)
1649 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable(pCLK, module, clkType);
1650 #else
1651 return clk_peripheral_clk_enable(pCLK, module, clkType);
1652 #endif
1653 }
1654
1655 /**
1656 * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable(M4CLK_Type *pCLK ,PERIPHERALS_CLK_T module)
1657 * @brief This API is used to disable the particular clock
1658 * @param[in] pCLK : Pointer to the pll register instance
1659 * @param[in] module : To select particular peripheral.
1660 * @return returns zero \ref RSI_OK on success ,on failure return error code.
1661 */
RSI_CLK_PeripheralClkDisable(M4CLK_Type * pCLK,PERIPHERALS_CLK_T module)1662 STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module)
1663 {
1664 #if defined(CLOCK_ROMDRIVER_PRESENT)
1665 return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable(pCLK, module);
1666 #else
1667 return clk_peripheral_clk_disable(pCLK, module);
1668 #endif
1669 }
1670
1671 /**
1672 *@fn void RSI_CLK_SocPllLockConfig(boolean_t manual_lock , boolean_t bypass_manual_lock , uint8_t mm_count_limit)
1673 *@brief This API is used to configure the SOC-PLL lock settings
1674 *@param[in] manual_lock : Enable for manual mode phase lock generation
1675 *@param[in] bypass_manual_lock : Bypass signal for phase detector logic
1676 *@param[in] mm_count_limit : Lock count limit in manual mode phase lock generation
1677 */
RSI_CLK_SocPllLockConfig(boolean_t manual_lock,boolean_t bypass_manual_lock,uint8_t mm_count_limit)1678 STATIC INLINE void RSI_CLK_SocPllLockConfig(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit)
1679 {
1680 #if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT)
1681 ROMAPI_M4SS_CLK_API->clk_config_pll_lock(manual_lock, bypass_manual_lock, mm_count_limit);
1682 #else
1683 clk_config_pll_lock(manual_lock, bypass_manual_lock, mm_count_limit);
1684 #endif
1685 }
1686
1687 /**
1688 *@fn STATIC INLINE void RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src)
1689 *@brief This API is used to configure SOC-PLL config
1690 *@param[in] ref_clk_src : Reference clock to be programmed.
1691 */
RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src)1692 STATIC INLINE void RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src)
1693 {
1694 #if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT)
1695 ROMAPI_M4SS_CLK_API->clk_config_pll_ref_clk(ref_clk_src);
1696 #else
1697 clk_config_pll_ref_clk(ref_clk_src);
1698 #endif
1699 }
1700
1701 #ifdef __cplusplus
1702 }
1703 #endif
1704
1705 #endif //__RSI_ROM_CLK_H_
1706
1707 /*@} end of RSI_M4SS_CLOCK_DRIVERS */
1708
1709 /* @} end of RSI_CHIP_CLOCK_DRIVERS */
1710
