1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.56 24 // Version: 1 25 26 #ifndef __SI32_DMADESC_A_REGISTERS_H__ 27 #define __SI32_DMADESC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_DMADESC_A_SRCEND_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Source End Pointer 42 volatile uint32_t SRCEND_BITS; 43 }; 44 volatile uint32_t U32; 45 }; 46 }; 47 48 #define SI32_DMADESC_A_SRCEND_SRCEND_MASK 0xFFFFFFFF 49 #define SI32_DMADESC_A_SRCEND_SRCEND_SHIFT 0 50 51 52 53 struct SI32_DMADESC_A_DSTEND_Struct 54 { 55 union 56 { 57 struct 58 { 59 // Destination End Pointer 60 volatile uint32_t DSTEND_BITS; 61 }; 62 volatile uint32_t U32; 63 }; 64 }; 65 66 #define SI32_DMADESC_A_DSTEND_DSTEND_MASK 0xFFFFFFFF 67 #define SI32_DMADESC_A_DSTEND_DSTEND_SHIFT 0 68 69 70 71 struct SI32_DMADESC_A_CONFIG_Struct 72 { 73 union 74 { 75 struct 76 { 77 // Transfer Mode 78 volatile uint32_t TMD: 3; 79 uint32_t reserved0: 1; 80 // Transfer Total 81 volatile uint32_t NCOUNT: 10; 82 // Transfer Size Select 83 volatile uint32_t RPOWER: 4; 84 uint32_t reserved1: 6; 85 // Source Data Size Select 86 volatile uint32_t SRCSIZE: 2; 87 // Source Address Increment Mode 88 volatile uint32_t SRCAIMD: 2; 89 // Destination Data Size Select 90 volatile uint32_t DSTSIZE: 2; 91 // Destination Address Increment Mode 92 volatile uint32_t DSTAIMD: 2; 93 }; 94 volatile uint32_t U32; 95 }; 96 }; 97 98 #define SI32_DMADESC_A_CONFIG_TMD_MASK 0x00000007 99 #define SI32_DMADESC_A_CONFIG_TMD_SHIFT 0 100 // Stop the DMA channel. 101 #define SI32_DMADESC_A_CONFIG_TMD_STOP_VALUE 0 102 #define SI32_DMADESC_A_CONFIG_TMD_STOP_U32 \ 103 (SI32_DMADESC_A_CONFIG_TMD_STOP_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 104 // Use the Basic transfer type (single structure only). 105 #define SI32_DMADESC_A_CONFIG_TMD_BASIC_VALUE 1 106 #define SI32_DMADESC_A_CONFIG_TMD_BASIC_U32 \ 107 (SI32_DMADESC_A_CONFIG_TMD_BASIC_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 108 // Use the Auto-Request transfer type (single structure only). 109 #define SI32_DMADESC_A_CONFIG_TMD_AUTO_REQUEST_VALUE 2 110 #define SI32_DMADESC_A_CONFIG_TMD_AUTO_REQUEST_U32 \ 111 (SI32_DMADESC_A_CONFIG_TMD_AUTO_REQUEST_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 112 // Use the Ping-Pong transfer type (primary and alternate structures). 113 #define SI32_DMADESC_A_CONFIG_TMD_PING_PONG_VALUE 3 114 #define SI32_DMADESC_A_CONFIG_TMD_PING_PONG_U32 \ 115 (SI32_DMADESC_A_CONFIG_TMD_PING_PONG_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 116 // Use the Memory Scatter-Gather Primary transfer type (primary, alternate, and 117 // scattered structures). 118 #define SI32_DMADESC_A_CONFIG_TMD_MEMORY_SCATTER_GATHER_P_VALUE 4 119 #define SI32_DMADESC_A_CONFIG_TMD_MEMORY_SCATTER_GATHER_P_U32 \ 120 (SI32_DMADESC_A_CONFIG_TMD_MEMORY_SCATTER_GATHER_P_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 121 // Use the Memory Scatter-Gather Alternate transfer type (primary, alternate, and 122 // scattered structures). 123 #define SI32_DMADESC_A_CONFIG_TMD_MEMORY_SCATTER_GATHER_A_VALUE 5 124 #define SI32_DMADESC_A_CONFIG_TMD_MEMORY_SCATTER_GATHER_A_U32 \ 125 (SI32_DMADESC_A_CONFIG_TMD_MEMORY_SCATTER_GATHER_A_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 126 // Use the Peripheral Scatter-Gather Primary transfer type (primary, alternate, and 127 // scattered structures). 128 #define SI32_DMADESC_A_CONFIG_TMD_PERIPHERAL_SCATTER_GATHER_P_VALUE 6 129 #define SI32_DMADESC_A_CONFIG_TMD_PERIPHERAL_SCATTER_GATHER_P_U32 \ 130 (SI32_DMADESC_A_CONFIG_TMD_PERIPHERAL_SCATTER_GATHER_P_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 131 // Use the Peripheral Scatter-Gather Alternate transfer type (primary, alternate, 132 // and scattered structures). 133 #define SI32_DMADESC_A_CONFIG_TMD_PERIPHERAL_SCATTER_GATHER_A_VALUE 7 134 #define SI32_DMADESC_A_CONFIG_TMD_PERIPHERAL_SCATTER_GATHER_A_U32 \ 135 (SI32_DMADESC_A_CONFIG_TMD_PERIPHERAL_SCATTER_GATHER_A_VALUE << SI32_DMADESC_A_CONFIG_TMD_SHIFT) 136 137 #define SI32_DMADESC_A_CONFIG_NCOUNT_MASK 0x00003FF0 138 #define SI32_DMADESC_A_CONFIG_NCOUNT_SHIFT 4 139 140 #define SI32_DMADESC_A_CONFIG_RPOWER_MASK 0x0003C000 141 #define SI32_DMADESC_A_CONFIG_RPOWER_SHIFT 14 142 143 #define SI32_DMADESC_A_CONFIG_SRCSIZE_MASK 0x03000000 144 #define SI32_DMADESC_A_CONFIG_SRCSIZE_SHIFT 24 145 // Each DMA source data transfer reads a byte. 146 #define SI32_DMADESC_A_CONFIG_SRCSIZE_BYTE_VALUE 0 147 #define SI32_DMADESC_A_CONFIG_SRCSIZE_BYTE_U32 \ 148 (SI32_DMADESC_A_CONFIG_SRCSIZE_BYTE_VALUE << SI32_DMADESC_A_CONFIG_SRCSIZE_SHIFT) 149 // Each DMA source data transfer reads a half-word. 150 #define SI32_DMADESC_A_CONFIG_SRCSIZE_HALF_WORD_VALUE 1 151 #define SI32_DMADESC_A_CONFIG_SRCSIZE_HALF_WORD_U32 \ 152 (SI32_DMADESC_A_CONFIG_SRCSIZE_HALF_WORD_VALUE << SI32_DMADESC_A_CONFIG_SRCSIZE_SHIFT) 153 // Each DMA source data transfer reads a word. 154 #define SI32_DMADESC_A_CONFIG_SRCSIZE_WORD_VALUE 2 155 #define SI32_DMADESC_A_CONFIG_SRCSIZE_WORD_U32 \ 156 (SI32_DMADESC_A_CONFIG_SRCSIZE_WORD_VALUE << SI32_DMADESC_A_CONFIG_SRCSIZE_SHIFT) 157 158 #define SI32_DMADESC_A_CONFIG_SRCAIMD_MASK 0x0C000000 159 #define SI32_DMADESC_A_CONFIG_SRCAIMD_SHIFT 26 160 // The source address increments by one byte after each data transfer. 161 #define SI32_DMADESC_A_CONFIG_SRCAIMD_BYTE_VALUE 0 162 #define SI32_DMADESC_A_CONFIG_SRCAIMD_BYTE_U32 \ 163 (SI32_DMADESC_A_CONFIG_SRCAIMD_BYTE_VALUE << SI32_DMADESC_A_CONFIG_SRCAIMD_SHIFT) 164 // The source address increments by one half-word after each data transfer. 165 #define SI32_DMADESC_A_CONFIG_SRCAIMD_HALF_WORD_VALUE 1 166 #define SI32_DMADESC_A_CONFIG_SRCAIMD_HALF_WORD_U32 \ 167 (SI32_DMADESC_A_CONFIG_SRCAIMD_HALF_WORD_VALUE << SI32_DMADESC_A_CONFIG_SRCAIMD_SHIFT) 168 // The source address increments by one word after each data transfer. 169 #define SI32_DMADESC_A_CONFIG_SRCAIMD_WORD_VALUE 2 170 #define SI32_DMADESC_A_CONFIG_SRCAIMD_WORD_U32 \ 171 (SI32_DMADESC_A_CONFIG_SRCAIMD_WORD_VALUE << SI32_DMADESC_A_CONFIG_SRCAIMD_SHIFT) 172 // The source address does not increment. 173 #define SI32_DMADESC_A_CONFIG_SRCAIMD_NO_INCREMENT_VALUE 3 174 #define SI32_DMADESC_A_CONFIG_SRCAIMD_NO_INCREMENT_U32 \ 175 (SI32_DMADESC_A_CONFIG_SRCAIMD_NO_INCREMENT_VALUE << SI32_DMADESC_A_CONFIG_SRCAIMD_SHIFT) 176 177 #define SI32_DMADESC_A_CONFIG_DSTSIZE_MASK 0x30000000 178 #define SI32_DMADESC_A_CONFIG_DSTSIZE_SHIFT 28 179 // Each DMA destination data transfer writes a byte. 180 #define SI32_DMADESC_A_CONFIG_DSTSIZE_BYTE_VALUE 0 181 #define SI32_DMADESC_A_CONFIG_DSTSIZE_BYTE_U32 \ 182 (SI32_DMADESC_A_CONFIG_DSTSIZE_BYTE_VALUE << SI32_DMADESC_A_CONFIG_DSTSIZE_SHIFT) 183 // Each DMA destination data transfer writes a half-word. 184 #define SI32_DMADESC_A_CONFIG_DSTSIZE_HALF_WORD_VALUE 1 185 #define SI32_DMADESC_A_CONFIG_DSTSIZE_HALF_WORD_U32 \ 186 (SI32_DMADESC_A_CONFIG_DSTSIZE_HALF_WORD_VALUE << SI32_DMADESC_A_CONFIG_DSTSIZE_SHIFT) 187 // Each DMA destination data transfer writes a word. 188 #define SI32_DMADESC_A_CONFIG_DSTSIZE_WORD_VALUE 2 189 #define SI32_DMADESC_A_CONFIG_DSTSIZE_WORD_U32 \ 190 (SI32_DMADESC_A_CONFIG_DSTSIZE_WORD_VALUE << SI32_DMADESC_A_CONFIG_DSTSIZE_SHIFT) 191 192 #define SI32_DMADESC_A_CONFIG_DSTAIMD_MASK 0xC0000000 193 #define SI32_DMADESC_A_CONFIG_DSTAIMD_SHIFT 30 194 // The destination address increments by one byte after each data transfer. 195 #define SI32_DMADESC_A_CONFIG_DSTAIMD_BYTE_VALUE 0U 196 #define SI32_DMADESC_A_CONFIG_DSTAIMD_BYTE_U32 \ 197 (SI32_DMADESC_A_CONFIG_DSTAIMD_BYTE_VALUE << SI32_DMADESC_A_CONFIG_DSTAIMD_SHIFT) 198 // The destination address increments by one half-word after each data transfer. 199 #define SI32_DMADESC_A_CONFIG_DSTAIMD_HALF_WORD_VALUE 1U 200 #define SI32_DMADESC_A_CONFIG_DSTAIMD_HALF_WORD_U32 \ 201 (SI32_DMADESC_A_CONFIG_DSTAIMD_HALF_WORD_VALUE << SI32_DMADESC_A_CONFIG_DSTAIMD_SHIFT) 202 // The destination address increments by one word after each data transfer. 203 #define SI32_DMADESC_A_CONFIG_DSTAIMD_WORD_VALUE 2U 204 #define SI32_DMADESC_A_CONFIG_DSTAIMD_WORD_U32 \ 205 (SI32_DMADESC_A_CONFIG_DSTAIMD_WORD_VALUE << SI32_DMADESC_A_CONFIG_DSTAIMD_SHIFT) 206 // The destination address does not increment. 207 #define SI32_DMADESC_A_CONFIG_DSTAIMD_NO_INCREMENT_VALUE 3U 208 #define SI32_DMADESC_A_CONFIG_DSTAIMD_NO_INCREMENT_U32 \ 209 (SI32_DMADESC_A_CONFIG_DSTAIMD_NO_INCREMENT_VALUE << SI32_DMADESC_A_CONFIG_DSTAIMD_SHIFT) 210 211 212 213 typedef struct SI32_DMADESC_A_Struct 214 { 215 struct SI32_DMADESC_A_SRCEND_Struct SRCEND ; // Base Address + 0x0 216 struct SI32_DMADESC_A_DSTEND_Struct DSTEND ; // Base Address + 0x4 217 struct SI32_DMADESC_A_CONFIG_Struct CONFIG ; // Base Address + 0x8 218 uint32_t reserved0; 219 } SI32_DMADESC_A_Type; 220 221 #ifdef __cplusplus 222 } 223 #endif 224 225 #endif // __SI32_DMADESC_A_REGISTERS_H__ 226 227 //-eof-------------------------------------------------------------------------- 228 229
