Searched refs:RESETEN_SET (Results 1 – 9 of 9) sorted by relevance
114 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_VMONREN_MASK)140 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_MCDREN_MASK)166 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_WDTREN_MASK)192 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_SWREN_MASK)205 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK)231 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK)257 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CPFREN_MASK)283 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK)309 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CPMREN_MASK)335 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_UART0MREN_MASK)[all …]
87 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_VMONREN_MASK; in _SI32_RSTSRC_A_enable_vdd_monitor_reset_source()113 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_MCDREN_MASK; in _SI32_RSTSRC_A_enable_missing_clock_detector_reset_source()139 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_WDTREN_MASK; in _SI32_RSTSRC_A_enable_watchdog_timer_reset_source()165 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_SWREN_MASK; in _SI32_RSTSRC_A_generate_software_reset()178 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK; in _SI32_RSTSRC_A_enable_comparator0_reset_source()204 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK; in _SI32_RSTSRC_A_enable_comparator1_reset_source()230 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CPFREN_MASK; in _SI32_RSTSRC_A_enable_low_power_mode_charge_pump_reset_source()256 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK; in _SI32_RSTSRC_A_enable_rtc0_reset_source()282 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CPMREN_MASK; in _SI32_RSTSRC_A_enable_system_reset_to_low_power_charge_pump()308 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_UART0MREN_MASK; in _SI32_RSTSRC_A_enable_system_reset_to_uart()[all …]
396 volatile uint32_t RESETEN_SET; member
114 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_VMONREN_MASK)140 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_MCDREN_MASK)166 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_WDTREN_MASK)192 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK)218 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK)244 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_USB0REN_MASK)270 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK)296 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_SWREN_ENABLED_U32)
87 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_VMONREN_MASK; in _SI32_RSTSRC_A_enable_vdd_monitor_reset_source()113 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_MCDREN_MASK; in _SI32_RSTSRC_A_enable_missing_clock_detector_reset_source()139 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_WDTREN_MASK; in _SI32_RSTSRC_A_enable_watchdog_timer_reset_source()165 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK; in _SI32_RSTSRC_A_enable_comparator0_reset_source()191 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK; in _SI32_RSTSRC_A_enable_comparator1_reset_source()217 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_USB0REN_MASK; in _SI32_RSTSRC_A_enable_usb0_reset_source()243 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK; in _SI32_RSTSRC_A_enable_rtc0_reset_source()269 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_SWREN_ENABLED_U32; in _SI32_RSTSRC_A_generate_software_reset()
366 volatile uint32_t RESETEN_SET; member
114 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_VMONREN_MASK)140 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_MCDREN_MASK)166 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_WDTREN_MASK)192 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK)218 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK)244 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK)270 (basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_SWREN_ENABLED_U32)
87 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_VMONREN_MASK; in _SI32_RSTSRC_A_enable_vdd_monitor_reset_source()113 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_MCDREN_MASK; in _SI32_RSTSRC_A_enable_missing_clock_detector_reset_source()139 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_WDTREN_MASK; in _SI32_RSTSRC_A_enable_watchdog_timer_reset_source()165 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK; in _SI32_RSTSRC_A_enable_comparator0_reset_source()191 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK; in _SI32_RSTSRC_A_enable_comparator1_reset_source()217 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK; in _SI32_RSTSRC_A_enable_rtc0_reset_source()243 basePointer->RESETEN_SET = SI32_RSTSRC_A_RESETEN_SWREN_ENABLED_U32; in _SI32_RSTSRC_A_generate_software_reset()
342 volatile uint32_t RESETEN_SET; member
