Searched refs:RESETEN_CLR (Results 1 – 9 of 9) sorted by relevance
127 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_VMONREN_MASK)153 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_MCDREN_MASK)179 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_WDTREN_MASK)218 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK)244 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK)270 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CPFREN_MASK)296 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK)322 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CPMREN_MASK)348 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_UART0MREN_MASK)374 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_LCD0MREN_MASK)[all …]
100 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_VMONREN_MASK; in _SI32_RSTSRC_A_disable_vdd_monitor_reset_source()126 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_MCDREN_MASK; in _SI32_RSTSRC_A_disable_missing_clock_detector_reset_source()152 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_WDTREN_MASK; in _SI32_RSTSRC_A_disable_watchdog_timer_reset_source()191 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK; in _SI32_RSTSRC_A_disable_comparator0_reset_source()217 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK; in _SI32_RSTSRC_A_disable_comparator1_reset_source()243 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CPFREN_MASK; in _SI32_RSTSRC_A_disable_low_power_mode_charge_pump_reset_source()269 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK; in _SI32_RSTSRC_A_disable_rtc0_reset_source()295 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CPMREN_MASK; in _SI32_RSTSRC_A_disable_system_reset_to_low_power_charge_pump()321 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_UART0MREN_MASK; in _SI32_RSTSRC_A_disable_system_reset_to_uart()347 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_LCD0MREN_MASK; in _SI32_RSTSRC_A_disable_system_reset_to_lcd()[all …]
397 volatile uint32_t RESETEN_CLR; member
127 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_VMONREN_MASK)153 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_MCDREN_MASK)179 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_WDTREN_MASK)205 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK)231 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK)257 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_USB0REN_MASK)283 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK)
100 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_VMONREN_MASK; in _SI32_RSTSRC_A_disable_vdd_monitor_reset_source()126 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_MCDREN_MASK; in _SI32_RSTSRC_A_disable_missing_clock_detector_reset_source()152 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_WDTREN_MASK; in _SI32_RSTSRC_A_disable_watchdog_timer_reset_source()178 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK; in _SI32_RSTSRC_A_disable_comparator0_reset_source()204 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK; in _SI32_RSTSRC_A_disable_comparator1_reset_source()230 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_USB0REN_MASK; in _SI32_RSTSRC_A_disable_usb0_reset_source()256 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK; in _SI32_RSTSRC_A_disable_rtc0_reset_source()
367 volatile uint32_t RESETEN_CLR; member
127 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_VMONREN_MASK)153 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_MCDREN_MASK)179 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_WDTREN_MASK)205 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK)231 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK)257 (basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK)
100 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_VMONREN_MASK; in _SI32_RSTSRC_A_disable_vdd_monitor_reset_source()126 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_MCDREN_MASK; in _SI32_RSTSRC_A_disable_missing_clock_detector_reset_source()152 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_WDTREN_MASK; in _SI32_RSTSRC_A_disable_watchdog_timer_reset_source()178 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP0REN_MASK; in _SI32_RSTSRC_A_disable_comparator0_reset_source()204 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_CMP1REN_MASK; in _SI32_RSTSRC_A_disable_comparator1_reset_source()230 basePointer->RESETEN_CLR = SI32_RSTSRC_A_RESETEN_RTC0REN_MASK; in _SI32_RSTSRC_A_disable_rtc0_reset_source()
343 volatile uint32_t RESETEN_CLR; member
