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Searched refs:RDMEM_SEQ_RAMECCADDR_WIDTH (Results 1 – 25 of 109) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h1158 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21a010f512im32.h1158 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21a010f768im32.h1158 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21a020f1024im32.h1160 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21a020f512im32.h1160 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21a020f768im32.h1160 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21b010f1024im32.h1158 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21b010f512im32.h1158 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21b010f768im32.h1158 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21b020f1024im32.h1160 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21b020f512im32.h1160 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32mg21b020f768im32.h1160 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Drm21z000f1024im32.h1156 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c224f512gn32.h1178 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c224f512im32.h1178 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22e224f512im40.h1192 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c112f352gm32.h1176 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c224f512im40.h1192 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22e224f512im32.h1178 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c112f352gm40.h1190 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c222f352gm32.h1178 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c222f352gm40.h1192 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c222f352gn32.h1178 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c224f512gm32.h1178 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro
Defr32bg22c224f512gm40.h1192 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ macro

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