1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 BUFC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_BUFC_H 31 #define EFR32MG21_BUFC_H 32 #define BUFC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_BUFC BUFC 40 * @{ 41 * @brief EFR32MG21 BUFC Register Declaration. 42 *****************************************************************************/ 43 44 /** BUFC BUF Register Group Declaration. */ 45 typedef struct bufc_buf_typedef{ 46 __IOM uint32_t CTRL; /**< Buffer Control */ 47 __IOM uint32_t ADDR; /**< Buffer Address */ 48 __IOM uint32_t WRITEOFFSET; /**< Write Offset */ 49 __IOM uint32_t READOFFSET; /**< Read Offset */ 50 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 51 __IM uint32_t READDATA; /**< Buffer Read Data */ 52 __IOM uint32_t WRITEDATA; /**< Buffer Write Data */ 53 __IOM uint32_t XWRITE; /**< Buffer XOR Write */ 54 __IM uint32_t STATUS; /**< Buffer Status Register */ 55 __IOM uint32_t THRESHOLDCTRL; /**< Threshold Control */ 56 __IOM uint32_t CMD; /**< Buffer Command */ 57 __IOM uint32_t FIFOASYNC; /**< New Register */ 58 } BUFC_BUF_TypeDef; 59 60 /** BUFC Register Declaration. */ 61 typedef struct bufc_typedef{ 62 __IM uint32_t IPVERSION; /**< IP Version */ 63 __IOM uint32_t EN; /**< Enable peripheral clock to this module */ 64 BUFC_BUF_TypeDef BUF[4U]; /**< Data Buffer */ 65 uint32_t RESERVED0[6U]; /**< Reserved for future use */ 66 __IOM uint32_t IF; /**< BUFC Interrupt Flags */ 67 uint32_t RESERVED1[2U]; /**< Reserved for future use */ 68 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 69 __IOM uint32_t RAMBASEADDR; /**< New Register */ 70 uint32_t RESERVED2[963U]; /**< Reserved for future use */ 71 __IM uint32_t IPVERSION_SET; /**< IP Version */ 72 __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ 73 BUFC_BUF_TypeDef BUF_SET[4U]; /**< Data Buffer */ 74 uint32_t RESERVED3[6U]; /**< Reserved for future use */ 75 __IOM uint32_t IF_SET; /**< BUFC Interrupt Flags */ 76 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 77 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 78 __IOM uint32_t RAMBASEADDR_SET; /**< New Register */ 79 uint32_t RESERVED5[963U]; /**< Reserved for future use */ 80 __IM uint32_t IPVERSION_CLR; /**< IP Version */ 81 __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ 82 BUFC_BUF_TypeDef BUF_CLR[4U]; /**< Data Buffer */ 83 uint32_t RESERVED6[6U]; /**< Reserved for future use */ 84 __IOM uint32_t IF_CLR; /**< BUFC Interrupt Flags */ 85 uint32_t RESERVED7[2U]; /**< Reserved for future use */ 86 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 87 __IOM uint32_t RAMBASEADDR_CLR; /**< New Register */ 88 uint32_t RESERVED8[963U]; /**< Reserved for future use */ 89 __IM uint32_t IPVERSION_TGL; /**< IP Version */ 90 __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ 91 BUFC_BUF_TypeDef BUF_TGL[4U]; /**< Data Buffer */ 92 uint32_t RESERVED9[6U]; /**< Reserved for future use */ 93 __IOM uint32_t IF_TGL; /**< BUFC Interrupt Flags */ 94 uint32_t RESERVED10[2U]; /**< Reserved for future use */ 95 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 96 __IOM uint32_t RAMBASEADDR_TGL; /**< New Register */ 97 } BUFC_TypeDef; 98 /** @} End of group EFR32MG21_BUFC */ 99 100 /**************************************************************************//** 101 * @addtogroup EFR32MG21_BUFC 102 * @{ 103 * @defgroup EFR32MG21_BUFC_BitFields BUFC Bit Fields 104 * @{ 105 *****************************************************************************/ 106 107 /* Bit fields for BUFC IPVERSION */ 108 #define _BUFC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for BUFC_IPVERSION */ 109 #define _BUFC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BUFC_IPVERSION */ 110 #define _BUFC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BUFC_IPVERSION */ 111 #define _BUFC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_IPVERSION */ 112 #define _BUFC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IPVERSION */ 113 #define BUFC_IPVERSION_IPVERSION_DEFAULT (_BUFC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IPVERSION */ 114 115 /* Bit fields for BUFC EN */ 116 #define _BUFC_EN_RESETVALUE 0x00000000UL /**< Default value for BUFC_EN */ 117 #define _BUFC_EN_MASK 0x00000001UL /**< Mask for BUFC_EN */ 118 #define BUFC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ 119 #define _BUFC_EN_EN_SHIFT 0 /**< Shift value for BUFC_EN */ 120 #define _BUFC_EN_EN_MASK 0x1UL /**< Bit mask for BUFC_EN */ 121 #define _BUFC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_EN */ 122 #define BUFC_EN_EN_DEFAULT (_BUFC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_EN */ 123 124 /* Bit fields for BUFC BUF_CTRL */ 125 #define _BUFC_BUF_CTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CTRL */ 126 #define _BUFC_BUF_CTRL_MASK 0x00000007UL /**< Mask for BUFC_BUF_CTRL */ 127 #define _BUFC_BUF_CTRL_SIZE_SHIFT 0 /**< Shift value for BUFC_SIZE */ 128 #define _BUFC_BUF_CTRL_SIZE_MASK 0x7UL /**< Bit mask for BUFC_SIZE */ 129 #define _BUFC_BUF_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CTRL */ 130 #define _BUFC_BUF_CTRL_SIZE_SIZE64 0x00000000UL /**< Mode SIZE64 for BUFC_BUF_CTRL */ 131 #define _BUFC_BUF_CTRL_SIZE_SIZE128 0x00000001UL /**< Mode SIZE128 for BUFC_BUF_CTRL */ 132 #define _BUFC_BUF_CTRL_SIZE_SIZE256 0x00000002UL /**< Mode SIZE256 for BUFC_BUF_CTRL */ 133 #define _BUFC_BUF_CTRL_SIZE_SIZE512 0x00000003UL /**< Mode SIZE512 for BUFC_BUF_CTRL */ 134 #define _BUFC_BUF_CTRL_SIZE_SIZE1024 0x00000004UL /**< Mode SIZE1024 for BUFC_BUF_CTRL */ 135 #define _BUFC_BUF_CTRL_SIZE_SIZE2048 0x00000005UL /**< Mode SIZE2048 for BUFC_BUF_CTRL */ 136 #define _BUFC_BUF_CTRL_SIZE_SIZE4096 0x00000006UL /**< Mode SIZE4096 for BUFC_BUF_CTRL */ 137 #define BUFC_BUF_CTRL_SIZE_DEFAULT (_BUFC_BUF_CTRL_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CTRL */ 138 #define BUFC_BUF_CTRL_SIZE_SIZE64 (_BUFC_BUF_CTRL_SIZE_SIZE64 << 0) /**< Shifted mode SIZE64 for BUFC_BUF_CTRL */ 139 #define BUFC_BUF_CTRL_SIZE_SIZE128 (_BUFC_BUF_CTRL_SIZE_SIZE128 << 0) /**< Shifted mode SIZE128 for BUFC_BUF_CTRL */ 140 #define BUFC_BUF_CTRL_SIZE_SIZE256 (_BUFC_BUF_CTRL_SIZE_SIZE256 << 0) /**< Shifted mode SIZE256 for BUFC_BUF_CTRL */ 141 #define BUFC_BUF_CTRL_SIZE_SIZE512 (_BUFC_BUF_CTRL_SIZE_SIZE512 << 0) /**< Shifted mode SIZE512 for BUFC_BUF_CTRL */ 142 #define BUFC_BUF_CTRL_SIZE_SIZE1024 (_BUFC_BUF_CTRL_SIZE_SIZE1024 << 0) /**< Shifted mode SIZE1024 for BUFC_BUF_CTRL */ 143 #define BUFC_BUF_CTRL_SIZE_SIZE2048 (_BUFC_BUF_CTRL_SIZE_SIZE2048 << 0) /**< Shifted mode SIZE2048 for BUFC_BUF_CTRL */ 144 #define BUFC_BUF_CTRL_SIZE_SIZE4096 (_BUFC_BUF_CTRL_SIZE_SIZE4096 << 0) /**< Shifted mode SIZE4096 for BUFC_BUF_CTRL */ 145 146 /* Bit fields for BUFC BUF_ADDR */ 147 #define _BUFC_BUF_ADDR_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_ADDR */ 148 #define _BUFC_BUF_ADDR_MASK 0x00FFFFFFUL /**< Mask for BUFC_BUF_ADDR */ 149 #define _BUFC_BUF_ADDR_ADDR_SHIFT 0 /**< Shift value for BUFC_ADDR */ 150 #define _BUFC_BUF_ADDR_ADDR_MASK 0xFFFFFFUL /**< Bit mask for BUFC_ADDR */ 151 #define _BUFC_BUF_ADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_ADDR */ 152 #define BUFC_BUF_ADDR_ADDR_DEFAULT (_BUFC_BUF_ADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_ADDR */ 153 154 /* Bit fields for BUFC BUF_WRITEOFFSET */ 155 #define _BUFC_BUF_WRITEOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEOFFSET */ 156 #define _BUFC_BUF_WRITEOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_WRITEOFFSET */ 157 #define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_SHIFT 0 /**< Shift value for BUFC_WRITEOFFSET */ 158 #define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_WRITEOFFSET */ 159 #define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEOFFSET */ 160 #define BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT (_BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEOFFSET*/ 161 162 /* Bit fields for BUFC BUF_READOFFSET */ 163 #define _BUFC_BUF_READOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READOFFSET */ 164 #define _BUFC_BUF_READOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_READOFFSET */ 165 #define _BUFC_BUF_READOFFSET_READOFFSET_SHIFT 0 /**< Shift value for BUFC_READOFFSET */ 166 #define _BUFC_BUF_READOFFSET_READOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_READOFFSET */ 167 #define _BUFC_BUF_READOFFSET_READOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READOFFSET */ 168 #define BUFC_BUF_READOFFSET_READOFFSET_DEFAULT (_BUFC_BUF_READOFFSET_READOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READOFFSET*/ 169 170 /* Bit fields for BUFC BUF_READDATA */ 171 #define _BUFC_BUF_READDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA */ 172 #define _BUFC_BUF_READDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_READDATA */ 173 #define _BUFC_BUF_READDATA_READDATA_SHIFT 0 /**< Shift value for BUFC_READDATA */ 174 #define _BUFC_BUF_READDATA_READDATA_MASK 0xFFUL /**< Bit mask for BUFC_READDATA */ 175 #define _BUFC_BUF_READDATA_READDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA */ 176 #define BUFC_BUF_READDATA_READDATA_DEFAULT (_BUFC_BUF_READDATA_READDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA */ 177 178 /* Bit fields for BUFC BUF_WRITEDATA */ 179 #define _BUFC_BUF_WRITEDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA */ 180 #define _BUFC_BUF_WRITEDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_WRITEDATA */ 181 #define _BUFC_BUF_WRITEDATA_WRITEDATA_SHIFT 0 /**< Shift value for BUFC_WRITEDATA */ 182 #define _BUFC_BUF_WRITEDATA_WRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_WRITEDATA */ 183 #define _BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA */ 184 #define BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT (_BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA */ 185 186 /* Bit fields for BUFC BUF_XWRITE */ 187 #define _BUFC_BUF_XWRITE_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE */ 188 #define _BUFC_BUF_XWRITE_MASK 0x000000FFUL /**< Mask for BUFC_BUF_XWRITE */ 189 #define _BUFC_BUF_XWRITE_XORWRITEDATA_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA */ 190 #define _BUFC_BUF_XWRITE_XORWRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_XORWRITEDATA */ 191 #define _BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE */ 192 #define BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT (_BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE */ 193 194 /* Bit fields for BUFC BUF_STATUS */ 195 #define _BUFC_BUF_STATUS_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_STATUS */ 196 #define _BUFC_BUF_STATUS_MASK 0x00111FFFUL /**< Mask for BUFC_BUF_STATUS */ 197 #define _BUFC_BUF_STATUS_BYTES_SHIFT 0 /**< Shift value for BUFC_BYTES */ 198 #define _BUFC_BUF_STATUS_BYTES_MASK 0x1FFFUL /**< Bit mask for BUFC_BYTES */ 199 #define _BUFC_BUF_STATUS_BYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */ 200 #define BUFC_BUF_STATUS_BYTES_DEFAULT (_BUFC_BUF_STATUS_BYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */ 201 #define BUFC_BUF_STATUS_THRESHOLDFLAG (0x1UL << 20) /**< Buffer Threshold Flag */ 202 #define _BUFC_BUF_STATUS_THRESHOLDFLAG_SHIFT 20 /**< Shift value for BUFC_THRESHOLDFLAG */ 203 #define _BUFC_BUF_STATUS_THRESHOLDFLAG_MASK 0x100000UL /**< Bit mask for BUFC_THRESHOLDFLAG */ 204 #define _BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */ 205 #define BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT (_BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */ 206 207 /* Bit fields for BUFC BUF_THRESHOLDCTRL */ 208 #define _BUFC_BUF_THRESHOLDCTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_THRESHOLDCTRL */ 209 #define _BUFC_BUF_THRESHOLDCTRL_MASK 0x00002FFFUL /**< Mask for BUFC_BUF_THRESHOLDCTRL */ 210 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_SHIFT 0 /**< Shift value for BUFC_THRESHOLD */ 211 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_MASK 0xFFFUL /**< Bit mask for BUFC_THRESHOLD */ 212 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */ 213 #define BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/ 214 #define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE (0x1UL << 13) /**< Buffer Threshold Mode */ 215 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_SHIFT 13 /**< Shift value for BUFC_THRESHOLDMODE */ 216 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_MASK 0x2000UL /**< Bit mask for BUFC_THRESHOLDMODE */ 217 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */ 218 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER 0x00000000UL /**< Mode LARGER for BUFC_BUF_THRESHOLDCTRL */ 219 #define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL 0x00000001UL /**< Mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL */ 220 #define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT << 13) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/ 221 #define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER << 13) /**< Shifted mode LARGER for BUFC_BUF_THRESHOLDCTRL*/ 222 #define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL << 13) /**< Shifted mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL*/ 223 224 /* Bit fields for BUFC BUF_CMD */ 225 #define _BUFC_BUF_CMD_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CMD */ 226 #define _BUFC_BUF_CMD_MASK 0x0000000FUL /**< Mask for BUFC_BUF_CMD */ 227 #define BUFC_BUF_CMD_CLEAR (0x1UL << 0) /**< Buffer Clear */ 228 #define _BUFC_BUF_CMD_CLEAR_SHIFT 0 /**< Shift value for BUFC_CLEAR */ 229 #define _BUFC_BUF_CMD_CLEAR_MASK 0x1UL /**< Bit mask for BUFC_CLEAR */ 230 #define _BUFC_BUF_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */ 231 #define BUFC_BUF_CMD_CLEAR_DEFAULT (_BUFC_BUF_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */ 232 #define BUFC_BUF_CMD_PREFETCH (0x1UL << 1) /**< Prefetch */ 233 #define _BUFC_BUF_CMD_PREFETCH_SHIFT 1 /**< Shift value for BUFC_PREFETCH */ 234 #define _BUFC_BUF_CMD_PREFETCH_MASK 0x2UL /**< Bit mask for BUFC_PREFETCH */ 235 #define _BUFC_BUF_CMD_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */ 236 #define BUFC_BUF_CMD_PREFETCH_DEFAULT (_BUFC_BUF_CMD_PREFETCH_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */ 237 238 /* Bit fields for BUFC BUF_FIFOASYNC */ 239 #define _BUFC_BUF_FIFOASYNC_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_FIFOASYNC */ 240 #define _BUFC_BUF_FIFOASYNC_MASK 0x00000001UL /**< Mask for BUFC_BUF_FIFOASYNC */ 241 #define BUFC_BUF_FIFOASYNC_RST (0x1UL << 0) /**< Reset ASYNC */ 242 #define _BUFC_BUF_FIFOASYNC_RST_SHIFT 0 /**< Shift value for BUFC_RST */ 243 #define _BUFC_BUF_FIFOASYNC_RST_MASK 0x1UL /**< Bit mask for BUFC_RST */ 244 #define _BUFC_BUF_FIFOASYNC_RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_FIFOASYNC */ 245 #define BUFC_BUF_FIFOASYNC_RST_DEFAULT (_BUFC_BUF_FIFOASYNC_RST_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_FIFOASYNC */ 246 247 /* Bit fields for BUFC IF */ 248 #define _BUFC_IF_RESETVALUE 0x00000000UL /**< Default value for BUFC_IF */ 249 #define _BUFC_IF_MASK 0x8F0F0F0FUL /**< Mask for BUFC_IF */ 250 #define BUFC_IF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */ 251 #define _BUFC_IF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */ 252 #define _BUFC_IF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */ 253 #define _BUFC_IF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 254 #define BUFC_IF_BUF0OF_DEFAULT (_BUFC_IF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IF */ 255 #define BUFC_IF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */ 256 #define _BUFC_IF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */ 257 #define _BUFC_IF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */ 258 #define _BUFC_IF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 259 #define BUFC_IF_BUF0UF_DEFAULT (_BUFC_IF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IF */ 260 #define BUFC_IF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */ 261 #define _BUFC_IF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */ 262 #define _BUFC_IF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */ 263 #define _BUFC_IF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 264 #define BUFC_IF_BUF0THR_DEFAULT (_BUFC_IF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IF */ 265 #define BUFC_IF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */ 266 #define _BUFC_IF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */ 267 #define _BUFC_IF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */ 268 #define _BUFC_IF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 269 #define BUFC_IF_BUF0CORR_DEFAULT (_BUFC_IF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IF */ 270 #define BUFC_IF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */ 271 #define _BUFC_IF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */ 272 #define _BUFC_IF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */ 273 #define _BUFC_IF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 274 #define BUFC_IF_BUF1OF_DEFAULT (_BUFC_IF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IF */ 275 #define BUFC_IF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */ 276 #define _BUFC_IF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */ 277 #define _BUFC_IF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */ 278 #define _BUFC_IF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 279 #define BUFC_IF_BUF1UF_DEFAULT (_BUFC_IF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IF */ 280 #define BUFC_IF_BUF1THR (0x1UL << 10) /**< Buffer 2 Threshold Event */ 281 #define _BUFC_IF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */ 282 #define _BUFC_IF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */ 283 #define _BUFC_IF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 284 #define BUFC_IF_BUF1THR_DEFAULT (_BUFC_IF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IF */ 285 #define BUFC_IF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */ 286 #define _BUFC_IF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */ 287 #define _BUFC_IF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */ 288 #define _BUFC_IF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 289 #define BUFC_IF_BUF1CORR_DEFAULT (_BUFC_IF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IF */ 290 #define BUFC_IF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */ 291 #define _BUFC_IF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */ 292 #define _BUFC_IF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */ 293 #define _BUFC_IF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 294 #define BUFC_IF_BUF2OF_DEFAULT (_BUFC_IF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IF */ 295 #define BUFC_IF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */ 296 #define _BUFC_IF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */ 297 #define _BUFC_IF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */ 298 #define _BUFC_IF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 299 #define BUFC_IF_BUF2UF_DEFAULT (_BUFC_IF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IF */ 300 #define BUFC_IF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */ 301 #define _BUFC_IF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */ 302 #define _BUFC_IF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */ 303 #define _BUFC_IF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 304 #define BUFC_IF_BUF2THR_DEFAULT (_BUFC_IF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IF */ 305 #define BUFC_IF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */ 306 #define _BUFC_IF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */ 307 #define _BUFC_IF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */ 308 #define _BUFC_IF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 309 #define BUFC_IF_BUF2CORR_DEFAULT (_BUFC_IF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IF */ 310 #define BUFC_IF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */ 311 #define _BUFC_IF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */ 312 #define _BUFC_IF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */ 313 #define _BUFC_IF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 314 #define BUFC_IF_BUF3OF_DEFAULT (_BUFC_IF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IF */ 315 #define BUFC_IF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */ 316 #define _BUFC_IF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */ 317 #define _BUFC_IF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */ 318 #define _BUFC_IF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 319 #define BUFC_IF_BUF3UF_DEFAULT (_BUFC_IF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IF */ 320 #define BUFC_IF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */ 321 #define _BUFC_IF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */ 322 #define _BUFC_IF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */ 323 #define _BUFC_IF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 324 #define BUFC_IF_BUF3THR_DEFAULT (_BUFC_IF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IF */ 325 #define BUFC_IF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */ 326 #define _BUFC_IF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */ 327 #define _BUFC_IF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */ 328 #define _BUFC_IF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 329 #define BUFC_IF_BUF3CORR_DEFAULT (_BUFC_IF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IF */ 330 #define BUFC_IF_BUSERROR (0x1UL << 31) /**< Bus Error */ 331 #define _BUFC_IF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */ 332 #define _BUFC_IF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */ 333 #define _BUFC_IF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */ 334 #define BUFC_IF_BUSERROR_DEFAULT (_BUFC_IF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IF */ 335 336 /* Bit fields for BUFC IEN */ 337 #define _BUFC_IEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_IEN */ 338 #define _BUFC_IEN_MASK 0x8F0F0F0FUL /**< Mask for BUFC_IEN */ 339 #define BUFC_IEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */ 340 #define _BUFC_IEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */ 341 #define _BUFC_IEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */ 342 #define _BUFC_IEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 343 #define BUFC_IEN_BUF0OF_DEFAULT (_BUFC_IEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IEN */ 344 #define BUFC_IEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */ 345 #define _BUFC_IEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */ 346 #define _BUFC_IEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */ 347 #define _BUFC_IEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 348 #define BUFC_IEN_BUF0UF_DEFAULT (_BUFC_IEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IEN */ 349 #define BUFC_IEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */ 350 #define _BUFC_IEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */ 351 #define _BUFC_IEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */ 352 #define _BUFC_IEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 353 #define BUFC_IEN_BUF0THR_DEFAULT (_BUFC_IEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IEN */ 354 #define BUFC_IEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */ 355 #define _BUFC_IEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */ 356 #define _BUFC_IEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */ 357 #define _BUFC_IEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 358 #define BUFC_IEN_BUF0CORR_DEFAULT (_BUFC_IEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IEN */ 359 #define BUFC_IEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */ 360 #define _BUFC_IEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */ 361 #define _BUFC_IEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */ 362 #define _BUFC_IEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 363 #define BUFC_IEN_BUF1OF_DEFAULT (_BUFC_IEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IEN */ 364 #define BUFC_IEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */ 365 #define _BUFC_IEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */ 366 #define _BUFC_IEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */ 367 #define _BUFC_IEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 368 #define BUFC_IEN_BUF1UF_DEFAULT (_BUFC_IEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IEN */ 369 #define BUFC_IEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */ 370 #define _BUFC_IEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */ 371 #define _BUFC_IEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */ 372 #define _BUFC_IEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 373 #define BUFC_IEN_BUF1THR_DEFAULT (_BUFC_IEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IEN */ 374 #define BUFC_IEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */ 375 #define _BUFC_IEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */ 376 #define _BUFC_IEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */ 377 #define _BUFC_IEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 378 #define BUFC_IEN_BUF1CORR_DEFAULT (_BUFC_IEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IEN */ 379 #define BUFC_IEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */ 380 #define _BUFC_IEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */ 381 #define _BUFC_IEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */ 382 #define _BUFC_IEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 383 #define BUFC_IEN_BUF2OF_DEFAULT (_BUFC_IEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IEN */ 384 #define BUFC_IEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */ 385 #define _BUFC_IEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */ 386 #define _BUFC_IEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */ 387 #define _BUFC_IEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 388 #define BUFC_IEN_BUF2UF_DEFAULT (_BUFC_IEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IEN */ 389 #define BUFC_IEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */ 390 #define _BUFC_IEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */ 391 #define _BUFC_IEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */ 392 #define _BUFC_IEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 393 #define BUFC_IEN_BUF2THR_DEFAULT (_BUFC_IEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IEN */ 394 #define BUFC_IEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */ 395 #define _BUFC_IEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */ 396 #define _BUFC_IEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */ 397 #define _BUFC_IEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 398 #define BUFC_IEN_BUF2CORR_DEFAULT (_BUFC_IEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IEN */ 399 #define BUFC_IEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */ 400 #define _BUFC_IEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */ 401 #define _BUFC_IEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */ 402 #define _BUFC_IEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 403 #define BUFC_IEN_BUF3OF_DEFAULT (_BUFC_IEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IEN */ 404 #define BUFC_IEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */ 405 #define _BUFC_IEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */ 406 #define _BUFC_IEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */ 407 #define _BUFC_IEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 408 #define BUFC_IEN_BUF3UF_DEFAULT (_BUFC_IEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IEN */ 409 #define BUFC_IEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */ 410 #define _BUFC_IEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */ 411 #define _BUFC_IEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */ 412 #define _BUFC_IEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 413 #define BUFC_IEN_BUF3THR_DEFAULT (_BUFC_IEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IEN */ 414 #define BUFC_IEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */ 415 #define _BUFC_IEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */ 416 #define _BUFC_IEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */ 417 #define _BUFC_IEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 418 #define BUFC_IEN_BUF3CORR_DEFAULT (_BUFC_IEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IEN */ 419 #define BUFC_IEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */ 420 #define _BUFC_IEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */ 421 #define _BUFC_IEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */ 422 #define _BUFC_IEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */ 423 #define BUFC_IEN_BUSERROR_DEFAULT (_BUFC_IEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IEN */ 424 425 /* Bit fields for BUFC RAMBASEADDR */ 426 #define _BUFC_RAMBASEADDR_RESETVALUE 0x20000000UL /**< Default value for BUFC_RAMBASEADDR */ 427 #define _BUFC_RAMBASEADDR_MASK 0xFFFF0000UL /**< Mask for BUFC_RAMBASEADDR */ 428 #define _BUFC_RAMBASEADDR_RAMBASEADDR_SHIFT 16 /**< Shift value for BUFC_RAMBASEADDR */ 429 #define _BUFC_RAMBASEADDR_RAMBASEADDR_MASK 0xFFFF0000UL /**< Bit mask for BUFC_RAMBASEADDR */ 430 #define _BUFC_RAMBASEADDR_RAMBASEADDR_DEFAULT 0x00002000UL /**< Mode DEFAULT for BUFC_RAMBASEADDR */ 431 #define BUFC_RAMBASEADDR_RAMBASEADDR_DEFAULT (_BUFC_RAMBASEADDR_RAMBASEADDR_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_RAMBASEADDR */ 432 433 /** @} End of group EFR32MG21_BUFC_BitFields */ 434 /** @} End of group EFR32MG21_BUFC */ 435 /** @} End of group Parts */ 436 437 #endif // EFR32MG21_BUFC_H 438
