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Searched refs:RAM1_MEM_BASE (Results 1 – 25 of 187) sorted by relevance

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/hal_silabs-latest/gecko/emlib/src/
Dem_msc.c79 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE)
103 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE)
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_msc.c79 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE)
103 #define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE)
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b810f1024gl112.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b810f1024gl120.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b830f512gm64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b830f512il112.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b830f512il120.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b830f512iq100.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b830f512iq64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b810f1024gm64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b810f1024gq100.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b810f1024gq64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b810f1024il112.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b410f1024im64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b410f1024iq100.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b410f1024iq64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512gl120.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512gm64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512gq100.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512gq64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512il112.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512il120.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512im64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512iq100.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro
Defm32gg12b430f512iq64.h174 #define RAM1_MEM_BASE (0x20010000UL) /**< RAM1 base address */ macro

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