1 /***************************************************************************/ /** 2 * @file rsi_qspi.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 // Include Files 31 32 #include "rsi_ccp_common.h" 33 #include "base_types.h" 34 #include "stdint.h" 35 #include "rsi_qspi_proto.h" 36 37 #ifndef RSI_QSPI_H 38 #define RSI_QSPI_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 // QSPI defines 45 #define TA_QSPI_BASE_ADDRESS 0x10000000 46 #define M4_QSPI_BASE_ADDRESS 0x12000000 47 #define M4_QSPI_2_BASE_ADDRESS 0x12040000 48 #define TA_QSPI_AUTOM_CHIP0_ADDRESS 0x04000000 49 #define M4_QSPI_AUTOM_CHIP0_ADDRESS 0x08000000 50 51 #define NWP_FSM_BASE_ADDR 0x41300000 52 #define MCU_NPSS_BASE_ADDR 0x24048000 53 #define MCU_FSM_BASE_ADDR MCU_NPSS_BASE_ADDR + 0x100 54 #define M4_BBFF_STORAGE1 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0580) 55 #define M4_BBFF_STORAGE2 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0584) 56 #define MCURET_BOOTSTATUS_REG *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x604) 57 #define TA_BBFF_STORAGE1 *(volatile uint32_t *)(NWP_FSM_BASE_ADDR + 0x580) 58 #define TA_BBFF_STORAGE2 *(volatile uint32_t *)(NWP_FSM_BASE_ADDR + 0x584) 59 60 // This structure contains qspi registers 61 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 62 struct qspi_reg_s { 63 volatile uint32_t QSPI_CLK_CONFIG_REG; // qspi reg 64 volatile uint32_t QSPI_BUS_MODE_REG; // qspi reg 65 volatile uint32_t QSPI_AUTO_CTRL_CONFIG_1_REG; // qspi reg 66 volatile uint32_t QSPI_AUTO_CTRL_CONFIG_2_REG; // qspi reg 67 volatile uint32_t QSPI_MANUAL_CONFIG_REG; // qspi reg 68 volatile uint32_t QSPI_MANUAL_CONFIG_2_REG; // qspi reg 69 70 volatile uint32_t RESERVED_1; // qspi reg 71 volatile uint32_t QSPI_FIFO_THRESHOLD_REG; // qspi reg 72 volatile uint32_t QSPI_STATUS_REG; // qspi reg 73 volatile uint32_t QSPI_INTR_MASK_REG; // qspi reg 74 volatile uint32_t QSPI_INTR_UNMASK_REG; // qspi reg 75 volatile uint32_t QSPI_INTR_STS_REG; // qspi reg 76 volatile uint32_t QSPI_INTR_ACK_REG; // qspi reg 77 volatile uint32_t QSPI_STS_MC_REG; // qspi reg 78 volatile uint32_t QSPI_AUTO_CONFIG_1_CSN1_REG; // qspi reg 79 volatile uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; // qspi reg 80 volatile uint32_t QSPI_MANUAL_RD_WR_DATA_REG; // qspi reg 81 volatile uint32_t RESERVED_2[15]; // qspi reg 82 volatile uint32_t QSPI_MANUAL_WRITE_DATA_2_REG; // qspi reg 83 volatile uint32_t RESERVED_3[3]; // qspi reg 84 volatile uint32_t QSPI_AUTO_CONFIG3; 85 volatile uint32_t QSPI_AUTO_CONFIG3_CSN1; 86 volatile uint32_t RESERVED_4[6]; // qspi reg 87 volatile uint32_t OCTA_SPI_BUS_CONTROLLER; // qspi reg :2c 88 volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; 89 volatile uint32_t RESERVED_7[3]; // qspi reg 90 volatile uint32_t OCTA_SPI_BUS_CONTROLLER2; // qspi reg:31 91 #if defined(SLI_SI917) || defined(SLI_SI915) 92 volatile uint32_t QSPI_AES_CONFIG; // qspi reg 93 volatile uint32_t QSPI_AES_KEY_IV_VALID; // qspi reg 94 volatile uint32_t QSPI_AES_IV1_0_3; // qspi reg 95 volatile uint32_t QSPI_AES_IV1_4_7; // qspi reg 96 volatile uint32_t QSPI_AES_IV1_8_B; // qspi reg 97 volatile uint32_t QSPI_AES_IV1_C_F; // qspi reg 98 volatile uint32_t RESERVED_8; // qspi reg 99 #else 100 volatile uint32_t QSPI_AES_KEY_0_3; // qspi reg 101 volatile uint32_t QSPI_AES_KEY_4_7; // qspi reg 102 volatile uint32_t QSPI_AES_KEY_8_B; // qspi reg 103 volatile uint32_t QSPI_AES_KEY_C_F; // qspi reg 104 volatile uint32_t QSPI_AES_NONCE_0_3; // qspi reg 105 volatile uint32_t QSPI_AES_NONCE_4_7; // qspi reg 106 volatile uint32_t QSPI_AES_NONCE_8_B; // qspi reg 107 #endif 108 volatile uint32_t QSPI_AES_SEC_SEG_ADDR[4 * 2]; // qspi reg 109 volatile uint32_t RESERVED_6[6]; // qspi reg 110 volatile uint32_t QSPI_SEMI_AUTO_ADDR_REG; 111 volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG_REG; 112 volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG2_REG; 113 volatile uint32_t QSPI_BUS_MODE2_REG; 114 volatile uint32_t QSPI_AES_SEC_KEY_FRM_KH; 115 volatile uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; // qspi reg 116 #if defined(SLI_SI917) || defined(SLI_SI915) 117 volatile uint32_t QSPI_AES_KEY1_0_3; // qspi reg 118 volatile uint32_t QSPI_AES_KEY1_4_7; // qspi reg 119 volatile uint32_t QSPI_AES_KEY1_8_B; // qspi reg 120 volatile uint32_t QSPI_AES_KEY1_C_F; // qspi reg 121 volatile uint32_t QSPI_AES_KEY1_10_13; // qspi reg 122 volatile uint32_t QSPI_AES_KEY1_14_17; // qspi reg 123 volatile uint32_t QSPI_AES_KEY1_18_1B; // qspi reg 124 volatile uint32_t QSPI_AES_KEY1_1C_1F; // qspi reg 125 volatile uint32_t QSPI_AES_KEY2_0_3; // qspi reg 126 volatile uint32_t QSPI_AES_KEY2_4_7; // qspi reg 127 volatile uint32_t QSPI_AES_KEY2_8_B; // qspi reg 128 volatile uint32_t QSPI_AES_KEY2_C_F; // qspi reg 129 volatile uint32_t QSPI_AES_KEY2_10_13; // qspi reg 130 volatile uint32_t QSPI_AES_KEY2_14_17; // qspi reg 131 volatile uint32_t QSPI_AES_KEY2_18_1B; // qspi reg 132 volatile uint32_t QSPI_AES_KEY2_1C_1F; // qspi reg 133 volatile uint32_t QSPI_AES_IV2_0_3; // qspi reg 134 volatile uint32_t QSPI_AES_IV2_4_7; // qspi reg 135 volatile uint32_t QSPI_AES_IV2_8_B; // qspi reg 136 volatile uint32_t QSPI_AES_IV2_C_F; // qspi reg 137 volatile uint32_t QSPI_AES_CTXOUT_IV1_0_3; // qspi reg 138 volatile uint32_t QSPI_AES_CTXOUT_IV1_4_7; // qspi reg 139 volatile uint32_t QSPI_AES_CTXOUT_IV1_8_B; // qspi reg 140 volatile uint32_t QSPI_AES_CTXOUT_IV1_C_F; // qspi reg 141 volatile uint32_t QSPI_AES_CTXOUT_IV2_0_3; // qspi reg 142 volatile uint32_t QSPI_AES_CTXOUT_IV2_4_7; // qspi reg 143 volatile uint32_t QSPI_AES_CTXOUT_IV2_8_B; // qspi reg 144 volatile uint32_t QSPI_AES_CTXOUT_IV2_C_F; // qspi reg 145 #endif 146 }; 147 148 #else 149 struct qspi_reg_s { 150 volatile uint32_t QSPI_CLK_CONFIG_REG; // qspi reg 0x00 151 volatile uint32_t QSPI_BUS_MODE_REG; // qspi reg 0x04 152 volatile uint32_t QSPI_AUTO_CTRL_CONFIG_1_REG; // qspi reg 0x08 153 volatile uint32_t QSPI_AUTO_CTRL_CONFIG_2_REG; // qspi reg 0x0C 154 volatile uint32_t QSPI_MANUAL_CONFIG_REG; // qspi reg 0x10 155 volatile uint32_t QSPI_MANUAL_CONFIG_2_REG; // qspi reg 0x14 156 157 volatile uint32_t RESERVED_1; // qspi reg 0x18 158 volatile uint32_t QSPI_FIFO_THRESHOLD_REG; // qspi reg 0x1c 159 volatile uint32_t QSPI_STATUS_REG; // qspi reg 0x20 160 volatile uint32_t QSPI_INTR_MASK_REG; // qspi reg 0x24 161 volatile uint32_t QSPI_INTR_UNMASK_REG; // qspi reg 0x28 162 volatile uint32_t QSPI_INTR_STS_REG; // qspi reg 0x2C 163 volatile uint32_t QSPI_INTR_ACK_REG; // qspi reg 0x30 164 volatile uint32_t QSPI_STS_MC_REG; // qspi reg 0x34 165 volatile uint32_t QSPI_AUTO_CONFIG_1_CSN1_REG; // qspi reg 0x38 166 volatile uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; // qspi reg 0x3C 167 volatile uint32_t QSPI_MANUAL_RD_WR_DATA_REG; // qspi reg 0x40 168 volatile uint32_t RESERVED_2[15]; // qspi reg -0x7c 169 volatile uint32_t QSPI_MANUAL_WRITE_DATA_2_REG; // qspi reg 0x80 170 volatile uint32_t RESERVED_3[3]; // qspi reg -0x8C 171 volatile uint32_t QSPI_AUTO_CONFIG3; // qspi reg 0x90 172 volatile uint32_t QSPI_AUTO_CONFIG3_CSN1; // qspi reg 0x94 173 volatile uint32_t RESERVED_4[2]; // qspi reg -0x9C 174 175 volatile uint32_t QSPI_AUTO_BASE_ADDR_CSN0; // qspi reg 0xA0 176 volatile uint32_t QSPI_AUTO_BASE_ADDR_CSN1; // qspi reg 0xA4 177 178 volatile uint32_t RESERVED_5[2]; // qspi reg -0xAC 179 180 volatile uint32_t OCTA_SPI_BUS_CONTROLLER; // qspi reg 0xB0 181 volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; // qspi reg 0xB4 182 183 volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; // qspi reg 0xB8 184 185 volatile uint32_t RESERVED_6[2]; // qspi reg -0xC0 186 volatile uint32_t OCTA_SPI_BUS_CONTROLLER2; // qspi reg 0xC4 187 188 volatile uint32_t QSPI_AES_CONFIG; // qspi reg 0xC8 189 volatile uint32_t QSPI_AES_KEY_IV_VALID; // qspi reg 0xCC 190 191 volatile uint32_t QSPI_CMNFLASH_STS; // qspi reg 0xD0 192 193 volatile uint32_t QSPI_AES_LB_DATA_0_3; // qspi reg 0xD4 194 volatile uint32_t QSPI_AES_LB_DATA_4_7; // qspi reg 0xD8 195 volatile uint32_t QSPI_AES_LB_DATA_8_B; // qspi reg 0xDC 196 volatile uint32_t QSPI_AES_LB_DATA_C_F; // qspi reg 0xE0 197 198 volatile uint32_t QSPI_AES_SEC_SEG_ADDR[4 * 2]; // qspi reg -0x100 199 200 volatile uint32_t QSPI_SRAM_CTRL_CSN0_REG; // qspi reg 0x104 201 volatile uint32_t QSPI_SRAM_CTRL_CSN1_REG; // qspi reg 0x108 202 volatile uint32_t QSPI_SRAM_CTRL_CSN2_REG; // qspi reg 0x10C 203 volatile uint32_t QSPI_SRAM_CTRL_CSN3_REG; // qspi reg 0x110 204 205 volatile uint32_t CCMP_LBK_CTRL_REG; // qspi reg 0x114 206 volatile uint32_t RESERVED_7; // qspi reg -0x118 207 208 volatile uint32_t QSPI_SEMI_AUTO_ADDR_REG; // qspi reg 0x11C 209 volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG_REG; // qspi reg 0x120 210 volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG2_REG; // qspi reg 0x124 211 volatile uint32_t QSPI_BUS_MODE2_REG; // qspi reg 0x128 212 volatile uint32_t QSPI_AES_SEC_KEY_FRM_KH; // qspi reg 0x12C 213 volatile uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; // qspi reg 0x130 214 215 volatile uint32_t QSPI_AES_KEY1_0_3; // qspi reg 0x134 216 volatile uint32_t QSPI_AES_KEY1_4_7; // qspi reg 0x138 217 volatile uint32_t QSPI_AES_KEY1_8_B; // qspi reg 0x13C 218 volatile uint32_t QSPI_AES_KEY1_C_F; // qspi reg 0x140 219 volatile uint32_t QSPI_AES_KEY1_10_13; // qspi reg 0x144 220 volatile uint32_t QSPI_AES_KEY1_14_17; // qspi reg 0x148 221 volatile uint32_t QSPI_AES_KEY1_18_1B; // qspi reg 0x14C 222 volatile uint32_t QSPI_AES_KEY1_1C_1F; // qspi reg 0x150 223 volatile uint32_t QSPI_AES_KEY2_0_3; // qspi reg 0x154 224 volatile uint32_t QSPI_AES_KEY2_4_7; // qspi reg 0x158 225 volatile uint32_t QSPI_AES_KEY2_8_B; // qspi reg 0x15C 226 volatile uint32_t QSPI_AES_KEY2_C_F; // qspi reg 0x160 227 volatile uint32_t QSPI_AES_KEY2_10_13; // qspi reg 0x164 228 volatile uint32_t QSPI_AES_KEY2_14_17; // qspi reg 0x168 229 volatile uint32_t QSPI_AES_KEY2_18_1B; // qspi reg 0x16C 230 volatile uint32_t QSPI_AES_KEY2_1C_1F; // qspi reg 0x170 231 volatile uint32_t QSPI_AES_IV1_0_3; // qspi reg 0x174 232 volatile uint32_t QSPI_AES_IV1_4_7; // qspi reg 0x178 233 volatile uint32_t QSPI_AES_IV1_8_B; // qspi reg 0x17C 234 volatile uint32_t QSPI_AES_IV1_C_F; // qspi reg 0x180 235 volatile uint32_t QSPI_LB_STATUS; // qspi reg 0x184 236 }; 237 #endif 238 239 #define XMAX(x, y) (((x) > (y)) ? (x) : (y)) 240 #define XMIN(x, y) (((x) < (y)) ? (x) : (y)) 241 242 #define QSPI_BASE_ADDRESS 0x12000000 243 #define QSPI_AUTOM_CHIP0_ADDRESS 0x08000000 244 #define QSPI_AUTOM_CHIP1_ADDRESS 0x09000000 245 #define PAD_CONFIGURATION_BASE_ADDR 0x41380000 246 #define TASS_CLK_PWR_CTRL_BASE_ADDR 0x41400000 247 #define GPIO_BASE_ADDR 0x40200000 248 #define DMA_BASE_ADDR 0x21000000 249 #define M4SS_CLK_PWR_CTRL_BASE_ADDR 0x46000000 250 #define M4GPIO_BASE_ADDR 0x46130000 251 #define M4PAD_CONFIGURATION_BASE_ADDR 0x46004000 252 #define M4PAD_SELECTION_BASE_ADDR 0x41300000 253 254 #define MISC_CONFIGURATION_REG 0x46008000 255 #define M4SS_QSPI_OCTA_MODE_CTRL *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1B4) 256 #define M4SS_QSPI_RX_DLL_TEST_REG *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1C0) 257 #define M4SS_QSPI_TX_DLL_TEST_REG *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1BC) 258 259 #define qspi_ddr_data_0 0 260 #define qspi_ddr_data_1 1 261 #define qspi_ddr_data_2 2 262 #define qspi_ddr_data_3 3 263 #define qspi_ddr_data_4 4 264 #define qspi_ddr_data_5 5 265 #define qspi_ddr_data_6 6 266 #define qspi_ddr_data_7 7 267 #define qspi_ddr_csn 8 268 #define qspi_ddr_clk 9 269 #define qspi_ddr_dqs 10 270 #define smih_wp 11 271 272 #define CHNL_21 21 273 #define CHNL_20 20 274 275 // Qspi register defines 276 277 // cmd len will be 8 bits 278 #define CMD_LEN 8 279 // reg bit 280 #define RD_FIFO_EMPTY BIT(7) 281 // reg bit 282 #define Q_QSPI_BUSY BIT(0) 283 // QSPI_MANUAL_CONFIG_REG bits 284 #define FULL_DUPLEX_EN BIT(22) 285 #define TAKE_LEN_FRM_REG BIT(21) 286 #define HW_CTRL_MODE BIT(25) 287 #define READ_TRIGGER BIT(2) 288 #define WRITE_TRIGGER BIT(1) 289 #define CSN_ACTIVE BIT(0) 290 291 // QSPI_MANUAL_CONFIG_2_REG bits 292 #define QSPI_LOOP_BACK_MODE_EN BIT(14) 293 #define QSPI_MANUAL_DDR_PHASSE BIT(15) 294 #define QSPI_DDR_CLK_EN BIT(16) 295 296 // QSPI_CLK_CONFIG_REG bits 297 #define QSPI_DLL_CALIB BIT(28) 298 #define QSPI_DLL_TX_EN BIT(21) 299 #define QSPI_DLL_RX_EN BIT(19) 300 301 // QSPI_AUTO_CTRL_CONFIG_1_REG bits 302 #define EXTRA_BYTE_EN BIT(18) 303 304 // QSPI_AUTO_CTRL_CONFIG_2_REG bits 305 #define AUTO_RD_SWAP BIT(0) 306 307 // QSPI_SEMI_AUTO_MODE_CONFIG2_REG 308 #define SEMI_AUTO_MODE_EN BIT(12) 309 #define QSPI_SEMI_AUTO_RD_BUSY BIT(13) 310 311 #define _1BYTE 0 312 #define _2BYTE 1 313 #define _4BYTE 3 314 315 // QSPI_STATUS_REG bits 316 #define HW_CTRLD_QSPI_MODE_CTRL_SCLK BIT(14) 317 #define AUTO_MODE_ENABLED BIT(12) 318 #define QSPI_AUTO_MODE BIT(11) 319 #define AUTO_MODE_FSM_IDLE_SCLK BIT(10) 320 #define QSPI_MANUAL_RD_CNT BIT(9) 321 #define QSPI_FIFO_AEMPTY_RFIFO_S BIT(8) 322 #define QSPI_FIFO_EMPTY_RFIFO_S BIT(7) 323 #define QSPI_FIFO_AFULL_RFIFO BIT(6) 324 #define QSPI_FIFO_FULL_RFIFO BIT(5) 325 #define QSPI_FIFO_AEMPTY_WFIFO BIT(4) 326 #define QSPI_FIFO_EMPTY_WFIFO BIT(3) 327 #define QSPI_FIFO_AFULL_WFIFO_S BIT(2) 328 #define QSPI_FIFO_FULL_WFIFO_S BIT(1) 329 #define BUSY BIT(0) 330 331 #define QSPI_FIFO_DEPTH 16 332 #define QSPI_FIFO_AFULL_TH 3 333 #define QSPI_FIFO_AEMPTY_TH 3 334 335 // QSPI_BUS_MODE_REG bits 336 #define AUTO_CSN_BASED_ADDR_ENABLE BIT(7) 337 #define AUTO_MODE BIT(6) 338 #define QSPI_WRAP_EN BIT(5) 339 #define QSPI_PREFETCH_EN BIT(4) 340 #define QSPI_ULTRA_HIGH_SPEED_MODE_EN BIT(0) 341 342 // QSPI_AUTO_CONFIG3 bits 343 #define QSPI_RD_INST_CSN0_MSB 24 344 #define QSPI_CMD_SIZE_16BIT_CSN0 BIT(18) 345 #define QSPI_ADR_SIZE_32BIT_AUTO_MODE BIT(19) 346 347 // QSPI_MANUAL_WRITE_DATA_2_REG bits 348 #define USE_PREV_LEN BIT(7) 349 350 // OCTA_SPI_BUS_CONTRLLER_2 bits 351 #define DUAL_FLASH_MODE BIT(3) 352 353 // FLASH CMDS 354 355 // Write enable cmd 356 #define WREN 0x06 357 #define WREN2 0xF9 358 // Write disable cmd 359 #define WRDI 0x04 360 #define WRDI2 0xFB 361 // Read status reg cmd 362 #define RDSR 0x05 363 #define RDSR2 0xFA 364 // chip erase cmd 365 #define CHIP_ERASE 0xC7 366 // block erase cmd 367 #define BLOCK_ERASE 0xD8 368 // sector erase cmd 369 #define SECTOR_ERASE 0x20 370 // high speed rd cmd 371 #define HISPEED_READ 0x0B 372 // rd cmd 373 #define READ 0x03 374 //write config2 375 #define WCFG2 0x72 376 377 // SST25 specific cmds 378 379 // Write status reg cmd 380 #define WRSR 0x01 381 #define WRSR2 0xFE 382 // Enable Write status reg cmd 383 #define EWSR 0x50 384 // Auto address incremental rd cmd 385 #define AAI 0xAF 386 // Byte program cmd 387 #define BYTE_PROGRAM 0x02 388 389 // SST26 specific cmds 390 391 // Enable quad IO 392 #define EQIO 0x38 393 // Reset quad IO 394 #define RSTQIO 0xFF 395 // Enable STR octa 396 #define OPI_ENABLE 0X01 397 // Enable DDR octa 398 #define DOPI_ENABLE 0x02 399 // wrap : set burst 400 #define SET_BURST 0xC0 401 // wrap : read cmd 402 #define READ_BURST 0x0C 403 // Jump : page index read 404 #define READ_PI 0x08 405 // Jump : Index read 406 #define READ_I 0x09 407 // Jump : Block Index read 408 #define READ_BI 0x10 409 // Page program cmd 410 #define PAGE_PROGRAM 0x02 411 // write suspend cmd 412 #define Write_Suspend 0xB0 413 // write resume cmd 414 #define Write_Resume 0x30 415 // read block protection reg 416 #define RBPR 0x72 417 // Write block protection reg 418 #define WBPR 0x42 419 // Lockdown block protection reg 420 #define LBPR 0x8D 421 422 // WINBOND + AT + MACRONIX specific cmds 423 424 // fast read dual output 425 #define FREAD_DUAL_O 0x3B 426 // fast read quad output 427 #define FREAD_QUAD_O 0x6B 428 429 #define FREAD_QUAD_O_EB 0xEB 430 431 // WINBOND + MACRONIX specific cmds 432 433 // fast read dual IO 434 #define FREAD_DUAL_IO 0xBB 435 // fast read quad IO 436 #define FREAD_QUAD_IO 0xEB 437 438 // WINBOND specific cmds 439 440 // Octal word read (A7-A0 must be 00) 441 #define OCTAL_WREAD 0xE3 442 // Enable high performance cmd 443 #define HI_PERFMNC 0xA3 444 445 // ATMEL specific cmds 446 447 // write config reg 448 #define WCON 0x3E 449 // read config reg 450 #define RCON 0x3F 451 // supported upto 100MHz 452 #define HI_FREQ_SPI_READ 0x1B 453 454 #define ATMEL_QEN BIT(7) 455 456 // MACRONIX specific write cmds 457 458 // Address and data in quad 459 #define QUAD_PAGE_PROGRAM 0x38 460 #define DDR_DATA 16 461 #define DDR_EXTRA_BYTE 15 462 #define DDR_DUMMY 14 463 #define DDR_ADDR 13 464 #define DDR_CMD 17 465 466 #define OCTA_DDR_READ 0xEE 467 #define OCTA_DDR_READ_CMD2 0x11 468 469 #define OCTA_SDR_READ 0xEC 470 #define OCTA_SDR_READ_CMD2 0x13 471 472 // ATMEL + WINBOND specific write cmds 473 474 // Only data in quad mode 475 #define QUAD_IN_PAGE_PROGRAM 0x32 476 477 // ATMEL specific write cmds 478 479 // Data in dual 480 #define DUAL_IN_PAGE_PROGRAM 0xA2 481 482 // MICRON specific cmds 483 #define RD_LOCK_REG 0xE8 484 #define WR_LOCK_REG 0xE5 485 #define RD_FLAG_STS_REG 0x70 486 #define CLR_FLAG_STS_REG 0x50 487 #define RD_NONVOL_CON_REG 0xB5 488 #define WR_NONVOL_CON_REG 0xB1 489 #define RD_VOL_CON_REG 0x85 490 #define WR_VOL_CON_REG 0x81 491 #define RD_ENHN_VOL_CON_REG 0x65 492 #define WR_ENHN_VOL_CON_REG 0x61 493 #define DIS_XIP BIT(3) 494 #define XIP_MODE 0 495 496 // ADESTO specific cmds 497 498 #define STS_BYT2 0x31 499 #define STS_CTRL 0x71 500 501 #define ADEST_PROTECT_CMD 0x36 502 #define ADEST_UNPROTECT_CMD 0x39 503 504 // Defines for arguments 505 506 // disable hw ctrl 507 #define DIS_HW_CTRL 1 508 // donot disable hw ctrl 509 #define DNT_DIS_HW_CTRL 0 510 511 // 32bit hsize 512 #define _32BIT 3 513 // 24bit hsize is not supported, so reserved 514 // reserved 2 515 // 16bit hsize 516 #define _16BIT 1 517 // 8bit hsize 518 #define _8BIT 0 519 520 // cmd len will be 8 bits 521 #define QSPI_8BIT_LEN 8 522 // cmd + 1 byte len 523 #define QSPI_16BIT_LEN 16 524 // cmd + 24bit addr len 525 #define QSPI_32BIT_LEN 0 526 527 // OCTA_SPI_BUS_CONTROLLER2 bits 528 // initialises NONCE 529 #define NONCE_INIT BIT(1) 530 // enables global security 531 #define EN_SECURITY BIT(2) 532 // enables of sec per segment 533 #define EN_SEG_SEC 12 534 // enable qspi to use key from kh 535 #define EN_KH_KEY BIT(18) 536 537 // QSPI AES SEC KEY FROM KH bits 538 // secure key loading interval 539 #define LOAD_SEC_KEY_FRM_KH BIT(0) 540 541 // LIST OF MACRO USED 542 543 // Macro to Deassert CS 544 #define DEASSERT_CSN qspi_reg->QSPI_MANUAL_CONFIG_REG = ((qspi_reg->QSPI_MANUAL_CONFIG_REG & (~0x1FFFU)) | 0x1) 545 546 // Macro to check Quad mode 547 #define CHK_QUAD_MODE (spi_config->spi_config_1.data_mode == QUAD_MODE) 548 // Macro to check DUAL mode 549 #define CHK_DUAL_MODE (spi_config->spi_config_1.data_mode == DUAL_MODE) 550 #define CHK_OCTA_MODE (spi_config->spi_config_1.data_mode == OCTA_MODE) 551 552 // Macro to provide protection byte for SST 553 #define SST_PROTECTION ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xFF : 0) 554 // Macro to provide protection byte for WB 555 #define WB_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0x1C00 : 0) 556 // Macro to provide protection byte for MX 557 #define MX_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0x3C : 0) 558 // Macro to provide protection byte for AT 559 #define AT_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xC : 0) 560 // Macro to get the position for D2 line data 561 #define GET_POS \ 562 ((spi_config->spi_config_2.cs_no == CHIP_THREE) ? 30 \ 563 : (spi_config->spi_config_2.cs_no == CHIP_TWO) ? 26 \ 564 : (spi_config->spi_config_2.cs_no == CHIP_ONE) ? 14 \ 565 : 10) 566 567 #define GET_POS_D7_D4 \ 568 ((spi_config->spi_config_2.cs_no == CHIP_THREE) ? 24 \ 569 : (spi_config->spi_config_2.cs_no == CHIP_TWO) ? 16 \ 570 : (spi_config->spi_config_2.cs_no == CHIP_ONE) ? 8 \ 571 : 0) 572 // Macro to mask the d3 and d2 data bits 573 #define MASK_D3_D2(_POS) ~(0x3 << _POS) 574 #define MASK_D7_D4(_POS) ~(0xf << _POS) 575 // for 0xEB 0xE3 and 0xBB, 7th bit will be high so check for it 576 #define HI_PERFORMANCE_REQ (spi_config->spi_config_1.read_cmd & BIT(7)) 577 578 // Macro to trigger QSPI to read from flash 579 #ifdef CHIP_9118 580 #define READ_4M_FLASH(_NUM_BYTES, _CS_NO, Hsize) \ 581 qspi_reg->QSPI_MANUAL_CONFIG_REG = (qspi_reg->QSPI_MANUAL_CONFIG_REG & ~0xF8387FFF) | READ_TRIGGER | (_CS_NO << 13) \ 582 | ((_NUM_BYTES & 0x3FF) << 3) | (((_NUM_BYTES >> 10) & 0x1F) << 27) \ 583 | ((spi_config->spi_config_3.ddr_mode_en == 1) ? (BIT(21) | (Hsize << 19)) : 0) 584 #else 585 #define READ_4M_FLASH(_NUM_BYTES, _CS_NO, Hsize) \ 586 qspi_reg->QSPI_MANUAL_CONFIG_REG = (qspi_reg->QSPI_MANUAL_CONFIG_REG & ~0xF8387FFF) | READ_TRIGGER | (_CS_NO << 13) \ 587 | ((_NUM_BYTES & 0x3FF) << 3) | (((_NUM_BYTES >> 10) & 0x1F) << 27) \ 588 | (Hsize << 19) 589 590 #endif 591 // Macro to return A8 bit in case 9bit addressing is required 592 #define A8_BIT ((spi_config->spi_config_2.addr_width == _9BIT_ADDR) ? ((addr & BIT(8)) << 3) : 0) 593 594 // Macro to RETURN QSPI_BUS_SIZE from manual regs 595 #define QSPI_MANUAL_BUS_SIZE(_CHIP_SELECT) \ 596 (_CHIP_SELECT == CHIP_ZERO) ? ((qspi_reg->QSPI_BUS_MODE_REG & 0x6) >> 1) \ 597 : ((qspi_reg->QSPI_MANUAL_CONFIG_2_REG >> (8 + ((_CHIP_SELECT - 1) * 2))) & 0x3) 598 #ifdef CHIP_9118 599 #define QSPI_CMD_DDR_MODE \ 600 (spi_config->spi_config_2.cs_no ? (qspi_reg->QSPI_AUTO_CONFIG3_CSN1 & BIT(DDR_CMD)) \ 601 : (qspi_reg->QSPI_AUTO_CONFIG3 & BIT(DDR_CMD))) 602 #define QSPI_DATA_DDR_MODE \ 603 (spi_config->spi_config_2.cs_no ? (qspi_reg->QSPI_AUTO_CONFIG3_CSN1 & BIT(DDR_CMD)) \ 604 : (qspi_reg->QSPI_AUTO_CONFIG3 & BIT(DDR_DATA))) 605 #define QSPI_DUAL_FLASH_MODE (qspi_reg->OCTA_SPI_BUS_CONTROLLER2 & DUAL_FLASH_MODE) 606 #else 607 #define QSPI_CMD_DDR_MODE 0 608 #define QSPI_DATA_DDR_MODE 0 609 #define QSPI_DUAL_FLASH_MODE 0 610 #endif 611 // Macro to compute address width for manual mode based upon the addressing specified 612 #define ADDR_LEN (spi_config->spi_config_2.addr_width ? (spi_config->spi_config_2.addr_width * 8) : 8) 613 #define QSPI_32BIT_ADDR 32 614 #define QSPI_8BIT_ADDR 8 615 // Macro to compute address width for auto mode based upon addressing specified 616 #define AUTO_ADDR_WIDTH (((spi_config->spi_config_2.addr_width + 1) & 0x1) << 1) 617 618 // Macro to check whether the addr violates page boundary 619 #define ODD_PAGE_BOUNDARY (addr & (page_size - 1)) 620 621 // EXTRA_BYTE is currently hardcoded to 0xA0 622 #define EXTRA_BYTE ((spi_config->spi_config_1.continuous) ? 0xA0 : 0x00) 623 624 // number of dummy bytes required by the flash during a wrap/burst read command 625 #define NUM_DUMMY_BYTES_WRAP 1 626 #define PROT_FROM_TOP BIT(3) 627 628 #define HIGH_PERF_MODE BIT(1) 629 #define HSIZE_IN_BITS ((hsize + 1) * 8) 630 631 // QSPI AES Decryption Defines 632 #define KEY_LEN_128 16 633 #define KEY_LEN_256 32 634 #if defined(SLI_SI917) || defined(SLI_SI915) 635 #define CTR_MODE 0x04 636 #define XTS_MODE 0x80 637 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 638 #define IV_VALID (0xf << 16) 639 #define KEY1_VALID (0xf << 0) 640 #define KEY2_VALID (0xf << 8) 641 #else 642 #define LB_IV_VALID (0xf << 8) 643 #define KEY1_VALID_128 (0xf0 << 0) //128-bit 644 #define KEY2_VALID_128 (0xf0 << 12) //128-bit 645 #define KEY1_VALID_256 (0xff << 0) //256-bit 646 #define KEY2_VALID_256 (0xff << 12) //256-bit 647 #endif 648 #define DECRYPT_KEY_CAL BIT(9) 649 #define KEY_FLIP_FOR_REG_INTF BIT(10) 650 #define KEY_FLIP_FOR_KH_INTF BIT(11) 651 #define SR2_READ 0x35 652 #define QUAD_EN BIT(1) 653 #define EN_STANDALONE_AES BIT(15) 654 #define FLIP_IN_LB BIT(13) 655 #define QSPI_AES_DIN_READY BIT(2) 656 #define QSPI_AES_DOUT_VALID BIT(1) 657 #if defined(SLI_SI917B0) || defined(SLI_SI915) 658 #define KEY_SIZE_MASK (0x40000) 659 #define KEY_SIZE_256 BIT(16) 660 #define QSPI_KEY_SIZE_256 BIT(16) 661 662 #define DEFAULT_AES_CONFIG (0x80) 663 #define DEFAULT_AES_SEC_KEY_FRM_KH (0x9 << 1) 664 #define DEFAULT_AES_KEY_IV_VALID (0x00) 665 #endif 666 667 //XMC Flash 668 #define SR3_READ 0x15 669 #define SR1_WRITE 0x1 670 #define SR2_WRITE 0x31 671 #define SR3_WRITE 0x11 672 #endif 673 674 #ifdef __cplusplus 675 } 676 #endif 677 void initialise_m4_efuse_in_io_mode(); 678 void rsi_cmemcpy(uint8_t *dst, uint8_t *src, uint32_t len); 679 void RSI_QSPI_GPDMA_Init(uint32_t hsize, uint32_t ch_no, uint32_t mode); 680 void RSI_QSPI_GPDMA_ReadFromFifo(uint32_t src, uint32_t dst, uint32_t len, uint32_t ch_no); 681 void RSI_QSPI_ReadFromFifo(uint32_t udma_read, void *udmaHandle, void *gpdmaHandle, uint32_t ch_no); 682 void RSI_QSPI_AutoModeEn(qspi_reg_t *qspi_reg); 683 void RSI_QSPI_ConfigQspiDll(spi_config_t *spi_config, qspi_reg_t *qspi_reg); 684 void RSI_QSPI_TIMER_Config(void); 685 void qspi_semi_auto_mode_config(qspi_reg_t *qspi_reg, uint32_t addr, uint32_t hsize, uint32_t bsize, uint32_t length); 686 void RSI_QSPI_ProtectAdesto(spi_config_t *spi_config, qspi_reg_t *qspi_reg, uint32_t protection, uint32_t cs_no); 687 688 #endif // RSI_QSPI_H 689
