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Searched refs:PRS_PEEK_CH5VAL (Results 1 – 25 of 71) sorted by relevance

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/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Cur… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Cur… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_prs.h711 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_prs.h664 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b390f1024gl112.h6996 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b390f512gl112.h6996 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512il120.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512im64.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512iq100.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512iq64.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512gq100.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512gq64.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512il112.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b110f1024gm64.h7773 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b110f1024gq64.h7773 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512gl112.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512gl120.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b530f512gm64.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b510f1024gq100.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
Defm32gg12b510f1024gq64.h7804 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_prs.h921 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5… macro

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